Implement likwid across all intel + new HBM variables for SPR

Author: stephenlienharrell

docs/monitor_variable_rename_map.yaml

@@ -25,6 +25,8 @@ types:
   intel_hsw_imc: intel_x86_uncore_imc_hsw
   intel_bdw_imc: intel_x86_uncore_imc_bdw
   intel_skx_imc: intel_x86_uncore_imc_skx
+  intel_icx_imc: intel_x86_uncore_imc_icx
+  intel_spr_imc: intel_x86_uncore_imc_spr
   intel_snb_cbo: intel_x86_uncore_cbo_snb
   intel_ivb_cbo: intel_x86_uncore_cbo_ivb
   intel_hsw_cbo: intel_x86_uncore_cbo_hsw
@@ -66,6 +68,8 @@ events:
   Bounce: bounce
   CAS_READS: dram_cas_reads
   CAS_WRITES: dram_cas_writes
+  HBM_CAS_READS: hbm_cas_reads
+  HBM_CAS_WRITES: hbm_cas_writes
   CPU_CLK_UNHALTED_CORE: cycles_unhalted_core
   CPU_CLK_UNHALTED_REF: cycles_unhalted_ref
   DCGM_CPU_POWER_LIMIT_W: dcgm_cpu_power_limit_w

monitor/LIKWID_MIGRATION.md

@@ -0,0 +1,30 @@
+# LIKWID PMU migration (Intel)
+
+Intel core and uncore performance counters are collected through **LIKWID PMON**
+(`likwid_pmc_adapter.c`, `likwid_uncore_adapter.c`). Native MSR, PCI, and MMIO
+programming in legacy `intel_*` collectors has been retired behind thin wrappers.
+
+## CPU detection (`cpuid.c`)
+
+| `processor_t` | CPUID signature |
+|---------------|-----------------|
+| `CASCADE_LAKE` | `06_55` |
+| `SKYLAKE` (client) | `06_4e`, `06_5e` |
+| `ICELAKE_SERVER` | `06_6a`, `06_6c` |
+| `SAPPHIRE_RAPIDS` | `06_8f` |
+
+## Collector mapping
+
+| `st_name` | LIKWID profile | Notes |
+|-----------|----------------|-------|
+| `host_cpu_hw` | `likwid_arch_eventset_for_processor()` | Auto-disables `intel_x86_pmc_gpr4/8` when active |
+| `intel_x86_rapl` | LIKWID RAPL (`likwid_rapl.c`) | Unchanged |
+| `intel_x86_uncore_imc_{snb,ivb,hsw,bdw,skx}` | `MBOX*` / `MDEV*` CAS events | Per-MBOX device rows |
+| `intel_x86_uncore_imc_icx` | `MDEV*` DDR bytes | Ice Lake server |
+| `intel_x86_uncore_imc_spr` | `MBOX*` + `HBM*` CAS | DDR and HBM on same type |
+| `intel_x86_uncore_cbo_*`, `cha_skx`, `qpi_*`, `hau_*`, `r2pci_*` | LIKWID adapter | Auto-disable when no LIKWID event profile |
+
+## Init order
+
+`host_cpu_hw` must begin before uncore collectors so `HPMinit` / `perfmon_init`
+run first (`stats_registry.c` ordering).

monitor/README.md

@@ -44,6 +44,12 @@ Small, testable units and daemons are split along these lines (non-exhaustive):
 | Archive header / schema suffix / directive class / marks (file mode) | `stats_file_format.c`, `stats_file_format.h` (`stats_file_classify_header_directive`, `stats_file_fprint_mark_multiline`, …); orchestration in `stats_file.c`. |
 | RMQ text payloads | `stats_buffer.c` + `stats_buffer_data_append.c` (persistent AMQP; cached `uname` for header + sample lines; batched rows; declare `syslog` INFO in `DEBUG` only). |
 | DEBUG shm mirror (`@fast`/`@full` snapshots) | `stats_buffer_debug_shm.c`, `stats_buffer_debug_shm.h` (`DEBUG` builds only). |
+| Intel CPUID / generation gating | `cpuid.c`, `intel_cpuid_match.c`, `intel_processor.c` |
+| LIKWID core + uncore PMU | `likwid_pmc_adapter.c`, `likwid_uncore_adapter.c`, `likwid_uncore_profiles.c` |
+
+Intel PMU collection uses **LIKWID only** on x86 (see [LIKWID_MIGRATION.md](LIKWID_MIGRATION.md)).
+Detected generations include Cascade Lake (`06_55`), Ice Lake server (`06_6a`/`06_6c`),
+and Sapphire Rapids (`06_8f`), with SPR DDR+HBM uncore keys (`dram_*`, `hbm_*`).
 
 ## Two-tier collection (fast/slow) and sparse rows
 

monitor/configure.ac

@@ -102,6 +102,15 @@ case "$host_cpu" in
   x86_64|i?86) is_x86=true ;;
 esac
 
+likwid=false
+dcgm_checked=false
+CPU_COUNTER_BACKEND_CPPFLAG=""
+MONITOR_ARCH_CPPFLAG=""
+
+if test "x$hardware" != "xtrue"; then
+  cpu_counter_backend="none"
+  AC_MSG_NOTICE([CPU counter backend: disabled (--disable-hardware)])
+else
 if test "x$cpu_counter_backend" = "xauto"; then
   if test "x$is_x86" = "xtrue"; then
     cpu_counter_backend="likwid"
@@ -139,11 +148,7 @@ if test "x$cpu_counter_backend" = "xlikwid"; then
     esac
   fi
 fi
-AM_CONDITIONAL([LIKWID], [test x$likwid = xtrue])
-AM_CONDITIONAL([CPU_BACKEND_LIKWID], [test x$cpu_counter_backend = xlikwid])
-AM_CONDITIONAL([CPU_BACKEND_DCGM], [test x$cpu_counter_backend = xdcgm])
 
-dcgm_checked=false
 if test "x$cpu_counter_backend" = "xdcgm"; then
   if test "x$enable_all_static" = xyes; then
     save_LIBS=$LIBS
@@ -168,9 +173,14 @@ if test "x$cpu_counter_backend" = "xdcgm"; then
   dcgm_checked=true
   CPU_COUNTER_BACKEND_CPPFLAG="-DMONITOR_CPU_BACKEND_DCGM"
   MONITOR_ARCH_CPPFLAG=""
-else
+elif test "x$cpu_counter_backend" = "xlikwid"; then
   CPU_COUNTER_BACKEND_CPPFLAG="-DMONITOR_CPU_BACKEND_LIKWID"
 fi
+
+if test "x$hardware" = "xtrue"; then
+  AC_MSG_NOTICE([CPU counter backend: ${cpu_counter_backend} (host_cpu=${host_cpu})])
+fi
+fi
 AC_SUBST([CPU_COUNTER_BACKEND_CPPFLAG])
 
 AC_ARG_WITH([monitor-arch],
@@ -207,7 +217,11 @@ case "$host_cpu" in
 esac
 AM_CONDITIONAL([MONITOR_ARCH_ARM], [test x$monitor_arch_arm = xtrue])
 
-AC_MSG_NOTICE([CPU counter backend: ${cpu_counter_backend} (host_cpu=${host_cpu})])
+AM_CONDITIONAL([LIKWID], [test x$likwid = xtrue])
+AM_CONDITIONAL([CPU_BACKEND_LIKWID],
+  [test x$hardware = xtrue -a x$cpu_counter_backend = xlikwid])
+AM_CONDITIONAL([CPU_BACKEND_DCGM],
+  [test x$hardware = xtrue -a x$cpu_counter_backend = xdcgm])
 
 AC_ARG_ENABLE([infiniband],
 [  --enable-infiniband	Enable Infiniband support (default is true)],
@@ -432,6 +446,30 @@ AS_IF([test "x$with_systemduserunitdir" != "xno"],
       [AC_SUBST([systemduserunitdir], [$with_systemduserunitdir])])
 AM_CONDITIONAL([HAVE_SYSTEMD], [test "x$with_systemduserunitdir" != "xno"])
 
+MONITOR_FEATURE_CPPFLAGS=""
+if test "x$hardware" = "xtrue"; then
+  MONITOR_FEATURE_CPPFLAGS="$MONITOR_FEATURE_CPPFLAGS -DMONITOR_WITH_HARDWARE"
+fi
+if test "x$infiniband" = "xtrue"; then
+  MONITOR_FEATURE_CPPFLAGS="$MONITOR_FEATURE_CPPFLAGS -DMONITOR_WITH_INFINIBAND"
+fi
+if test "x$lustre" = "xtrue"; then
+  MONITOR_FEATURE_CPPFLAGS="$MONITOR_FEATURE_CPPFLAGS -DMONITOR_WITH_LUSTRE"
+fi
+if test "x$gpu" = "xtrue"; then
+  MONITOR_FEATURE_CPPFLAGS="$MONITOR_FEATURE_CPPFLAGS -DMONITOR_WITH_GPU"
+fi
+if test "x$amd_gpu" = "xtrue"; then
+  MONITOR_FEATURE_CPPFLAGS="$MONITOR_FEATURE_CPPFLAGS -DMONITOR_WITH_AMD_GPU"
+fi
+if test "x$opa" = "xtrue"; then
+  MONITOR_FEATURE_CPPFLAGS="$MONITOR_FEATURE_CPPFLAGS -DMONITOR_WITH_OPA"
+fi
+if test "x$monitor_arch_arm" = "xtrue"; then
+  MONITOR_FEATURE_CPPFLAGS="$MONITOR_FEATURE_CPPFLAGS -DMONITOR_HOST_IS_ARM"
+fi
+AC_SUBST([MONITOR_FEATURE_CPPFLAGS])
+
 AC_CONFIG_FILES([Makefile src/Makefile tests/Makefile])
 AC_OUTPUT
 

monitor/scripts/cross_compile_test.sh

@@ -1048,7 +1048,6 @@ foreign_monitor_cfg_args() {
   local args=(
     --disable-all-static
     --with-systemduserunitdir=no
-    --with-cpu-counter-backend=auto
     --disable-gpu
     --disable-amd-gpu
     --disable-infiniband
@@ -1058,7 +1057,10 @@ foreign_monitor_cfg_args() {
 
   # Under emulation, /proc/cpuinfo may reflect host details. Keep x86 deterministic.
   if is_x86_triplet "${target}"; then
-    args+=(--with-monitor-arch=intel)
+    args+=(--with-monitor-arch=intel --with-cpu-counter-backend=auto)
+  else
+    # Non-x86 foreign smoke has no LIKWID and usually no libdcgm in the sysroot.
+    args+=(--disable-hardware)
   fi
   printf '%s\n' "${args[@]}"
 }

monitor/src/Makefile.am

@@ -31,6 +31,7 @@ hpcperfstatsd_CPPFLAGS = \
 	-DSTATS_LOCK_PATH=\"$(STATS_LOCK_PATH)\" \
 	-DJOBID_FILE_PATH=\"$(JOBID_FILE_PATH)\" \
 	@CPU_COUNTER_BACKEND_CPPFLAG@ \
+	@MONITOR_FEATURE_CPPFLAGS@ \
 	@METRIC_PROFILER_CPPFLAG@ \
 	@METRIC_PROFILER_BACKEND_CPPFLAG@
 
@@ -59,6 +60,10 @@ hpcperfstatsd_SOURCES = \
 	collect_tier.c \
 	cpuid.h \
 	cpuid.c \
+	intel_cpuid_match.h \
+	intel_cpuid_match.c \
+	intel_processor.h \
+	intel_processor.c \
 	daemonize.h \
 	daemonize.c \
 	monitor_log.h \
@@ -200,6 +205,8 @@ TYPES 	+= \
 	intel_bdw_cbo.c \
 	intel_bdw_hau.c \
 	intel_bdw_imc.c \
+	intel_icx_imc.c \
+	intel_spr_imc.c \
 	intel_bdw_qpi.c \
 	intel_bdw_r2pci.c \
 	intel_hsw_cbo.c \
@@ -259,7 +266,15 @@ hpcperfstatsd_SOURCES += \
 	likwid_pmc_adapter.h \
 	likwid_pmc_adapter.c \
 	likwid_arch_map.h \
-	likwid_arch_map.c
+	likwid_arch_map.c \
+	likwid_uncore_adapter.h \
+	likwid_uncore_adapter.c \
+	likwid_uncore_profiles.h \
+	likwid_uncore_profiles.c \
+	intel_skx_imc.h \
+	intel_icx_imc.h \
+	intel_spr_imc.h \
+	intel_snb_imc.h
 endif
 
 if INFINIBAND

monitor/src/cpu_counter_metrics_likwid_begin.c

@@ -13,6 +13,7 @@
 #include "cpu_counter_metrics_likwid_begin.h"
 
 #ifndef MONITOR_CPU_BACKEND_DCGM
+#include "cpuid.h"
 #include "likwid_pmc_adapter.h"
 #include "likwid_arch_map.h"
 
@@ -22,7 +23,8 @@ int likwid_backend_begin(struct stats_type *type)
 {
   (void)type;
   if (likwid_pmc_adapter_init(nr_cpus) == 0 &&
-      likwid_pmc_adapter_setup_events(likwid_arch_eventset()) == 0) {
+      likwid_pmc_adapter_setup_events(
+          likwid_arch_eventset_for_processor(processor, n_pmcs)) == 0) {
     g_likwid_ready = 1;
     return 0;
   }

monitor/src/cpuid.c

@@ -9,6 +9,7 @@
 #include "trace.h"
 #include "path_open_fail_once.h"
 #include "cpuid.h"
+#include "intel_cpuid_match.h"
 
 #if defined(__i386__) || defined(__x86_64__)
 
@@ -48,52 +49,10 @@ processor_t signature(int *n_pmcs) {
     *n_pmcs = (eax >> 8) & 0xFF;
     TRACE("Number of PMCs = %d\n", *n_pmcs);
 
-    if (strncmp(sig, "06_1a", 5) == 0 ||
-        strncmp(sig, "06_1e", 5) == 0 ||
-        strncmp(sig, "06_2e", 5) == 0) {
-      TRACE("Nehalem %s\n", sig);
-      return NEHALEM;
-    }
-
-    if (strncmp(sig, "06_25", 5) == 0 ||
-        strncmp(sig, "06_2c", 5) == 0 ||
-        strncmp(sig, "06_2f", 5) == 0) {
-      TRACE("Westmere %s\n", sig);
-      return WESTMERE;
-    }
-
-    if (strncmp(sig, "06_3a", 5) == 0 ||
-        strncmp(sig, "06_3e", 5) == 0) {
-      TRACE("Ivy Bridge %s\n", sig);
-      return IVYBRIDGE;
-    }
-
-    if (strncmp(sig, "06_2a", 5) == 0 ||
-        strncmp(sig, "06_2d", 5) == 0) {	
-      TRACE("Sandy Bridge %s\n", sig);
-      return SANDYBRIDGE;
-    }
-
-    if (strncmp(sig, "06_3c", 5) == 0 ||
-        strncmp(sig, "06_45", 5) == 0 ||
-        strncmp(sig, "06_46", 5) == 0 ||
-        strncmp(sig, "06_3f", 5) == 0) {
-      TRACE("Haswell %s\n", sig);
-      return HASWELL;
-    }
-
-    if (strncmp(sig, "06_3d", 5) == 0 ||
-        strncmp(sig, "06_47", 5) == 0 ||
-        strncmp(sig, "06_4f", 5) == 0) {
-      TRACE("Broadwell %s %d\n", sig);
-      return BROADWELL;
-    }
-
-    if (strncmp(sig, "06_55", 5) == 0 ||
-        strncmp(sig, "06_4e", 5) == 0 ||
-        strncmp(sig, "06_5e", 5) == 0) {
-      TRACE("Skylake %s\n", sig);
-      return SKYLAKE;
+    rc = intel_cpuid_sig_to_processor(vendor, sig);
+    if (rc != (processor_t)-1) {
+      TRACE("Intel processor sig %s -> %d\n", sig, (int)rc);
+      return rc;
     }
   }
   else if (strncmp(vendor, "AuthenticAMD", 12) == 0) {

monitor/src/cpuid.h

@@ -8,7 +8,10 @@ typedef enum {
   NEHALEM, WESTMERE, 
   SANDYBRIDGE, IVYBRIDGE, 
   HASWELL, BROADWELL,
-  SKYLAKE
+  SKYLAKE,
+  CASCADE_LAKE,
+  ICELAKE_SERVER,
+  SAPPHIRE_RAPIDS
 } processor_t;
 
 // Return 1 for true and 0 for false

monitor/src/intel_4pmc3.c

@@ -13,6 +13,7 @@
 
 #include "intel_pmc3.h"
 #include "intel_pmc3_core.h"
+#include "cpu_counter_metrics_likwid_begin.h"
 #include "stats.h"
 #include "trace.h"
 #include "msr_io.h"
@@ -62,6 +63,10 @@ static void intel_4pmc3_collect(struct stats_type *type)
 
 static int intel_4pmc3_begin(struct stats_type *type)
 {
+  if (cpu_counter_metrics_likwid_ready()) {
+    type->st_enabled = 0;
+    return -1;
+  }
   return intel_pmc3_core_begin_if_pmcs(type, 4);
 }