Finishing up likwid conversion and retiring all pre-skx intel architectures.

Author: stephenlienharrell

docs/monitor_variable_rename_map.yaml

@@ -20,31 +20,10 @@ types:
   amd64_df: amd_x86_uncore_df
   amd64_rapl: amd_x86_rapl
   intel_rapl: intel_x86_rapl
-  intel_snb_imc: intel_x86_uncore_imc_snb
-  intel_ivb_imc: intel_x86_uncore_imc_ivb
-  intel_hsw_imc: intel_x86_uncore_imc_hsw
-  intel_bdw_imc: intel_x86_uncore_imc_bdw
   intel_skx_imc: intel_x86_uncore_imc_skx
   intel_icx_imc: intel_x86_uncore_imc_icx
   intel_spr_imc: intel_x86_uncore_imc_spr
-  intel_snb_cbo: intel_x86_uncore_cbo_snb
-  intel_ivb_cbo: intel_x86_uncore_cbo_ivb
-  intel_hsw_cbo: intel_x86_uncore_cbo_hsw
-  intel_bdw_cbo: intel_x86_uncore_cbo_bdw
   intel_skx_cha: intel_x86_uncore_cha_skx
-  intel_snb_qpi: intel_x86_uncore_qpi_snb
-  intel_ivb_qpi: intel_x86_uncore_qpi_ivb
-  intel_hsw_qpi: intel_x86_uncore_qpi_hsw
-  intel_bdw_qpi: intel_x86_uncore_qpi_bdw
-  intel_snb_hau: intel_x86_uncore_hau_snb
-  intel_ivb_hau: intel_x86_uncore_hau_ivb
-  intel_hsw_hau: intel_x86_uncore_hau_hsw
-  intel_bdw_hau: intel_x86_uncore_hau_bdw
-  intel_snb_r2pci: intel_x86_uncore_r2pci_snb
-  intel_ivb_r2pci: intel_x86_uncore_r2pci_ivb
-  intel_hsw_r2pci: intel_x86_uncore_r2pci_hsw
-  intel_bdw_r2pci: intel_x86_uncore_r2pci_bdw
-  intel_pcu: intel_x86_pcu
   arm_imc: arm_aarch64_imc
   ib: host_ib
   ib_ext: host_ib
@@ -68,6 +47,7 @@ events:
   Bounce: bounce
   CAS_READS: dram_cas_reads
   CAS_WRITES: dram_cas_writes
+  CPU_PEAK_HBM_BW_BYTES_PER_S: cpu_peak_hbm_bw_bytes_per_s
   HBM_CAS_READS: hbm_cas_reads
   HBM_CAS_WRITES: hbm_cas_writes
   CPU_CLK_UNHALTED_CORE: cycles_unhalted_core
@@ -148,10 +128,6 @@ events:
   tx_bytes: sw_tx_bytes
   rx_packets: sw_rx_packets
   tx_packets: sw_tx_packets
-file_event_overrides:
-  intel_pcu.c:
-    instr_retired: pcu_ctr0
-    aperf: pcu_ctr1
 host_mem_aliases:
   MemTotal: mem_total
   MemFree: mem_free

monitor/LIKWID_MIGRATION.md

@@ -4,6 +4,15 @@ Intel core and uncore performance counters are collected through **LIKWID PMON**
 (`likwid_pmc_adapter.c`, `likwid_uncore_adapter.c`). Native MSR, PCI, and MMIO
 programming in legacy `intel_*` collectors has been retired behind thin wrappers.
 
+## Supported generations (SKX+)
+
+Intel uncore collectors and LIKWID uncore profiles target **Skylake-X / Cascade
+Lake**, **Ice Lake server**, and **Sapphire Rapids** only.
+
+**Retired (no longer classified or registered):** Sandybridge, Ivybridge,
+Haswell, Broadwell — including `intel_x86_pcu` MSR PCU and all
+`intel_x86_uncore_*_{snb,ivb,hsw,bdw}` types (IMC, CBO, QPI, HAU, R2PCI).
+
 ## CPU detection (`cpuid.c`)
 
 | `processor_t` | CPUID signature |
@@ -13,16 +22,22 @@ programming in legacy `intel_*` collectors has been retired behind thin wrappers
 | `ICELAKE_SERVER` | `06_6a`, `06_6c` |
 | `SAPPHIRE_RAPIDS` | `06_8f` |
 
+Signatures for SNB/IVB/HSW/BDW (`06_2a`, `06_3a`, `06_3c`, `06_3d`, …) return
+unsupported (`processor_t`-1).
+
 ## Collector mapping
 
 | `st_name` | LIKWID profile | Notes |
 |-----------|----------------|-------|
 | `host_cpu_hw` | `likwid_arch_eventset_for_processor()` | Auto-disables `intel_x86_pmc_gpr4/8` when active |
 | `intel_x86_rapl` | LIKWID RAPL (`likwid_rapl.c`) | Unchanged |
-| `intel_x86_uncore_imc_{snb,ivb,hsw,bdw,skx}` | `MBOX*` / `MDEV*` CAS events | Per-MBOX device rows |
-| `intel_x86_uncore_imc_icx` | `MDEV*` DDR bytes | Ice Lake server |
-| `intel_x86_uncore_imc_spr` | `MBOX*` + `HBM*` CAS | DDR and HBM on same type |
-| `intel_x86_uncore_cbo_*`, `cha_skx`, `qpi_*`, `hau_*`, `r2pci_*` | LIKWID adapter | Auto-disable when no LIKWID event profile |
+| `intel_x86_uncore_imc_skx` | `IMC_SKX` (`MBOX*` CAS) | Cascade Lake / SKX server |
+| `intel_x86_uncore_imc_icx` | `IMC_ICX` (`MDEV*` DDR bytes) | Ice Lake server |
+| `intel_x86_uncore_imc_spr` | `IMC_SPR` (`MBOX*` + `HBM*` CAS) | DDR and HBM on same type |
+| `intel_x86_uncore_cha_skx` | `CHA_SKX` (`CBOX*` LLC events) | Trimmed CBOX subset from `skylakeX/CACHES.txt` |
+
+Counter-name → device/key mapping is exercised by `test_likwid_uncore_adapter.c`
+via `likwid_uncore_adapter_emit_counter()`.
 
 ## Init order
 

monitor/README.md

@@ -48,8 +48,12 @@ Small, testable units and daemons are split along these lines (non-exhaustive):
 | LIKWID core + uncore PMU | `likwid_pmc_adapter.c`, `likwid_uncore_adapter.c`, `likwid_uncore_profiles.c` |
 
 Intel PMU collection uses **LIKWID only** on x86 (see [LIKWID_MIGRATION.md](LIKWID_MIGRATION.md)).
-Detected generations include Cascade Lake (`06_55`), Ice Lake server (`06_6a`/`06_6c`),
-and Sapphire Rapids (`06_8f`), with SPR DDR+HBM uncore keys (`dram_*`, `hbm_*`).
+**Uncore collectors (IMC/CHA)** target SKX+ server parts only: Cascade Lake
+(`06_55`), Ice Lake server (`06_6a`/`06_6c`), and Sapphire Rapids (`06_8f`).
+Sandybridge, Ivybridge, Haswell, and Broadwell are no longer classified or
+registered (`intel_x86_pcu` and pre-SKX uncore types removed). SPR exposes DDR
+and HBM uncore keys (`dram_*`, `hbm_*`); `host_roofline_peak` adds
+`cpu_peak_hbm_bw_bytes_per_s` (EDAC HBM/DDR split, `peak_calc_version` 2).
 
 ## Two-tier collection (fast/slow) and sparse rows
 

monitor/src/Makefile.am

@@ -202,31 +202,10 @@ TYPES 	+= \
 	intel_pmc3_core.c \
 	intel_uncore_msr_box.c \
 	intel_uncore_pci.c \
-	intel_bdw_cbo.c \
-	intel_bdw_hau.c \
-	intel_bdw_imc.c \
 	intel_icx_imc.c \
 	intel_spr_imc.c \
-	intel_bdw_qpi.c \
-	intel_bdw_r2pci.c \
-	intel_hsw_cbo.c \
-	intel_hsw_hau.c \
-	intel_hsw_imc.c \
-	intel_hsw_qpi.c \
-	intel_hsw_r2pci.c \
-	intel_ivb_cbo.c \
-	intel_ivb_hau.c \
-	intel_ivb_imc.c \
-	intel_ivb_qpi.c \
-	intel_ivb_r2pci.c \
-	intel_pcu.c \
 	intel_skx_cha.c \
-	intel_skx_imc.c \
-	intel_snb_cbo.c \
-	intel_snb_hau.c \
-	intel_snb_imc.c \
-	intel_snb_qpi.c \
-	intel_snb_r2pci.c
+	intel_skx_imc.c
 hpcperfstatsd_SOURCES += \
 	amd64_event_tables.h \
 	amd64_event_tables.c \
@@ -273,8 +252,7 @@ hpcperfstatsd_SOURCES += \
 	likwid_uncore_profiles.c \
 	intel_skx_imc.h \
 	intel_icx_imc.h \
-	intel_spr_imc.h \
-	intel_snb_imc.h
+	intel_spr_imc.h
 endif
 
 if INFINIBAND

monitor/src/intel_bdw_cbo.c

@@ -19,25 +19,6 @@ processor_t intel_cpuid_sig_to_processor(const char *vendor, const char *sig)
       strncmp(sig, "06_2f", 5) == 0)
     return WESTMERE;
 
-  if (strncmp(sig, "06_3a", 5) == 0 ||
-      strncmp(sig, "06_3e", 5) == 0)
-    return IVYBRIDGE;
-
-  if (strncmp(sig, "06_2a", 5) == 0 ||
-      strncmp(sig, "06_2d", 5) == 0)
-    return SANDYBRIDGE;
-
-  if (strncmp(sig, "06_3c", 5) == 0 ||
-      strncmp(sig, "06_45", 5) == 0 ||
-      strncmp(sig, "06_46", 5) == 0 ||
-      strncmp(sig, "06_3f", 5) == 0)
-    return HASWELL;
-
-  if (strncmp(sig, "06_3d", 5) == 0 ||
-      strncmp(sig, "06_47", 5) == 0 ||
-      strncmp(sig, "06_4f", 5) == 0)
-    return BROADWELL;
-
   if (strncmp(sig, "06_4e", 5) == 0 ||
       strncmp(sig, "06_5e", 5) == 0)
     return SKYLAKE;