[Z80A] Correct Tw cycles for IO

The Z80 should only be sampling the /WAIT pin during the 3rd cycle T of an IO REQ M Cycle.
Instruction timing tests verified on CPCHawk using WinAPE plustest.dsk.

Note: CPCHawk is the only core to currently use the Z80A /WAIT pin (FlagW), so other core exposure is 0.

Author: Asnivor

src/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Direct.cs

@@ -515,7 +515,7 @@ private void OUT_()
 						WAIT,
 						RD_INC, Z, PCl, PCh,
 						TR, ALU, A,
-						WAIT,
+						IDLE,
 						WAIT,
 						OUT_INC, Z, ALU, A);
 
@@ -530,7 +530,7 @@ private void OUT_REG_(ushort dest, ushort src)
 					(IDLE,
 						TR16, Z, W, C, B,
 						IDLE,
-						IDLE,
+						WAIT,
 						OUT_INC, Z, W, src);
 
 			PopulateBUSRQ(0, BIO1, BIO2, BIO3, BIO4);
@@ -546,7 +546,7 @@ private void IN_()
 						WAIT,
 						RD_INC, Z, PCl, PCh,
 						IDLE,
-						WAIT,
+						IDLE,
 						WAIT,
 						IN_A_N_INC, A, Z, W);
 
@@ -560,7 +560,7 @@ private void IN_REG_(ushort dest, ushort src)
 			PopulateCURINSTR
 					(IDLE,
 						TR16, Z, W, C, B,
-						WAIT,
+						IDLE,
 						WAIT,
 						IN_INC, dest, Z, W);
 

src/BizHawk.Emulation.Cores/CPUs/Z80A/Tables_Indirect.cs

@@ -461,7 +461,7 @@ private void IN_OP_R(ushort operation, ushort repeat_instr)
 					(IDLE,
 						IDLE,
 						IDLE,
-						WAIT,
+						IDLE,
 						WAIT,
 						IN, ALU, C, B,
 						IDLE,
@@ -482,7 +482,7 @@ private void OUT_OP_R(ushort operation, ushort repeat_instr)
 						WAIT,
 						RD, ALU, L, H,
 						IDLE,
-						WAIT,
+						IDLE,
 						WAIT,
 						REP_OP_O, C, B, ALU, operation, 3, operation, repeat_instr);
 

src/BizHawk.Emulation.Cores/Computers/AmstradCPC/readme.md

@@ -52,31 +52,7 @@ Unknown
 
 #### Test 5: Instruction timing test
 
-| Prefix | OPC | Inst. | Comments |
-|:----:|:----:|:-----:|:------------:|
-|NONE| D3:4 | OUT A |				|
-|NONE| DB:4 | IN A  |				|
-|NONE| D3:5 | OUT A |				|	
-|NONE| DB:5 | IN A  |				|
-|ED| 41:3 | OUT (C), B     |              |
-|ED| 49:3 | OUT (C), C      |              |
-|ED| 51:3 | OUT (C), D       |              |
-|ED| 59:3 | OUT (C), E      |              |
-|ED| 61:3 | OUT (C), H      |              |
-|ED| 69:3 | OUT (C), L      |              |
-|ED| 71:3 | OUT (C), 0      |              |
-|ED| 79:3 | OUT (C), A      |              |
-|ED| A2:6 | INI      |              |
-|ED| A3:6 | OUTI      |              |
-|ED| AA:6 | IND      |              |
-|ED| B2:7/6| INIR     |              |
-|ED| B3:7/6| OTIR     |              |
-|ED| BA:7/6| INDR    |              |
-|ED| BB:7/6| OTDR    |              |
-|DD CB| D3:5| SET 2, (ix+d), e    |              |
-|DD CB| DB:5| SET 3, (ix+d), e    |              |
-
-Everything else passes. Almost certainly the problems observed relate to IO timing.
+All tests passing
 
 #### Test 6: Register 0 test
 Unknown