FPGA-Project-Train-Controller/Tcontrol.tan.summary at master · TabbieD/FPGA-Project-Train-Controller · GitHub

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.280 ns
From           : sensor4
To             : state.ABout
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.266 ns
From           : state.Bin
To             : entry_B
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.744 ns
From           : sensor3
To             : sensor_3
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.124 ns
From           : sensor3
To             : state.Astop
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 420.17 MHz ( period = 2.380 ns )
From           : state.Ain
To             : state.ABout
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          :
Required Time  :
Actual Time    :
From           :
To             :
From Clock     :
To Clock       :
Failed Paths   : 0

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