Verify Setup Issue

[shotaminato]

Describe the bug

All items in “Verify Setup” pass, but it still shows “Some checks failed.”

2026-03-21 12:54:27.610 [info] 
*************************************************
Checking general configuration (https://terostechnology.github.io/terosHDLdoc/docs/category/installation-checklist) 
❌ Some checks failed ❌
*************************************************
⊙ Checking make. This tool is used to run some external tools. Current configured installation path: ""
  🔎 Searching for the binary "make" in the system path
  ✅ make Found in the system path using the command: "make --version"
🎉 The make installation path is correctly configured.


⊙ Checking Python installation. Configured installation path: "~/HOME/tool/python/.py_venv/bin/python3"
  ✅ Python was found in the path "~/HOME/tool/python/.py_venv/bin/python3". Tried to find it using the command: "~/HOME/tool/python/.py_venv/bin/python3 -c "import sys; check_version = sys.version_info >         (3,0); exit(0) if check_version == True else exit(-1)""
🎉 Python installation path is correctly configured. Using "/home/shota/HOME/tool/python/.py_venv/bin/python3"


⊙ Checking Python dependencies. Current configured installation path: "~/HOME/tool/python/.py_venv/bin/python3"
  🎉 vunit found.
  🎉 edalize found.
  🎉 cocotb (optional) found.
  🎉 vsg (optional) found.
*************************************************
Checking Linter configuration (https://terostechnology.github.io/terosHDLdoc/docs/guides/linter) 
🎉 Correctly configured 🎉🎉
*************************************************
⊙ Linter errors for VHDL is disabled. Skipping configuration check.


⊙ Checking linter errors with verilator for Verilog/SV. Current configured installation path: "~/HOME/tool/YosysHQ/oss-cad-suite/bin/"
  🔎 Searching for the binary Verilator at "~/HOME/tool/YosysHQ/oss-cad-suite/bin//verilator"
  ✅ Verilator found at "~/HOME/tool/YosysHQ/oss-cad-suite/bin//verilator" using the command: "~/HOME/tool/YosysHQ/oss-cad-suite/bin//verilator --version"
🎉 The linter installation path is correctly configured.


⊙ Linter style for VHDL is disabled. Skipping configuration check.


⊙ Checking linter style with verible for Verilog/SV. Current configured installation path: "~/HOME/tool/verible/verible-v0.0-4007-g98bdb38a/bin/"
  🔎 Searching for the binary Verible at "~/HOME/tool/verible/verible-v0.0-4007-g98bdb38a/bin//verible-verilog-lint"
  ✅ Verible found at "~/HOME/tool/verible/verible-v0.0-4007-g98bdb38a/bin//verible-verilog-lint" using the command: "~/HOME/tool/verible/verible-v0.0-4007-g98bdb38a/bin//verible-verilog-lint --version"
🎉 The linter installation path is correctly configured.


*************************************************
Checking External Tool Configuration (https://terostechnology.github.io/terosHDLdoc/docs/external_tools/) 
🎉 Correctly configured 🎉🎉
*************************************************
⊙ Selected external tool: GHDL. Installation path: "~/HOME/tool/YosysHQ/oss-cad-suite/bin/"
  🔎 Searching for the binary ghdl at "~/HOME/tool/YosysHQ/oss-cad-suite/bin//ghdl"
  ✅ ghdl found at "~/HOME/tool/YosysHQ/oss-cad-suite/bin//ghdl" using the command: "~/HOME/tool/YosysHQ/oss-cad-suite/bin//ghdl --version"
🎉 The GHDL installation path is correctly configured.

⊙ Execution mode: CMD. The tool will be executend in the command line.

⊙ Waveform viewer: TOOL. Built-in tool waveform viewer will be opened after the simulation if it is available.

*************************************************
Checking Formatter configuration (https://terostechnology.github.io/terosHDLdoc/docs/guides/formatter) 
🎉 Correctly configured 🎉🎉
*************************************************
⊙ Checking formatter standalone for VHDL.
  The formatter is built into TerosHDL. Skipping configuration check.
🎉 The linter installation path is correctly configured.


⊙ Checking formatter istyle for Verilog/SV.
  The formatter is built into TerosHDL. Skipping configuration check.
🎉 The linter installation path is correctly configured.


*************************************************
Checking Schematic configuration (https://terostechnology.github.io/terosHDLdoc/docs/guides/schematic_viewer/installation) 
🎉 Correctly configured 🎉🎉
*************************************************
⊙ Selected backend: yowasp with installation path: "". This backend doesn't support VHDL files.
  🔎 Searching for the binary yowasp at "~/HOME/tool/python/.py_venv/bin//yowasp-yosys"
  ✅ yowasp found at "~/HOME/tool/python/.py_venv/bin//yowasp-yosys" using the command: "~/HOME/tool/python/.py_venv/bin//yowasp-yosys --version"
🎉 The Schematic Backend installation path is correctly configured.

To Reproduce
Follow the instruction: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/TerosHDL%20installation
Using python 3.12 virtual environment.

Please complete the following information:

• OS: Ubuntu 22.04 WSL2
• Cursor version
  Version: 2.6.19 (user setup)
  VSCode Version: 1.105.1
  Commit: 224838f96445be37e3db643a163a817c15b36060
  Date: 2026-03-12T04:07:27.435Z
  Build Type: Stable
  Release Track: Default
  Electron: 39.4.0
  Chromium: 142.0.7444.265
  Node.js: 22.22.0
  V8: 14.2.231.22-electron.0
  OS: Windows_NT x64 10.0.26200