Enhancement: Add icons to source files

package.json

@@ -38,6 +38,13 @@
     },
 
     "contributes": {
+        "iconThemes": [
+            {
+                "id": "teroshdl-icons",
+                "label": "TerosHDL File Icons",
+                "path": "./resources/icon/teroshdl-icon-theme.json"
+            }
+        ],
         "viewsContainers": {
             "activitybar": [
                 {
@@ -892,7 +899,18 @@
                 "mac": "command+delete",
                 "when": "editorTextFocus"
             }
-        ]
+        ],
+
+        "configuration": {
+            "title": "TerosHDL",
+            "properties": {
+                "teroshdl.fileIcons.enabled": {
+                    "type": "boolean",
+                    "default": true,
+                    "markdownDescription": "Enable TerosHDL file icons. To apply changes:\n1. Open Command Palette (Ctrl+Shift+P)\n2. Type 'File Icon Theme'\n3. Select 'TerosHDL File Icons' to enable or 'None' to disable"
+                }
+            }
+        }
     },
 
     "scripts": {

resources/icon/teroshdl-icon-theme.json

@@ -0,0 +1,122 @@
+{
+  "iconDefinitions": {
+    "_vhdl_file": {
+      "iconPath": "./light/vhdl.svg"
+    },
+    "_vhdl_file_dark": {
+      "iconPath": "./dark/vhdl.svg"
+    },
+    "_verilog_file": {
+      "iconPath": "./light/verilog.svg"
+    },
+    "_verilog_file_dark": {
+      "iconPath": "./dark/verilog.svg"
+    },
+    "_systemverilog_file": {
+      "iconPath": "./light/systemverilog.svg"
+    },
+    "_systemverilog_file_dark": {
+      "iconPath": "./dark/systemverilog.svg"
+    },
+    "_tcl_file": {
+      "iconPath": "./light/tcl.svg"
+    },
+    "_tcl_file_dark": {
+      "iconPath": "./dark/tcl.svg"
+    },
+    "_xdc_file": {
+      "iconPath": "./light/xdc.svg"
+    },
+    "_xdc_file_dark": {
+      "iconPath": "./dark/xdc.svg"
+    },
+    "_ucf_file": {
+      "iconPath": "./light/ucf.svg"
+    },
+    "_ucf_file_dark": {
+      "iconPath": "./dark/ucf.svg"
+    }
+  },
+  "fileExtensions": {
+    "vhd": "_vhdl_file",
+    "vhdl": "_vhdl_file",
+    "vho": "_vhdl_file",
+    "v": "_verilog_file",
+    "vh": "_verilog_file",
+    "vl": "_verilog_file",
+    "sv": "_systemverilog_file",
+    "svh": "_systemverilog_file",
+    "tcl": "_tcl_file",
+    "pro": "_tcl_file",
+    "xdc": "_xdc_file",
+    "sdc": "_xdc_file",
+    "ldc": "_xdc_file",
+    "pdc": "_xdc_file",
+    "ucf": "_ucf_file"
+  },
+  "languageIds": {
+    "vhdl": "_vhdl_file",
+    "verilog": "_verilog_file",
+    "systemverilog": "_systemverilog_file",
+    "tcl": "_tcl_file",
+    "xdc": "_xdc_file",
+    "ldc": "_xdc_file",
+    "ucf": "_ucf_file"
+  },
+  "light": {
+    "fileExtensions": {
+      "vhd": "_vhdl_file",
+      "vhdl": "_vhdl_file",
+      "vho": "_vhdl_file",
+      "v": "_verilog_file",
+      "vh": "_verilog_file",
+      "vl": "_verilog_file",
+      "sv": "_systemverilog_file",
+      "svh": "_systemverilog_file",
+      "tcl": "_tcl_file",
+      "pro": "_tcl_file",
+      "xdc": "_xdc_file",
+      "sdc": "_xdc_file",
+      "ldc": "_xdc_file",
+      "pdc": "_xdc_file",
+      "ucf": "_ucf_file"
+    },
+    "languageIds": {
+      "vhdl": "_vhdl_file",
+      "verilog": "_verilog_file",
+      "systemverilog": "_systemverilog_file",
+      "tcl": "_tcl_file",
+      "xdc": "_xdc_file",
+      "ldc": "_xdc_file",
+      "ucf": "_ucf_file"
+    }
+  },
+  "highContrast": {
+    "fileExtensions": {
+      "vhd": "_vhdl_file_dark",
+      "vhdl": "_vhdl_file_dark",
+      "vho": "_vhdl_file_dark",
+      "v": "_verilog_file_dark",
+      "vh": "_verilog_file_dark",
+      "vl": "_verilog_file_dark",
+      "sv": "_systemverilog_file_dark",
+      "svh": "_systemverilog_file_dark",
+      "tcl": "_tcl_file_dark",
+      "pro": "_tcl_file_dark",
+      "xdc": "_xdc_file_dark",
+      "sdc": "_xdc_file_dark",
+      "ldc": "_xdc_file_dark",
+      "pdc": "_xdc_file_dark",
+      "ucf": "_ucf_file_dark"
+    },
+    "languageIds": {
+      "vhdl": "_vhdl_file_dark",
+      "verilog": "_verilog_file_dark",
+      "systemverilog": "_systemverilog_file_dark",
+      "tcl": "_tcl_file_dark",
+      "xdc": "_xdc_file_dark",
+      "ldc": "_xdc_file_dark",
+      "ucf": "_ucf_file_dark"
+    }
+  }
+}