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| 1 | +.. _am62l_standby_mode: |
| 2 | + |
| 3 | +################## |
| 4 | +AM62L Standby Mode |
| 5 | +################## |
| 6 | + |
| 7 | +******** |
| 8 | +Overview |
| 9 | +******** |
| 10 | + |
| 11 | +Unlike system suspend modes that require explicit user intervention, Standby Mode operates transparently |
| 12 | +during normal system operation. The system continuously evaluates the idle state of processor clusters and |
| 13 | +automatically adjusts clock frequencies, disables non-critical power domains, and enables DDR auto-self-refresh |
| 14 | +when all cores are idle. On receiving an interrupt, quickly restores full operational state. |
| 15 | + |
| 16 | +Key characteristics of this opportunistic approach: |
| 17 | + |
| 18 | +* **Automatic Operation**: No user configuration required; the system continuously monitors CPU activity and automatically enters power-saving states when cores are idle, then exits when work resumes. This contrasts with system suspend modes that require explicit commands. |
| 19 | +* **Transparent**: Happens silently in the background during normal idle periods |
| 20 | +* **Fast Response**: Wakeup latency is in microseconds, meaning the system can instantly resume full performance when an interrupt arrives. This makes standby suitable for real-time responsiveness. |
| 21 | +* **Hierarchical Power Management**: The system optimizes power at multiple levels: first at individual CPU cores (via CPU idle states), then at the cluster level (via cluster standby). This multi-level approach allows fine-grained control, reducing power consumption incrementally based on the number of active cores. |
| 22 | + |
| 23 | +************************* |
| 24 | +Device Tree Configuration |
| 25 | +************************* |
| 26 | + |
| 27 | +Idle states |
| 28 | +=========== |
| 29 | + |
| 30 | +The AM62L Standby Mode configuration includes the following idle states: |
| 31 | + |
| 32 | +.. list-table:: AM62L Idle States |
| 33 | + :widths: 20 50 30 |
| 34 | + :header-rows: 1 |
| 35 | + |
| 36 | + * - Idle State |
| 37 | + - Description |
| 38 | + - Latency |
| 39 | + |
| 40 | + * - **cpu_sleep_0** (CPU Level) |
| 41 | + - Individual CPU WFI (Wait For Interrupt) state |
| 42 | + - Very Low (microseconds) |
| 43 | + |
| 44 | + * - **cluster_sleep_0** (Low Latency Cluster standby) |
| 45 | + - Cluster low-latency standby mode when all cores are idle, with reduced clock frequencies and non-critical power domains disabled |
| 46 | + - Low (milliseconds) |
| 47 | + |
| 48 | +The configuration can be loaded from the device tree overlay :file:`k3-am62l3-evm-idle-states.dtso`, which defines |
| 49 | +these states and their power management characteristics. |
| 50 | + |
| 51 | +Power Domain Hierarchy |
| 52 | +====================== |
| 53 | + |
| 54 | +In addition to idle states, the device tree defines the power domain hierarchy that allows CPUIdle to understand |
| 55 | +how different power domains relate to each other: |
| 56 | + |
| 57 | +* **CPU_PD** (CPU Power Domain): Per-CPU power domain |
| 58 | +* **CLUSTER_PD** (Cluster Power Domain): Cluster-level power domain that groups multiple CPUs |
| 59 | + |
| 60 | +These power domains inform CPUIdle about which non-critical domains can be disabled when all cores within them are idle. |
| 61 | + |
| 62 | +.. note:: |
| 63 | + |
| 64 | + The device tree overlay also includes additional idle states for Suspend-to-Idle (S2Idle) functionality |
| 65 | + that can be referred from :ref:`pm_s2idle_psci`. |
| 66 | + The Standby Mode uses the **cpu_sleep_0** and **cluster_sleep_0** idle states, coordinated through the |
| 67 | + **CPU_PD** and **CLUSTER_PD** power domain hierarchy. |
| 68 | + |
| 69 | +Critical Prerequisites |
| 70 | +====================== |
| 71 | + |
| 72 | +The AM62L Standby Mode implementation has important prerequisites that must be met for correct operation. |
| 73 | + |
| 74 | +**CPSW (Gigabit Ethernet) Driver Suspension** |
| 75 | + |
| 76 | +The entry into Cluster level standby is conditional on CPSW driver being suspended, since hardware CRC errors |
| 77 | +occur when CPSW continues operation during cluster standby. The CPSW is an Always-On IP in the AM62L SoC. |
| 78 | + |
| 79 | +**Display Driver Suspension** |
| 80 | + |
| 81 | +Similarly, the display driver must be in a suspended state for cluster standby due to frame buffer overflow issues. |
| 82 | +Ensure display is not actively driving output when testing or relying on Standby Mode for power savings. |
| 83 | + |
| 84 | +.. warning:: |
| 85 | + |
| 86 | + Standby Mode only functions correctly when the DISPLAY and CPSW drivers are suspended. The device tree |
| 87 | + overlay :file:`k3-am62l3-evm-idle-states.dtso` disables the CPSW driver to ensure this |
| 88 | + condition is met. Do not override this configuration without understanding the implications for cluster |
| 89 | + idle transitions and hardware stability. |
| 90 | + |
| 91 | +*********************************************** |
| 92 | +Power Sequencing and Cluster Standby Entry/Exit |
| 93 | +*********************************************** |
| 94 | + |
| 95 | +When the all cores in a cluster become idle and AM62L system enters Standby Mode: |
| 96 | + |
| 97 | +1. **Detection Phase**: |
| 98 | + - CPUIdle monitors per-CPU idle state transitions |
| 99 | + - Domain idle state manager tracks core idle status |
| 100 | + - When all cores in a cluster are idle, cluster standby opportunity is identified |
| 101 | + |
| 102 | +2. **Coordination Phase**: |
| 103 | + - Linux CPUIdle framework signals cluster idle state via PSCI ``CPU_SUSPEND`` call |
| 104 | + - PSCI parameter encodes cluster standby request with standby state type (not power-down) |
| 105 | + - TF-A receives request in secure monitor |
| 106 | + |
| 107 | +3. **Validation Phase**: |
| 108 | + - TF-A validates the PSCI request parameter sent for cluster standby |
| 109 | + - Checks all cores in cluster are idle |
| 110 | + |
| 111 | +4. **Standby Entry Phase**: |
| 112 | + - TF-A executes cluster standby entry sequence |
| 113 | + - Reduces PLL clock frequencies for non-critical subsystems |
| 114 | + - Disables non-critical power domains |
| 115 | + - Puts DDR into auto-self-refresh mode |
| 116 | + - System enters low-power standby state with reduced power consumption |
| 117 | + |
| 118 | +5. **Wake-Up Phase**: |
| 119 | + - Incoming interrupt(*any* interrupt can wake the system) triggers wake-up |
| 120 | + - TF-A restores normal PLL frequencies and power domains |
| 121 | + - DDR exits auto-self-refresh mode |
| 122 | + - Cores resume execution with minimal latency |
| 123 | + - System returns to active operation |
| 124 | + |
| 125 | +*************************** |
| 126 | +Monitoring Standby Activity |
| 127 | +*************************** |
| 128 | + |
| 129 | +Once Standby Mode is enabled, you can monitor idle state activity through the PM generic power domain (genpd) |
| 130 | +sysfs interface. The power domain names are derived from the PSCI power domain hierarchy defined in the device |
| 131 | +tree overlay. |
| 132 | + |
| 133 | +.. rubric:: CPU Idle Activity |
| 134 | + |
| 135 | +To monitor per-CPU idle state usage: |
| 136 | + |
| 137 | +.. code-block:: console |
| 138 | +
|
| 139 | + # View CPU idle state statistics |
| 140 | + $ cat /sys/kernel/debug/pm_genpd/power-controller-cpu/idle_states |
| 141 | +
|
| 142 | + State Time(ms) Usage Rejected Above Below S2idle |
| 143 | + S0 1052189 34224 0 0 0 0 |
| 144 | +
|
| 145 | +.. rubric:: Cluster Standby Activity (Recommended) |
| 146 | + |
| 147 | +To monitor cluster-level standby mode usage, which is the most useful metric for verifying that the system |
| 148 | +is successfully entering the low-latency standby mode when all cores are idle: |
| 149 | + |
| 150 | +.. code-block:: console |
| 151 | +
|
| 152 | + # View cluster standby state statistics |
| 153 | + $ cat /sys/kernel/debug/pm_genpd/power-controller-cluster/idle_states |
| 154 | +
|
| 155 | + State Time(ms) Usage Rejected Above Below S2idle |
| 156 | + S0 263595 5415 647 2854 0 0 |
| 157 | +
|
| 158 | +The ``Usage`` counter shows how many times the cluster entered the standby state, while ``Time(ms)`` shows |
| 159 | +the total milliseconds spent in that state. A non-zero Usage count indicates that the cluster standby mode |
| 160 | +is being actively used during idle periods. |
| 161 | + |
| 162 | +********************************** |
| 163 | +Difference from System Sleep Modes |
| 164 | +********************************** |
| 165 | + |
| 166 | +Standby Mode is distinct from deeper system sleep modes like Deep Sleep or RTC-Only+DDR: |
| 167 | + |
| 168 | +.. list-table:: Standby versus Deep Sleep Modes |
| 169 | + :widths: 25 35 40 |
| 170 | + :header-rows: 1 |
| 171 | + |
| 172 | + * - Feature |
| 173 | + - Standby Mode |
| 174 | + - Deep Sleep (mem) |
| 175 | + |
| 176 | + * - **Entry** |
| 177 | + - Automatic, opportunistic |
| 178 | + - Explicit user request |
| 179 | + |
| 180 | + * - **CPU State** |
| 181 | + - Idle in standby state, context preserved |
| 182 | + - Offline via hotplug |
| 183 | + |
| 184 | + * - **Wakeup Latency** |
| 185 | + - Microseconds |
| 186 | + - Milliseconds |
| 187 | + |
| 188 | + * - **PLL/Clock State** |
| 189 | + - Reduced frequencies for non-critical subsystems |
| 190 | + - Full frequency restoration required |
| 191 | + |
| 192 | + * - **DDR State** |
| 193 | + - Auto-self-refresh during cluster standby |
| 194 | + - Self-refresh |
| 195 | + |
| 196 | + * - **Wakeup Interrupts** |
| 197 | + - Any SoC interrupt event |
| 198 | + - Only specific wakeup sources - GPIO, RTC, etc. |
| 199 | + |
| 200 | + * - **Use Case** |
| 201 | + - Normal idle periods with fast wakeup |
| 202 | + - Extended inactivity periods |
| 203 | + |
| 204 | +**************************************** |
| 205 | +Platform-Specific Implementation Details |
| 206 | +**************************************** |
| 207 | + |
| 208 | +The AM62L Standby Mode implementation uses platform-specific handlers in TF-A: |
| 209 | + |
| 210 | +* :file:`plat/ti/k3low/common/am62l_psci.c` - AM62L PSCI implementation |
| 211 | +* :file:`plat/ti/k3low/board/am62lx/lpm/standby.c` - Cluster standby handler and power sequencing logic |
| 212 | + |
| 213 | +These files implement the ``validate_power_state()`` and ``am62l_entry/exit_standby()`` PSCI platform operations that |
| 214 | +coordinate the idle state requests and manage the actual hardware sequencing for cluster standby entry/exit, |
| 215 | +including clock frequency adjustments and power domain transitions. |
| 216 | + |
| 217 | +**References** |
| 218 | + |
| 219 | +* :ref:`cpuidle-guide` - General CPUIdle framework documentation |
| 220 | +* :ref:`pm_s2idle_psci` - To understand PSCI and OSI mode |
| 221 | +* :ref:`lpm_modes` - Low power modes overview |
| 222 | +* :ref:`howto_dt_overlays` - Device Tree Overlay Documentation |
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