You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
feat(security): Add Secure Boot documentation for AM62LX SoC
Secure boot page is missing AM62L specific documentation. Due to very
large difference with other SoCs in the boot flow, this contains many
differences in documentation as well. This commit adds any AM62L
specific information in the Secure Boot section, and adds it to its TOC.
Signed-off-by: T Pratham <t-pratham@ti.com>
We offer methods for U-Boot's Secondary Program Loader (SPL) to securely verify the U-Boot
36
-
proper. U-Boot calls Texas Instrument Foundational Security (TIFS) through Texas Instruments System Controller Interface (TISCI)
37
-
to do this. For more information about using TISCI methods see the
38
-
`TISCI User Guide <https://software-dl.ti.com/tisci/esd/latest/index.html>`__. U-Boot proper then securely verifies and decrypts the kernel, Device Tree Blobs (DTB), and initramfs.
35
+
.. ifconfig:: CONFIG_part_variant in ('AM62LX')
39
36
40
-
.. Image:: /images/K3_KF.png
37
+
The U-Boot's Secondary Program Loader (SPL) securely verifies the U-Boot
38
+
proper. U-Boot uses its verified boot framework to do this. U-Boot proper
39
+
then securely verifies and decrypts the kernel, Device Tree Blobs (DTB),
40
+
and initramfs.
41
+
42
+
.. Image:: /images/AM62L_KF.png
41
43
:scale:70%
42
44
45
+
.. ifconfig:: CONFIG_part_variant not in ('AM62LX')
46
+
47
+
We offer methods for U-Boot's Secondary Program Loader (SPL) to securely
48
+
verify the U-Boot proper. U-Boot calls Texas Instrument Foundational
49
+
Security (TIFS) through Texas Instruments System Controller Interface
50
+
(TISCI) to do this. For more information about using TISCI methods see the
51
+
`TISCI User Guide <https://software-dl.ti.com/tisci/esd/latest/index.html>`__.
52
+
U-Boot proper then securely verifies and decrypts the kernel, Device Tree
53
+
Blobs (DTB), and initramfs.
54
+
55
+
.. Image:: /images/K3_KF.png
56
+
:scale:70%
57
+
43
58
Secure boot has layers. Some layers are trusted more than others. Secure ROM has the highest trust and Runtime Execution
44
59
Environment (REE) non-trustzone user-space applications have the least. If a
45
60
lower trust entity must load a higher trust code, an even higher trust entity
46
61
must verify it and not allow access by the lower trust entity after that
47
62
point. Some such trust inversions are as follows:
48
63
49
-
- R5 U-Boot loading ATF/OP-TEE
50
-
- R5 Public Boot ROM loading TIFS
51
-
- Linux loading Trusted applications(TA)
64
+
.. ifconfig:: CONFIG_part_variant in ('AM62LX')
65
+
66
+
- A53 Public Boot ROM loading TF-A/OP-TEE
67
+
- A53 Public Boot ROM loading TIFS
68
+
- Linux loading Trusted applications (TA)
69
+
70
+
.. ifconfig:: CONFIG_part_variant not in ('AM62LX')
71
+
72
+
- R5 U-Boot loading TF-A/OP-TEE
73
+
- R5 Public Boot ROM loading TIFS
74
+
- Linux loading Trusted applications (TA)
52
75
53
76
These are called out in the sequence as shown in the following image and their method of ensuring trust is explained.
54
77
55
78
Secure Boot Flow
56
79
--------------------
57
80
58
-
.. Image:: /images/K3_BF.jpg
59
-
:scale:70%
81
+
.. ifconfig:: CONFIG_part_variant in ('AM62LX')
82
+
83
+
.. Image:: /images/AM62L_BF.png
84
+
:scale:70%
85
+
86
+
.. ifconfig:: CONFIG_part_variant not in ('AM62LX')
87
+
88
+
.. Image:: /images/K3_BF.jpg
89
+
:scale:70%
60
90
61
91
.. rubric:: ROM
62
92
63
-
On device startup, execution begins with the ROM bootloader (Secure ROM) running on the DSMC/TIFS core. After initial device security
64
-
setup the Secure ROM starts the Public ROM running on the R5 core. The Public Boot ROM handles loading the first stage image `tiboot3.bin` from a
65
-
peripheral as selected by the BOOTMODE pins. This image is placed into on chip SRAM as external memory interfaces such as DDR are not yet enabled.
66
-
The exact location is device dependent. More details can be found in the device "Technical Reference Manual".
93
+
.. ifconfig:: CONFIG_part_variant not in ('AM62LX')
94
+
95
+
On device startup, execution begins with the ROM bootloader (Secure ROM)
96
+
running on the DSMC/TIFS core. After initial device security setup the
97
+
Secure ROM starts the Public ROM running on the R5 core. The Public Boot ROM
98
+
handles loading the first stage image :file:`tiboot3.bin` from a peripheral
99
+
as selected by the BOOTMODE pins. This image is placed into on chip SRAM as
100
+
external memory interfaces such as DDR are not yet enabled. The exact
101
+
location is device dependent. More details can be found in the device
102
+
"Technical Reference Manual".
103
+
104
+
.. ifconfig:: CONFIG_part_variant in ('AM64X')
67
105
68
-
.. ifconfig:: CONFIG_part_variant in ('AM64x')
106
+
The contents of this first stage image are authenticated and decrypted by
107
+
the Secure ROM. Contents include:
69
108
70
-
The contents of this first stage image are authenticated and decrypted by the Secure ROM. Contents include:
109
+
* DMSC firmware: `Texas Instruments Foundational Security (TIFS)` + Device/Power Manager: After authentication/decryption, DMSC firmware replaces the Secure ROM as the authenticator entity executing on the DMSC core.
110
+
* R5 SPL: The R5 SPL bootloader is executed on the R5 core.
71
111
72
-
* DMSC firmware: `Texas Instruments Foundational Security (TIFS)` + Device/Power Manager: After authentication/decryption, DMSC firmware replaces the Secure ROM as the authenticator entity executing on the DMSC core.
73
-
* R5 SPL: The R5 SPL bootloader is executed on the R5 core.
112
+
.. ifconfig:: CONFIG_part_variant not in ('AM64X')
74
113
75
-
.. ifconfig:: CONFIG_part_variant not in ('AM64X')
114
+
The contents of this first stage image are authenticated and decrypted by
115
+
the Secure ROM. Contents include:
116
+
117
+
* `Texas Instruments Foundational Security (TIFS)` firmware: After authentication/decryption, TIFS firmware replaces the Secure ROM as the authenticator entity executing on the TIFS core.
118
+
* R5 SPL: The R5 SPL bootloader is executed on the R5 core.
119
+
120
+
.. ifconfig:: CONFIG_part_variant in ('AM62LX')
121
+
122
+
On device startup, execution begins with the ROM bootloader (Secure ROM)
123
+
running on SMS M4 core. After initial device security setup, the Secure ROM
124
+
starts the Public ROM running on the A53 core. The Public ROM handles
125
+
loading the first stage image :file:`tiboot3.bin` from a peripheral as
126
+
selected by the BOOTMODE pins. This image is placed into on-chip SRAM as
127
+
external memory interfaces such as DDR are not yet enabled. The exact
128
+
location is device dependent. More details can be found in the device
129
+
"Technical Reference Manual".
76
130
77
131
The contents of this first stage image are authenticated and decrypted by the Secure ROM. Contents include:
78
132
79
-
* `Texas Instruments Foundational Security (TIFS)` firmware: After authentication/decryption, TIFS firmware replaces the Secure ROM as the authenticator entity executing on the TIFS core.
80
-
* R5 SPL`: The R5 SPL bootloader is executed on the R5 core.
133
+
* `Texas Instruments Foundational Security (TIFS)` firmware: After authentication/decryption, TIFS firmware replaces the Secure ROM as the authenticator entity executing on the M4 core in the 2nd phase of the boot.
134
+
* BL-1: The pre-bootloader executed on the A53 core, initializes the console and DDR for the 2nd phase of the boot.
81
135
82
-
.. rubric:: R5 SPL
136
+
.. ifconfig:: CONFIG_part_variant not in ('AM62LX')
83
137
84
-
R5 SPL loads the second boot stage FIT image `tispl.bin` from the peripheral as selected by the BOOTMODE pins. From this FIT image, TF-A, OPTEE, A53 SPL,
85
-
and SPL DTB are extracted and authenticated and/or decrypted by TIFS. If authentication passed, the R5 SPL starts the ARM64 core. TF-A, OPTEE, and A53 SPL
86
-
will begin execution on the ARM64 core. R5 SPL also configures DDR and the console so the user can see the first prints as seen below:
138
+
.. rubric:: R5 SPL
87
139
88
-
R5 SPL's output will be similar to this:
89
-
Notice the "Authentication passed" lines as TF-A, OPTEE, A53 SPL, and SPL DTB are authenticated.
140
+
R5 SPL loads the second boot stage FIT image `tispl.bin` from the
141
+
peripheral as selected by the BOOTMODE pins. From this FIT image, TF-A,
142
+
OPTEE, A53 SPL, and SPL DTB are extracted and authenticated and/or decrypted
143
+
by TIFS. If authentication passed, the R5 SPL starts the ARM64 core. TF-A,
144
+
OPTEE, and A53 SPL will begin execution on the ARM64 core. R5 SPL also
145
+
configures DDR and the console so the user can see the first prints as seen
146
+
below:
90
147
91
-
.. code-block:: console
148
+
R5 SPL's output will be similar to this:
149
+
Notice the "Authentication passed" lines as TF-A, OPTEE, A53 SPL, and SPL DTB are authenticated.
After R5 SPL, the device/power manager firmware continues running on the R5 core.
163
+
.. ifconfig:: CONFIG_part_variant in ('AM62x')
164
+
165
+
After R5 SPL, the device/power manager firmware continues running on the R5 core.
106
166
107
167
.. rubric:: A53 SPL
108
168
109
-
A53 SPL then loads the U-Boot proper FIT image `U-boot.img` from the peripheral as selected by the BOOTMODE pins. From this FIT image, the U-boot bootloader
110
-
and DTB are extracted before passing execution to u-boot proper.
169
+
.. ifconfig:: CONFIG_part_variant not in ('AM62LX')
111
170
112
-
A53 SPL's output will be similar to this: (notice the "Authentication passed" lines as U-Boot and the DTB are authenticated).
171
+
A53 SPL then loads the U-Boot proper FIT image :file:`u-boot.img` from the
172
+
peripheral as selected by the BOOTMODE pins. From this FIT image, the U-Boot
173
+
bootloader and DTB are extracted before passing execution to U-Boot proper.
113
174
114
-
.. code-block:: console
175
+
A53 SPL's output will be similar to this: (notice the "Authentication passed" lines as U-Boot and the DTB are authenticated).
## Checking hash(es) for config conf-0 ... sha512,rsa4096:custMpk+ OK
210
+
## Checking hash(es) for Image uboot ... sha512+ OK
211
+
## Checking hash(es) for Image fdt-0 ... sha512+ OK
121
212
122
213
.. rubric:: U-Boot
123
214
@@ -194,17 +285,38 @@ HS Boot Flow Tools
194
285
195
286
U-boot:
196
287
197
-
The ti-u-boot source is a project used to create tiboot3.bin, tispl.bin, and u-boot.img. To create tiboot3.bin for K3 family devices, u-boot builds R5 SPL and
198
-
binman packages it in a `tiboot3.bin` image. To build A53 SPL, binman takes ATF (bl31.bin), OPTEE (bl32.bin), A53 SPL, and A53 DTBs and packages
199
-
them in a `tispl.bin` image. U-Boot can then use the openssl library to sign each component as specified in k3-<soc>-binman.dtsi.
288
+
.. ifconfig:: CONFIG_part_variant not in ('AM62LX')
200
289
201
-
.. code-block:: console
290
+
The ti-u-boot source is a project used to create tiboot3.bin, tispl.bin, and u-boot.img. To create tiboot3.bin for K3 family devices, u-boot builds R5 SPL and
291
+
binman packages it in a `tiboot3.bin` image. To build A53 SPL, binman takes TF-A (bl31.bin), OPTEE (bl32.bin), A53 SPL, and A53 DTBs and packages
292
+
them in a `tispl.bin` image. U-Boot can then use the openssl library to sign each component as specified in k3-<soc>-binman.dtsi.
0 commit comments