Skip to content

Commit 5765ba4

Browse files
committed
feat(crypto): Add crypto perf table for different hardware
Add a performance table which contains the output of `openssl speed ...` command over the 3 different hardware options: SA2UL/DTHEv2 accelerator, ARM CE, and base ARM, for AES-128-CBC algorithm. This gives a clear picture of how crypto operations fare over each IP option. Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
1 parent be90396 commit 5765ba4

6 files changed

Lines changed: 75 additions & 0 deletions

File tree

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
.. csv-table:: AES-128-CBC Performance
2+
:header: "Size (bytes)", "DTHEv2 Accelerator", "ARM CE", "ARM"
3+
:widths: 30, 30, 30, 30
4+
5+
"16", "0.28", "86.86", "28.02"
6+
"64", "1.16", "271.43", "35.57"
7+
"256", "4.63", "568.25", "38.33"
8+
"1024", "17.15", "800.83", "39.08"
9+
"8192", "82.06", "908.72", "39.31"
10+
"16384", "112.48", "917.23", "39.02"
11+
"CPU Usage %", "18", "99", "99"
12+
Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
.. csv-table:: AES-128-CBC Performance
2+
:header: "Size (bytes)", "SA2UL Accelerator", "ARM CE", "ARM"
3+
:widths: 30, 30, 30, 30
4+
5+
"16", "0.43", "97.37", "31.46"
6+
"64", "1.88", "304.29", "39.87"
7+
"256", "7.18", "636.54", "42.97"
8+
"1024", "23.80", "897.51", "43.82"
9+
"8192", "71.31", "1018.75", "44.05"
10+
"16384", "83.60", "1028.48", "43.99"
11+
"CPU Usage %", "34%", "99%", "99%"
Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
.. csv-table:: AES-128-CBC Performance
2+
:header: "Size (bytes)", "SA2UL Accelerator", "ARM CE", "ARM"
3+
:widths: 30, 30, 30, 30
4+
5+
"16", "0.38", "95.83", "31.06"
6+
"64", "1.60", "300.27", "39.69"
7+
"256", "6.08", "632.25", "42.89"
8+
"1024", "23.90", "895.17", "43.74"
9+
"8192", "93.02", "1018.16", "44.04"
10+
"16384", "117.17", "1028.05", "44.03"
11+
"CPU Usage %", "38%", "99%", "99%"
Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
.. csv-table:: AES-128-CBC Performance
2+
:header: "Size (bytes)", "SA2UL Accelerator", "ARM CE", "ARM"
3+
:widths: 30, 30, 30, 30
4+
5+
"16", "0.34", "69.43", "22.18"
6+
"64", "1.51", "217.04", "28.34"
7+
"256", "5.99", "454.25", "30.63"
8+
"1024", "21.92", "640.51", "31.25"
9+
"8192", "97.97", "726.61", "31.44"
10+
"16384", "134.93", "727.48", "31.44"
11+
"CPU Usage %", "39%", "99%", "99%"

source/linux/Foundational_Components/Kernel/Kernel_Drivers/Crypto/DTHEv2.rst

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,16 @@ software only implementation can be compared to the previous test.
212212
Page size (bytes): 4096
213213
Exit status: 0
214214
215+
*******************************
216+
Hardware Performance Comparison
217+
*******************************
218+
219+
The following table shows AES-128-CBC throughput measured using ``openssl speed``
220+
across the DTHEv2 hardware accelerator, ARM Cryptographic Extension (CE), and
221+
baseline ARM CPU.
222+
223+
.. include:: ../../../../../devices/AM62LX/linux/_Crypto_Perf_AES_128_CBC.rst
224+
215225
******************************************************************
216226
Using the True Random Number Generator (TRNG) Hardware Accelerator
217227
******************************************************************

source/linux/Foundational_Components/Kernel/Kernel_Drivers/Crypto/SA2UL_OMAP.rst

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,26 @@ software only implementation can be compared to the previous test.
300300
Page size (bytes): 4096
301301
Exit status: 0
302302
303+
*******************************
304+
Hardware Performance Comparison
305+
*******************************
306+
307+
The following table shows AES-128-CBC throughput measured using ``openssl speed``
308+
across the SA2UL hardware accelerator, ARM Cryptographic Extension (CE), and
309+
baseline ARM CPU.
310+
311+
.. ifconfig:: CONFIG_part_variant in ('AM62X')
312+
313+
.. include:: ../../../../../devices/AM62X/linux/_Crypto_Perf_AES_128_CBC.rst
314+
315+
.. ifconfig:: CONFIG_part_variant in ('AM62PX')
316+
317+
.. include:: ../../../../../devices/AM62PX/linux/_Crypto_Perf_AES_128_CBC.rst
318+
319+
.. ifconfig:: CONFIG_part_variant in ('AM64X')
320+
321+
.. include:: ../../../../../devices/AM64X/linux/_Crypto_Perf_AES_128_CBC.rst
322+
303323
***********************************
304324
Using the TRNG Hardware Accelerator
305325
***********************************

0 commit comments

Comments
 (0)