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Merged
praneethbajjuri merged 2 commits into from
May 16, 2025
Merged

AM64 Early boot support #264

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a8c1d3b
feat(U-Boot): add remoteproc earlyboot support for AM64x
h-nagalla Mar 26, 2025
970129f
fix(U-Boot): Keep MCU-R5 boot specifics only for Jacinto devices
h-nagalla Mar 26, 2025
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1 change: 1 addition & 0 deletions configs/AM64X/AM64X_linux_toc.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@ linux/Foundational_Components/U-Boot/UG-UART
linux/Foundational_Components/U-Boot/UG-DDRSS
linux/Foundational_Components/U-Boot/UG-NAND
linux/Foundational_Components/U-Boot/UG-Network-K3
linux/Foundational_Components/U-Boot/UG-RemoteProc
linux/Foundational_Components/U-Boot/Applications
linux/Foundational_Components/U-Boot/Apps-SPL-Debug-OpenOCD
linux/Foundational_Components/U-Boot/Apps-TroubleShooting
Expand Down
185 changes: 93 additions & 92 deletions source/linux/Foundational_Components/U-Boot/UG-RemoteProc.rst
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Expand Up @@ -21,7 +21,7 @@ The below command will initialize all the available remote cores:

.. code-block:: console

=> rproc init
=> rproc init

The below command will initialize just the given remote core

Expand Down Expand Up @@ -53,10 +53,10 @@ image is loaded only after initializing the core.

.. code-block:: console

=> load mmc 1:2 0x90000000 /lib/firmware/j7-main-r5f0_0-fw
2536540 bytes read in 112 ms (21.6 MiB/s)
=> rproc load 2 0x90000000 0x${filesize}
Load Remote Processor 2 with data@addr=0x90000000 2536540 bytes: Success!
=> load mmc 1:2 0x90000000 /lib/firmware/j7-main-r5f0_0-fw
2536540 bytes read in 112 ms (21.6 MiB/s)
=> rproc load 2 0x90000000 0x${filesize}
Load Remote Processor 2 with data@addr=0x90000000 2536540 bytes: Success!


Starting
Expand All @@ -66,7 +66,7 @@ Successfully loaded remotecore can be started using the following command.

.. code-block:: console

=> rproc start 2
=> rproc start 2

Stop
^^^^^
Expand All @@ -75,18 +75,19 @@ A running remotecore can be stopped using the following command.

.. code-block:: console

=> rproc stop 2
=> rproc stop 2

Make sure all the commands are run in the above given sequence. Currently IPC
is not supported in U-boot.

Lockstep and Split mode
^^^^^^^^^^^^^^^^^^^^^^^
.. ifconfig:: CONFIG_part_variant in ('J722S')

.. note::
.. ifconfig:: (CONFIG_sdk in ('SITARA')) or (CONFIG_part_variant in ('J722S'))

This platform does not have split cores for R5F so below information is just for show.
.. note::

This is not relevant for this platform and is only applicable to R5 clusters with lockstep suport.

Cortex-R5F can be used in both lockstep (both cores run same code) and split
mode (each core runs independently).
Expand All @@ -109,105 +110,105 @@ Refer to the below example on K3 J784S4 SoC.

* MAIN R5F:

arch/arm/dts/k3-j784s4-main.dtsi
arch/arm/dts/k3-j784s4-main.dtsi

.. code-block:: dts
.. code-block:: dts

main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>; # set to lockstep-mode
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
...
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>; # set to lockstep-mode
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
...

* Boot MCU R5F:

arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi

.. code-block:: dts
.. code-block:: dts

mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>; # set to lockstep-mode
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
...
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>; # set to lockstep-mode
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
...

arch/arm/dts/k3-j784s4-binman.dtsi
arch/arm/dts/k3-j784s4-binman.dtsi

.. code-block:: dts
.. code-block:: dts

&binman {
tiboot3-j784s4-gp-evm.bin { # In the case of GP boards
filename = "tiboot3-j784s4-gp-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
core-opts = <0>; # core-opts value should be set to 0 for lockstep-mode on boot core
content-sbl = <&u_boot_spl_unsigned>;
load = <0x41c00000>;
...
&binman {
tiboot3-j784s4-gp-evm.bin { # In the case of GP boards
filename = "tiboot3-j784s4-gp-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
core-opts = <0>; # core-opts value should be set to 0 for lockstep-mode on boot core
content-sbl = <&u_boot_spl_unsigned>;
load = <0x41c00000>;
...

.. rubric:: Split-mode configuration

* MAIN R5F:

arch/arm/dts/k3-j784s4-main.dtsi
arch/arm/dts/k3-j784s4-main.dtsi

.. code-block:: dts
.. code-block:: dts

main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <0>; # set to split-mode
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
...
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <0>; # set to split-mode
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
...

* Boot MCU R5:

arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi

.. code-block:: dts

mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <0>; # set to split-mode
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi

.. code-block:: dts

mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <0>; # set to split-mode
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
...

arch/arm/dts/k3-j784s4-binman.dtsi

.. code-block:: dts

&binman {
tiboot3-j784s4-gp-evm.bin { # In the case of GP boards
filename = "tiboot3-j784s4-gp-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
core-opts = <2>; # core-opts value should be set to 2 for split-mode on boot core
content-sbl = <&u_boot_spl_unsigned>;
load = <0x41c00000>;
...

arch/arm/dts/k3-j784s4-binman.dtsi

.. code-block:: dts

&binman {
tiboot3-j784s4-gp-evm.bin { # In the case of GP boards
filename = "tiboot3-j784s4-gp-evm.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
core-opts = <2>; # core-opts value should be set to 2 for split-mode on boot core
content-sbl = <&u_boot_spl_unsigned>;
load = <0x41c00000>;
...

.. note::

From SDK 9.1 onward, default mode is split mode for boot cores.
From SDK 9.1 onward, default mode is split mode for boot cores.

HS Devices
^^^^^^^^^^
Expand All @@ -222,19 +223,19 @@ Steps for signing and updating firmware images in filesystem.

* Getting Security Dev Tool

.. code-block:: console
.. code-block:: console

$ git clone https://git.ti.com/git/security-development-tools/core-secdev-k3.git -b master
$ export TI_SECURE_DEV_PKG=`pwd`/core-secdev-k3
$ git clone https://git.ti.com/git/security-development-tools/core-secdev-k3.git -b master
$ export TI_SECURE_DEV_PKG=`pwd`/core-secdev-k3

* Export the path for secdev

.. code-block:: console
.. code-block:: console

$ ${TI_SECURE_DEV_PKG}/scripts/secure-binary-image.sh $FIRMWARE $FIRMWARE.signed
$ ${TI_SECURE_DEV_PKG}/scripts/secure-binary-image.sh $FIRMWARE $FIRMWARE.signed

* Updating firmware image

.. code-block:: console
.. code-block:: console

$ ln -vfs $FIRMWARE.signed /lib/firmware/j7-main-r5f0_0-fw-sec
$ ln -vfs $FIRMWARE.signed /lib/firmware/j7-main-r5f0_0-fw-sec