Re-factored fakeram to support sp/dp ram/regfile

fixed coverage instrumentation
more cleanup and code coverage

Signed-off-by: Jeff Ng <jeffng@precisioninno.com>

Author: jeffng-or

run.py

@@ -1,17 +1,12 @@
 #!/usr/bin/env python3
 
-import os
 import sys
-import json
 import argparse
-from pathlib import Path
 
+from utils.run_utils import RunUtils
 from utils.class_process import Process
-from utils.class_memory import Memory
-
-from utils.create_lib import create_lib
-from utils.create_lef import create_lef
-from utils.create_verilog import create_verilog
+from utils.memory_factory import MemoryFactory
+from utils.timing_data import TimingData
 
 ################################################################################
 # RUN GENERATOR
@@ -40,39 +35,49 @@ def get_args() -> argparse.Namespace:
         action="store",
         help="Output directory ",
         required=False,
-        default=None,
+        default="results",
     )
     return parser.parse_args()
 
 
-def ensure_results_dir(output_dir, memory_name):
-    if output_dir:  # Output dir was set by command line option
-        p = str(Path(output_dir).expanduser().resolve(strict=False))
-        results_dir = os.sep.join([p, memory_name])
-    else:
-        results_dir = os.sep.join([os.getcwd(), "results", memory_name])
-    if not os.path.exists(results_dir):
-        os.makedirs(results_dir)
-    return results_dir
+def get_memory_type(json_data):
+    if "memory_type" in json_data:
+        return json_data["memory_type"]
+    return "RAM"
 
 
-def main(args: argparse.Namespace):
+def get_port_config(json_data):
+    if "port_configuration" in json_data:
+        return json_data["port_configuration"]
+    return "SP"
 
-    # Load the JSON configuration file
-    with open(args.config, "r") as fid:
-        raw = [line.strip() for line in fid if not line.strip().startswith("#")]
-    json_data = json.loads("\n".join(raw))
 
+def main(args: argparse.Namespace):
+    json_data = RunUtils.get_config(args.config)
     # Create a process object (shared by all srams)
     process = Process(json_data)
+    timing_data = TimingData(json_data)
+
+    memory_type = get_memory_type(json_data)
+    port_config = get_port_config(json_data)
 
     # Go through each sram and generate the lib, lef and v files
     for sram_data in json_data["srams"]:
-        memory = Memory(process, sram_data)
-        results_dir = ensure_results_dir(args.output_dir, memory.name)
-        create_lib(memory, results_dir)
-        create_lef(memory, results_dir)
-        create_verilog(memory, results_dir)
+        name = str(sram_data["name"])
+        width_in_bits = int(sram_data["width"])
+        depth = int(sram_data["depth"])
+        num_banks = int(sram_data["banks"])
+        memory = MemoryFactory.create(
+            name,
+            width_in_bits,
+            depth,
+            num_banks,
+            memory_type,
+            port_config,
+            process,
+            timing_data,
+        )
+        RunUtils.write_memory(memory, args.output_dir)
 
 
 ### Entry point

test/.gitignore

@@ -2,4 +2,5 @@
 #*#
 .#*
 __pycache__
-results
+results
+*_results