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Switched to use dict.get() (#8)
Signed-off-by: Jeff Ng <jeffng@precisioninno.com>
1 parent 61faced commit db3968e

2 files changed

Lines changed: 4 additions & 19 deletions

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run.py

Lines changed: 2 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -30,26 +30,14 @@ def get_args() -> argparse.Namespace:
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return parser.parse_args()
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def get_memory_type(json_data):
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if "memory_type" in json_data:
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return json_data["memory_type"]
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return "RAM"
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def get_port_config(json_data):
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if "port_configuration" in json_data:
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return json_data["port_configuration"]
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return "SP"
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def main(args: argparse.Namespace):
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json_data = RunUtils.get_config(args.config)
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# Create a process object (shared by all srams)
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process = Process(json_data)
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timing_data = TimingData(json_data)
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51-
memory_type = get_memory_type(json_data)
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port_config = get_port_config(json_data)
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memory_type = json_data.get("memory_type", "RAM")
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port_config = json_data.get("port_configuration", "SP")
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# Go through each sram and generate the lib, lef and v files
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for sram_data in json_data["srams"]:

utils/class_process.py

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -63,11 +63,8 @@ def __init__(self, json_data):
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+ (self.pin_width_um / 2.0)
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)
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if "bitcell_width_um" in json_data and "bitcell_height_um" in json_data:
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self.bitcell_width_um = float(json_data["bitcell_width_um"])
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self.bitcell_height_um = float(json_data["bitcell_height_um"])
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else:
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self.bitcell_width_um = self.bitcell_height_um = None
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self.bitcell_width_um = json_data.get("bitcell_width_um", None)
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self.bitcell_height_um = json_data.get("bitcell_height_um", None)
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def has_defined_bitcell_size(self):
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return self.bitcell_width_um and self.bitcell_height_um

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