diff --git a/parse_input.py b/parse_input.py deleted file mode 100644 index fdfad7c..0000000 --- a/parse_input.py +++ /dev/null @@ -1,89 +0,0 @@ -import math -import os -import sys -from pathlib import Path -from utils.cacti_config import cacti_config - -################################################################################ -# MEMORY CLASS -# -# This class stores the infromation about a specific memory that is being -# generated. This class takes in a process object, the infromation in one of -# the items in the "sram" list section of the json configuration file, and -# finally runs cacti to generate the rest of the data. -################################################################################ - -class Memory: - - def __init__( self, process, sram_data , output_dir = None, cacti_dir = None): - - self.process = process - self.name = str(sram_data['name']) - self.width_in_bits = int(sram_data['width']) - self.depth = int(sram_data['depth']) - self.num_banks = int(sram_data['banks']) - self.cache_type = str(sram_data['type']) if 'type' in sram_data else 'cache' - self.rw_ports = 1 - self.width_in_bytes = math.ceil(self.width_in_bits / 8.0) - self.total_size = self.width_in_bytes * self.depth - if output_dir: # Output dir was set by command line option - p = str(Path(output_dir).expanduser().resolve(strict=False)) - self.results_dir = os.sep.join([p, self.name]) - else: - self.results_dir = os.sep.join([os.getcwd(), 'results', self.name]) - if not os.path.exists( self.results_dir ): - os.makedirs( self.results_dir ) - if cacti_dir: - self.cacti_dir = cacti_dir - else: - self.cacti_dir = os.environ['CACTI_BUILD_DIR'] - self.__run_cacti() - with open( os.sep.join([self.results_dir, 'cacti.cfg.out']), 'r' ) as fid: - lines = [line for line in fid] - cacti_data = lines[-1].split(',') - - self.tech_node_nm = int(cacti_data[0]) - self.capacity_bytes = int(cacti_data[1]) - self.associativity = int(cacti_data[2]) - self.output_width_bits = int(cacti_data[3]) - self.access_time_ns = float(cacti_data[4]) - self.cycle_time_ns = float(cacti_data[5]) - #self.dyn_search_energy_nj = float(cacti_data[6]) - self.dyn_read_energy_nj = float(cacti_data[7]) - self.dyn_write_energy_nj = float(cacti_data[8]) - self.standby_leakage_per_bank_mW = float(cacti_data[9]) - self.area_mm2 = float(cacti_data[10]) - self.fo4_ps = float(cacti_data[11]) - self.width_um = float(cacti_data[12]) - self.height_um = float(cacti_data[13]) - - self.cap_input_pf = 0.005 - - self.tech_node_um = self.tech_node_nm / 1000.0 - - # Adjust to snap - self.width_um = (math.ceil((self.width_um*1000.0)/self.process.snapWidth_nm)*self.process.snapWidth_nm)/1000.0 - self.height_um = (math.ceil((self.height_um*1000.0)/self.process.snapHeight_nm)*self.process.snapHeight_nm)/1000.0 - self.area_um2 = self.width_um * self.height_um - - #self.pin_dynamic_power_mW = (0.5 * self.cap_input_pf * (float(self.process.voltage)**2))*1e9 ;# P = 0.5*CV^2 - self.pin_dynamic_power_mW = self.dyn_write_energy_nj - - self.t_setup_ns = 0.050 ;# arbitrary 50ps setup - self.t_hold_ns = 0.050 ;# arbitrary 50ps hold - - # __run_cacti: shell out to cacti to generate a csv file with more data - # regarding this memory based on the input parameters from the json - # configuration file. - def __run_cacti( self ): - fid = open(os.sep.join([self.results_dir,'cacti.cfg']), 'w') - fid.write( cacti_config.format( self.total_size - , self.width_in_bytes, self.rw_ports, 0, 0 - , self.process.tech_um, self.width_in_bytes*8, self.num_banks - , self.cache_type )) - fid.close() - odir = os.getcwd() - os.chdir(self.cacti_dir ) - cmd = os.sep.join(['.','cacti -infile ']) + os.sep.join([self.results_dir,'cacti.cfg']) - os.system( cmd) - os.chdir(odir) diff --git a/run.py b/run.py index d3f5aff..731c2a0 100755 --- a/run.py +++ b/run.py @@ -1,26 +1,12 @@ #!/usr/bin/env python3 -import os import sys -import json import argparse -from pathlib import Path +from utils.run_utils import RunUtils from utils.class_process import Process -from utils.class_memory import Memory - -from utils.create_lib import create_lib -from utils.create_lef import create_lef -from utils.create_verilog import create_verilog - -################################################################################ -# RUN GENERATOR -# -# This is the main part of the script. It will read in the JSON configuration -# file, create a Cacti configuration file, run Cacti, extract the data from -# Cacti, and then generate the timing, physical and logical views for each SRAM -# found in the JSON configuration file. -################################################################################ +from utils.memory_factory import MemoryFactory +from utils.timing_data import TimingData def get_args() -> argparse.Namespace: @@ -29,9 +15,8 @@ def get_args() -> argparse.Namespace: """ parser = argparse.ArgumentParser( description=""" - BSG Black-box SRAM Generator -- This project is designed to generate black-boxed SRAMs for use in CAD - flows where either an SRAM generator is not avaible or doesn't + flows where either an SRAM generator is not available or doesn't exist. """ ) parser.add_argument("config", help="JSON configuration file") @@ -40,39 +25,49 @@ def get_args() -> argparse.Namespace: action="store", help="Output directory ", required=False, - default=None, + default="results", ) return parser.parse_args() -def ensure_results_dir(output_dir, memory_name): - if output_dir: # Output dir was set by command line option - p = str(Path(output_dir).expanduser().resolve(strict=False)) - results_dir = os.sep.join([p, memory_name]) - else: - results_dir = os.sep.join([os.getcwd(), "results", memory_name]) - if not os.path.exists(results_dir): - os.makedirs(results_dir) - return results_dir +def get_memory_type(json_data): + if "memory_type" in json_data: + return json_data["memory_type"] + return "RAM" -def main(args: argparse.Namespace): +def get_port_config(json_data): + if "port_configuration" in json_data: + return json_data["port_configuration"] + return "SP" - # Load the JSON configuration file - with open(args.config, "r") as fid: - raw = [line.strip() for line in fid if not line.strip().startswith("#")] - json_data = json.loads("\n".join(raw)) +def main(args: argparse.Namespace): + json_data = RunUtils.get_config(args.config) # Create a process object (shared by all srams) process = Process(json_data) + timing_data = TimingData(json_data) + + memory_type = get_memory_type(json_data) + port_config = get_port_config(json_data) # Go through each sram and generate the lib, lef and v files for sram_data in json_data["srams"]: - memory = Memory(process, sram_data) - results_dir = ensure_results_dir(args.output_dir, memory.name) - create_lib(memory, results_dir) - create_lef(memory, results_dir) - create_verilog(memory, results_dir) + name = str(sram_data["name"]) + width_in_bits = int(sram_data["width"]) + depth = int(sram_data["depth"]) + num_banks = int(sram_data["banks"]) + memory = MemoryFactory.create( + name, + width_in_bits, + depth, + num_banks, + memory_type, + port_config, + process, + timing_data, + ) + RunUtils.write_memory(memory, args.output_dir) ### Entry point diff --git a/test/.gitignore b/test/.gitignore index 9fbd300..419fb9a 100644 --- a/test/.gitignore +++ b/test/.gitignore @@ -2,4 +2,5 @@ #*# .#* __pycache__ -results \ No newline at end of file +results +*_results diff --git a/test/au/dprf_256x256.au b/test/au/dprf_256x256.au new file mode 100644 index 0000000..8231154 --- /dev/null +++ b/test/au/dprf_256x256.au @@ -0,0 +1,10243 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO dprf_256x256 + PROPERTY width 256 ; + PROPERTY depth 256 ; + PROPERTY banks 1 ; + FOREIGN dprf_256x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 84.000 ; + CLASS BLOCK ; + PIN dout_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END dout_a[0] + PIN dout_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.096 0.024 0.120 ; + END + END dout_a[1] + PIN dout_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.024 0.168 ; + END + END dout_a[2] + PIN dout_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END dout_a[3] + PIN dout_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.024 0.264 ; + END + END dout_a[4] + PIN dout_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.024 0.312 ; + END + END dout_a[5] + PIN dout_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END dout_a[6] + PIN dout_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.384 0.024 0.408 ; + END + END dout_a[7] + PIN dout_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.024 0.456 ; + END + END dout_a[8] + PIN dout_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END dout_a[9] + PIN dout_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.024 0.552 ; + END + END dout_a[10] + PIN dout_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.024 0.600 ; + END + END dout_a[11] + PIN dout_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END dout_a[12] + PIN dout_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.672 0.024 0.696 ; + END + END dout_a[13] + PIN dout_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.024 0.744 ; + END + END dout_a[14] + PIN dout_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END dout_a[15] + PIN dout_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.024 0.840 ; + END + END dout_a[16] + PIN dout_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.864 0.024 0.888 ; + END + END dout_a[17] + PIN dout_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END dout_a[18] + PIN dout_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.960 0.024 0.984 ; + END + END dout_a[19] + PIN dout_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.024 1.032 ; + END + END dout_a[20] + PIN dout_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END dout_a[21] + PIN dout_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.024 1.128 ; + END + END dout_a[22] + PIN dout_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.152 0.024 1.176 ; + END + END dout_a[23] + PIN dout_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END dout_a[24] + PIN dout_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.024 1.272 ; + END + END dout_a[25] + PIN dout_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.024 1.320 ; + END + END dout_a[26] + PIN dout_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END dout_a[27] + PIN dout_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.024 1.416 ; + END + END dout_a[28] + PIN dout_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.440 0.024 1.464 ; + END + END dout_a[29] + PIN dout_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END dout_a[30] + PIN dout_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.536 0.024 1.560 ; + END + END dout_a[31] + PIN dout_a[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.024 1.608 ; + END + END dout_a[32] + PIN dout_a[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END dout_a[33] + PIN dout_a[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.024 1.704 ; + END + END dout_a[34] + PIN dout_a[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.728 0.024 1.752 ; + END + END dout_a[35] + PIN dout_a[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END dout_a[36] + PIN dout_a[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.824 0.024 1.848 ; + END + END dout_a[37] + PIN dout_a[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.024 1.896 ; + END + END dout_a[38] + PIN dout_a[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END dout_a[39] + PIN dout_a[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.024 1.992 ; + END + END dout_a[40] + PIN dout_a[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.016 0.024 2.040 ; + END + END dout_a[41] + PIN dout_a[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END dout_a[42] + PIN dout_a[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.112 0.024 2.136 ; + END + END dout_a[43] + PIN dout_a[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.024 2.184 ; + END + END dout_a[44] + PIN dout_a[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END dout_a[45] + PIN dout_a[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.024 2.280 ; + END + END dout_a[46] + PIN dout_a[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.304 0.024 2.328 ; + END + END dout_a[47] + PIN dout_a[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END dout_a[48] + PIN dout_a[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.400 0.024 2.424 ; + END + END dout_a[49] + PIN dout_a[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.024 2.472 ; + END + END dout_a[50] + PIN dout_a[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END dout_a[51] + PIN dout_a[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.024 2.568 ; + END + END dout_a[52] + PIN dout_a[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.024 2.616 ; + END + END dout_a[53] + PIN dout_a[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END dout_a[54] + PIN dout_a[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END dout_a[55] + PIN dout_a[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.024 2.760 ; + END + END dout_a[56] + PIN dout_a[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END dout_a[57] + PIN dout_a[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.024 2.856 ; + END + END dout_a[58] + PIN dout_a[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.024 2.904 ; + END + END dout_a[59] + PIN dout_a[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END dout_a[60] + PIN dout_a[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.024 3.000 ; + END + END dout_a[61] + PIN dout_a[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.024 3.048 ; + END + END dout_a[62] + PIN dout_a[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END dout_a[63] + PIN dout_a[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.024 3.144 ; + END + END dout_a[64] + PIN dout_a[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.024 3.192 ; + END + END dout_a[65] + PIN dout_a[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END dout_a[66] + PIN dout_a[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.024 3.288 ; + END + END dout_a[67] + PIN dout_a[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.024 3.336 ; + END + END dout_a[68] + PIN dout_a[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END dout_a[69] + PIN dout_a[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.024 3.432 ; + END + END dout_a[70] + PIN dout_a[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.024 3.480 ; + END + END dout_a[71] + PIN dout_a[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END dout_a[72] + PIN dout_a[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.024 3.576 ; + END + END dout_a[73] + PIN dout_a[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.024 3.624 ; + END + END dout_a[74] + PIN dout_a[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END dout_a[75] + PIN dout_a[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.696 0.024 3.720 ; + END + END dout_a[76] + PIN dout_a[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.024 3.768 ; + END + END dout_a[77] + PIN dout_a[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END dout_a[78] + PIN dout_a[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.840 0.024 3.864 ; + END + END dout_a[79] + PIN dout_a[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.888 0.024 3.912 ; + END + END dout_a[80] + PIN dout_a[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END dout_a[81] + PIN dout_a[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.984 0.024 4.008 ; + END + END dout_a[82] + PIN dout_a[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.032 0.024 4.056 ; + END + END dout_a[83] + PIN dout_a[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END dout_a[84] + PIN dout_a[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.024 4.152 ; + END + END dout_a[85] + PIN dout_a[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.176 0.024 4.200 ; + END + END dout_a[86] + PIN dout_a[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END dout_a[87] + PIN dout_a[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.272 0.024 4.296 ; + END + END dout_a[88] + PIN dout_a[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.320 0.024 4.344 ; + END + END dout_a[89] + PIN dout_a[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END dout_a[90] + PIN dout_a[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.416 0.024 4.440 ; + END + END dout_a[91] + PIN dout_a[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.464 0.024 4.488 ; + END + END dout_a[92] + PIN dout_a[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END dout_a[93] + PIN dout_a[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.024 4.584 ; + END + END dout_a[94] + PIN dout_a[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.024 4.632 ; + END + END dout_a[95] + PIN dout_a[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END dout_a[96] + PIN dout_a[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.024 4.728 ; + END + END dout_a[97] + PIN dout_a[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.024 4.776 ; + END + END dout_a[98] + PIN dout_a[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END dout_a[99] + PIN dout_a[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.848 0.024 4.872 ; + END + END dout_a[100] + PIN dout_a[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.896 0.024 4.920 ; + END + END dout_a[101] + PIN dout_a[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END dout_a[102] + PIN dout_a[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.992 0.024 5.016 ; + END + END dout_a[103] + PIN dout_a[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.024 5.064 ; + END + END dout_a[104] + PIN dout_a[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END dout_a[105] + PIN dout_a[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.024 5.160 ; + END + END dout_a[106] + PIN dout_a[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.184 0.024 5.208 ; + END + END dout_a[107] + PIN dout_a[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END dout_a[108] + PIN dout_a[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.280 0.024 5.304 ; + END + END dout_a[109] + PIN dout_a[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END dout_a[110] + PIN dout_a[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END dout_a[111] + PIN dout_a[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.024 5.448 ; + END + END dout_a[112] + PIN dout_a[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.472 0.024 5.496 ; + END + END dout_a[113] + PIN dout_a[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END dout_a[114] + PIN dout_a[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.024 5.592 ; + END + END dout_a[115] + PIN dout_a[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.616 0.024 5.640 ; + END + END dout_a[116] + PIN dout_a[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END dout_a[117] + PIN dout_a[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.712 0.024 5.736 ; + END + END dout_a[118] + PIN dout_a[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.024 5.784 ; + END + END dout_a[119] + PIN dout_a[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END dout_a[120] + PIN dout_a[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.024 5.880 ; + END + END dout_a[121] + PIN dout_a[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.904 0.024 5.928 ; + END + END dout_a[122] + PIN dout_a[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END dout_a[123] + PIN dout_a[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.000 0.024 6.024 ; + END + END dout_a[124] + PIN dout_a[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.048 0.024 6.072 ; + END + END dout_a[125] + PIN dout_a[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END dout_a[126] + PIN dout_a[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.144 0.024 6.168 ; + END + END dout_a[127] + PIN dout_a[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.192 0.024 6.216 ; + END + END dout_a[128] + PIN dout_a[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END dout_a[129] + PIN dout_a[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.288 0.024 6.312 ; + END + END dout_a[130] + PIN dout_a[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.336 0.024 6.360 ; + END + END dout_a[131] + PIN dout_a[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END dout_a[132] + PIN dout_a[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.432 0.024 6.456 ; + END + END dout_a[133] + PIN dout_a[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.480 0.024 6.504 ; + END + END dout_a[134] + PIN dout_a[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END dout_a[135] + PIN dout_a[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.576 0.024 6.600 ; + END + END dout_a[136] + PIN dout_a[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.624 0.024 6.648 ; + END + END dout_a[137] + PIN dout_a[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END dout_a[138] + PIN dout_a[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.720 0.024 6.744 ; + END + END dout_a[139] + PIN dout_a[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.768 0.024 6.792 ; + END + END dout_a[140] + PIN dout_a[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END dout_a[141] + PIN dout_a[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.864 0.024 6.888 ; + END + END dout_a[142] + PIN dout_a[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.912 0.024 6.936 ; + END + END dout_a[143] + PIN dout_a[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END dout_a[144] + PIN dout_a[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.008 0.024 7.032 ; + END + END dout_a[145] + PIN dout_a[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.056 0.024 7.080 ; + END + END dout_a[146] + PIN dout_a[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END dout_a[147] + PIN dout_a[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.152 0.024 7.176 ; + END + END dout_a[148] + PIN dout_a[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.200 0.024 7.224 ; + END + END dout_a[149] + PIN dout_a[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END dout_a[150] + PIN dout_a[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.296 0.024 7.320 ; + END + END dout_a[151] + PIN dout_a[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.344 0.024 7.368 ; + END + END dout_a[152] + PIN dout_a[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END dout_a[153] + PIN dout_a[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.440 0.024 7.464 ; + END + END dout_a[154] + PIN dout_a[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.488 0.024 7.512 ; + END + END dout_a[155] + PIN dout_a[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END dout_a[156] + PIN dout_a[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.584 0.024 7.608 ; + END + END dout_a[157] + PIN dout_a[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.632 0.024 7.656 ; + END + END dout_a[158] + PIN dout_a[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END dout_a[159] + PIN dout_a[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.728 0.024 7.752 ; + END + END dout_a[160] + PIN dout_a[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.776 0.024 7.800 ; + END + END dout_a[161] + PIN dout_a[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END dout_a[162] + PIN dout_a[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.872 0.024 7.896 ; + END + END dout_a[163] + PIN dout_a[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.920 0.024 7.944 ; + END + END dout_a[164] + PIN dout_a[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END dout_a[165] + PIN dout_a[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.016 0.024 8.040 ; + END + END dout_a[166] + PIN dout_a[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.064 0.024 8.088 ; + END + END dout_a[167] + PIN dout_a[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END dout_a[168] + PIN dout_a[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.160 0.024 8.184 ; + END + END dout_a[169] + PIN dout_a[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.208 0.024 8.232 ; + END + END dout_a[170] + PIN dout_a[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END dout_a[171] + PIN dout_a[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.304 0.024 8.328 ; + END + END dout_a[172] + PIN dout_a[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.352 0.024 8.376 ; + END + END dout_a[173] + PIN dout_a[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END dout_a[174] + PIN dout_a[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.448 0.024 8.472 ; + END + END dout_a[175] + PIN dout_a[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.496 0.024 8.520 ; + END + END dout_a[176] + PIN dout_a[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END dout_a[177] + PIN dout_a[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.592 0.024 8.616 ; + END + END dout_a[178] + PIN dout_a[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.640 0.024 8.664 ; + END + END dout_a[179] + PIN dout_a[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END dout_a[180] + PIN dout_a[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.736 0.024 8.760 ; + END + END dout_a[181] + PIN dout_a[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.784 0.024 8.808 ; + END + END dout_a[182] + PIN dout_a[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END dout_a[183] + PIN dout_a[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.880 0.024 8.904 ; + END + END dout_a[184] + PIN dout_a[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.928 0.024 8.952 ; + END + END dout_a[185] + PIN dout_a[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END dout_a[186] + PIN dout_a[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.024 0.024 9.048 ; + END + END dout_a[187] + PIN dout_a[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.072 0.024 9.096 ; + END + END dout_a[188] + PIN dout_a[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END dout_a[189] + PIN dout_a[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.168 0.024 9.192 ; + END + END dout_a[190] + PIN dout_a[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.216 0.024 9.240 ; + END + END dout_a[191] + PIN dout_a[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.024 9.288 ; + END + END dout_a[192] + PIN dout_a[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.312 0.024 9.336 ; + END + END dout_a[193] + PIN dout_a[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.360 0.024 9.384 ; + END + END dout_a[194] + PIN dout_a[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.024 9.432 ; + END + END dout_a[195] + PIN dout_a[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.456 0.024 9.480 ; + END + END dout_a[196] + PIN dout_a[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.504 0.024 9.528 ; + END + END dout_a[197] + PIN dout_a[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END dout_a[198] + PIN dout_a[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.600 0.024 9.624 ; + END + END dout_a[199] + PIN dout_a[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.648 0.024 9.672 ; + END + END dout_a[200] + PIN dout_a[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.024 9.720 ; + END + END dout_a[201] + PIN dout_a[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.744 0.024 9.768 ; + END + END dout_a[202] + PIN dout_a[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.024 9.816 ; + END + END dout_a[203] + PIN dout_a[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.024 9.864 ; + END + END dout_a[204] + PIN dout_a[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.888 0.024 9.912 ; + END + END dout_a[205] + PIN dout_a[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.024 9.960 ; + END + END dout_a[206] + PIN dout_a[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.024 10.008 ; + END + END dout_a[207] + PIN dout_a[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.032 0.024 10.056 ; + END + END dout_a[208] + PIN dout_a[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.024 10.104 ; + END + END dout_a[209] + PIN dout_a[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.024 10.152 ; + END + END dout_a[210] + PIN dout_a[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.176 0.024 10.200 ; + END + END dout_a[211] + PIN dout_a[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.224 0.024 10.248 ; + END + END dout_a[212] + PIN dout_a[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.024 10.296 ; + END + END dout_a[213] + PIN dout_a[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.320 0.024 10.344 ; + END + END dout_a[214] + PIN dout_a[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.024 10.392 ; + END + END dout_a[215] + PIN dout_a[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END dout_a[216] + PIN dout_a[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.464 0.024 10.488 ; + END + END dout_a[217] + PIN dout_a[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.512 0.024 10.536 ; + END + END dout_a[218] + PIN dout_a[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.024 10.584 ; + END + END dout_a[219] + PIN dout_a[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.608 0.024 10.632 ; + END + END dout_a[220] + PIN dout_a[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.024 10.680 ; + END + END dout_a[221] + PIN dout_a[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.024 10.728 ; + END + END dout_a[222] + PIN dout_a[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.752 0.024 10.776 ; + END + END dout_a[223] + PIN dout_a[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.800 0.024 10.824 ; + END + END dout_a[224] + PIN dout_a[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.024 10.872 ; + END + END dout_a[225] + PIN dout_a[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.896 0.024 10.920 ; + END + END dout_a[226] + PIN dout_a[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.024 10.968 ; + END + END dout_a[227] + PIN dout_a[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.024 11.016 ; + END + END dout_a[228] + PIN dout_a[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.040 0.024 11.064 ; + END + END dout_a[229] + PIN dout_a[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.088 0.024 11.112 ; + END + END dout_a[230] + PIN dout_a[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END dout_a[231] + PIN dout_a[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.184 0.024 11.208 ; + END + END dout_a[232] + PIN dout_a[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.024 11.256 ; + END + END dout_a[233] + PIN dout_a[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.024 11.304 ; + END + END dout_a[234] + PIN dout_a[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.328 0.024 11.352 ; + END + END dout_a[235] + PIN dout_a[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.024 11.400 ; + END + END dout_a[236] + PIN dout_a[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.024 11.448 ; + END + END dout_a[237] + PIN dout_a[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.472 0.024 11.496 ; + END + END dout_a[238] + PIN dout_a[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.024 11.544 ; + END + END dout_a[239] + PIN dout_a[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.024 11.592 ; + END + END dout_a[240] + PIN dout_a[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.616 0.024 11.640 ; + END + END dout_a[241] + PIN dout_a[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.024 11.688 ; + END + END dout_a[242] + PIN dout_a[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.024 11.736 ; + END + END dout_a[243] + PIN dout_a[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.760 0.024 11.784 ; + END + END dout_a[244] + PIN dout_a[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.024 11.832 ; + END + END dout_a[245] + PIN dout_a[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END dout_a[246] + PIN dout_a[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.904 0.024 11.928 ; + END + END dout_a[247] + PIN dout_a[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.952 0.024 11.976 ; + END + END dout_a[248] + PIN dout_a[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.024 12.024 ; + END + END dout_a[249] + PIN dout_a[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.048 0.024 12.072 ; + END + END dout_a[250] + PIN dout_a[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.024 12.120 ; + END + END dout_a[251] + PIN dout_a[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.024 12.168 ; + END + END dout_a[252] + PIN dout_a[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.192 0.024 12.216 ; + END + END dout_a[253] + PIN dout_a[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.240 0.024 12.264 ; + END + END dout_a[254] + PIN dout_a[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.024 12.312 ; + END + END dout_a[255] + PIN din_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.616 0.024 23.640 ; + END + END din_a[0] + PIN din_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.024 23.688 ; + END + END din_a[1] + PIN din_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.712 0.024 23.736 ; + END + END din_a[2] + PIN din_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.760 0.024 23.784 ; + END + END din_a[3] + PIN din_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.024 23.832 ; + END + END din_a[4] + PIN din_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.856 0.024 23.880 ; + END + END din_a[5] + PIN din_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.904 0.024 23.928 ; + END + END din_a[6] + PIN din_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.024 23.976 ; + END + END din_a[7] + PIN din_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.000 0.024 24.024 ; + END + END din_a[8] + PIN din_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.048 0.024 24.072 ; + END + END din_a[9] + PIN din_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.024 24.120 ; + END + END din_a[10] + PIN din_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.144 0.024 24.168 ; + END + END din_a[11] + PIN din_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.024 24.216 ; + END + END din_a[12] + PIN din_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.024 24.264 ; + END + END din_a[13] + PIN din_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.288 0.024 24.312 ; + END + END din_a[14] + PIN din_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.336 0.024 24.360 ; + END + END din_a[15] + PIN din_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.024 24.408 ; + END + END din_a[16] + PIN din_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.432 0.024 24.456 ; + END + END din_a[17] + PIN din_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.480 0.024 24.504 ; + END + END din_a[18] + PIN din_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.024 24.552 ; + END + END din_a[19] + PIN din_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.576 0.024 24.600 ; + END + END din_a[20] + PIN din_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.624 0.024 24.648 ; + END + END din_a[21] + PIN din_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.024 24.696 ; + END + END din_a[22] + PIN din_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.720 0.024 24.744 ; + END + END din_a[23] + PIN din_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.768 0.024 24.792 ; + END + END din_a[24] + PIN din_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.024 24.840 ; + END + END din_a[25] + PIN din_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.864 0.024 24.888 ; + END + END din_a[26] + PIN din_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.912 0.024 24.936 ; + END + END din_a[27] + PIN din_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.024 24.984 ; + END + END din_a[28] + PIN din_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.008 0.024 25.032 ; + END + END din_a[29] + PIN din_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.056 0.024 25.080 ; + END + END din_a[30] + PIN din_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.024 25.128 ; + END + END din_a[31] + PIN din_a[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.152 0.024 25.176 ; + END + END din_a[32] + PIN din_a[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.200 0.024 25.224 ; + END + END din_a[33] + PIN din_a[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.024 25.272 ; + END + END din_a[34] + PIN din_a[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.296 0.024 25.320 ; + END + END din_a[35] + PIN din_a[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.344 0.024 25.368 ; + END + END din_a[36] + PIN din_a[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END din_a[37] + PIN din_a[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.440 0.024 25.464 ; + END + END din_a[38] + PIN din_a[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.488 0.024 25.512 ; + END + END din_a[39] + PIN din_a[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.024 25.560 ; + END + END din_a[40] + PIN din_a[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.584 0.024 25.608 ; + END + END din_a[41] + PIN din_a[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.024 25.656 ; + END + END din_a[42] + PIN din_a[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.024 25.704 ; + END + END din_a[43] + PIN din_a[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.728 0.024 25.752 ; + END + END din_a[44] + PIN din_a[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.776 0.024 25.800 ; + END + END din_a[45] + PIN din_a[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.024 25.848 ; + END + END din_a[46] + PIN din_a[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.872 0.024 25.896 ; + END + END din_a[47] + PIN din_a[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.920 0.024 25.944 ; + END + END din_a[48] + PIN din_a[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.024 25.992 ; + END + END din_a[49] + PIN din_a[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.016 0.024 26.040 ; + END + END din_a[50] + PIN din_a[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.064 0.024 26.088 ; + END + END din_a[51] + PIN din_a[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.024 26.136 ; + END + END din_a[52] + PIN din_a[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.160 0.024 26.184 ; + END + END din_a[53] + PIN din_a[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.208 0.024 26.232 ; + END + END din_a[54] + PIN din_a[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.024 26.280 ; + END + END din_a[55] + PIN din_a[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.304 0.024 26.328 ; + END + END din_a[56] + PIN din_a[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.352 0.024 26.376 ; + END + END din_a[57] + PIN din_a[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.024 26.424 ; + END + END din_a[58] + PIN din_a[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.448 0.024 26.472 ; + END + END din_a[59] + PIN din_a[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.496 0.024 26.520 ; + END + END din_a[60] + PIN din_a[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.024 26.568 ; + END + END din_a[61] + PIN din_a[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.592 0.024 26.616 ; + END + END din_a[62] + PIN din_a[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.640 0.024 26.664 ; + END + END din_a[63] + PIN din_a[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.024 26.712 ; + END + END din_a[64] + PIN din_a[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.736 0.024 26.760 ; + END + END din_a[65] + PIN din_a[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.784 0.024 26.808 ; + END + END din_a[66] + PIN din_a[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END din_a[67] + PIN din_a[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.880 0.024 26.904 ; + END + END din_a[68] + PIN din_a[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.928 0.024 26.952 ; + END + END din_a[69] + PIN din_a[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.024 27.000 ; + END + END din_a[70] + PIN din_a[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.024 0.024 27.048 ; + END + END din_a[71] + PIN din_a[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.072 0.024 27.096 ; + END + END din_a[72] + PIN din_a[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.024 27.144 ; + END + END din_a[73] + PIN din_a[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.168 0.024 27.192 ; + END + END din_a[74] + PIN din_a[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.216 0.024 27.240 ; + END + END din_a[75] + PIN din_a[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.024 27.288 ; + END + END din_a[76] + PIN din_a[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.312 0.024 27.336 ; + END + END din_a[77] + PIN din_a[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.360 0.024 27.384 ; + END + END din_a[78] + PIN din_a[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.024 27.432 ; + END + END din_a[79] + PIN din_a[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.456 0.024 27.480 ; + END + END din_a[80] + PIN din_a[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.504 0.024 27.528 ; + END + END din_a[81] + PIN din_a[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.024 27.576 ; + END + END din_a[82] + PIN din_a[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.600 0.024 27.624 ; + END + END din_a[83] + PIN din_a[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.648 0.024 27.672 ; + END + END din_a[84] + PIN din_a[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.024 27.720 ; + END + END din_a[85] + PIN din_a[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.744 0.024 27.768 ; + END + END din_a[86] + PIN din_a[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.792 0.024 27.816 ; + END + END din_a[87] + PIN din_a[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.024 27.864 ; + END + END din_a[88] + PIN din_a[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.888 0.024 27.912 ; + END + END din_a[89] + PIN din_a[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.936 0.024 27.960 ; + END + END din_a[90] + PIN din_a[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.024 28.008 ; + END + END din_a[91] + PIN din_a[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.032 0.024 28.056 ; + END + END din_a[92] + PIN din_a[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.080 0.024 28.104 ; + END + END din_a[93] + PIN din_a[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.024 28.152 ; + END + END din_a[94] + PIN din_a[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.176 0.024 28.200 ; + END + END din_a[95] + PIN din_a[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.224 0.024 28.248 ; + END + END din_a[96] + PIN din_a[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END din_a[97] + PIN din_a[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.320 0.024 28.344 ; + END + END din_a[98] + PIN din_a[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.368 0.024 28.392 ; + END + END din_a[99] + PIN din_a[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.024 28.440 ; + END + END din_a[100] + PIN din_a[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.464 0.024 28.488 ; + END + END din_a[101] + PIN din_a[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.512 0.024 28.536 ; + END + END din_a[102] + PIN din_a[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.024 28.584 ; + END + END din_a[103] + PIN din_a[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.608 0.024 28.632 ; + END + END din_a[104] + PIN din_a[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.656 0.024 28.680 ; + END + END din_a[105] + PIN din_a[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.024 28.728 ; + END + END din_a[106] + PIN din_a[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.752 0.024 28.776 ; + END + END din_a[107] + PIN din_a[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.800 0.024 28.824 ; + END + END din_a[108] + PIN din_a[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.024 28.872 ; + END + END din_a[109] + PIN din_a[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.896 0.024 28.920 ; + END + END din_a[110] + PIN din_a[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.944 0.024 28.968 ; + END + END din_a[111] + PIN din_a[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.024 29.016 ; + END + END din_a[112] + PIN din_a[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.040 0.024 29.064 ; + END + END din_a[113] + PIN din_a[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.088 0.024 29.112 ; + END + END din_a[114] + PIN din_a[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.024 29.160 ; + END + END din_a[115] + PIN din_a[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.184 0.024 29.208 ; + END + END din_a[116] + PIN din_a[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.232 0.024 29.256 ; + END + END din_a[117] + PIN din_a[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.024 29.304 ; + END + END din_a[118] + PIN din_a[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.328 0.024 29.352 ; + END + END din_a[119] + PIN din_a[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.376 0.024 29.400 ; + END + END din_a[120] + PIN din_a[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.024 29.448 ; + END + END din_a[121] + PIN din_a[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.472 0.024 29.496 ; + END + END din_a[122] + PIN din_a[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.520 0.024 29.544 ; + END + END din_a[123] + PIN din_a[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.024 29.592 ; + END + END din_a[124] + PIN din_a[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.616 0.024 29.640 ; + END + END din_a[125] + PIN din_a[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.664 0.024 29.688 ; + END + END din_a[126] + PIN din_a[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.024 29.736 ; + END + END din_a[127] + PIN din_a[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.760 0.024 29.784 ; + END + END din_a[128] + PIN din_a[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.808 0.024 29.832 ; + END + END din_a[129] + PIN din_a[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.024 29.880 ; + END + END din_a[130] + PIN din_a[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.904 0.024 29.928 ; + END + END din_a[131] + PIN din_a[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.952 0.024 29.976 ; + END + END din_a[132] + PIN din_a[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.024 30.024 ; + END + END din_a[133] + PIN din_a[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.048 0.024 30.072 ; + END + END din_a[134] + PIN din_a[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.096 0.024 30.120 ; + END + END din_a[135] + PIN din_a[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.024 30.168 ; + END + END din_a[136] + PIN din_a[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.192 0.024 30.216 ; + END + END din_a[137] + PIN din_a[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.240 0.024 30.264 ; + END + END din_a[138] + PIN din_a[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.024 30.312 ; + END + END din_a[139] + PIN din_a[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.336 0.024 30.360 ; + END + END din_a[140] + PIN din_a[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.384 0.024 30.408 ; + END + END din_a[141] + PIN din_a[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.024 30.456 ; + END + END din_a[142] + PIN din_a[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.480 0.024 30.504 ; + END + END din_a[143] + PIN din_a[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.528 0.024 30.552 ; + END + END din_a[144] + PIN din_a[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.024 30.600 ; + END + END din_a[145] + PIN din_a[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.624 0.024 30.648 ; + END + END din_a[146] + PIN din_a[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.672 0.024 30.696 ; + END + END din_a[147] + PIN din_a[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.024 30.744 ; + END + END din_a[148] + PIN din_a[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.768 0.024 30.792 ; + END + END din_a[149] + PIN din_a[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.816 0.024 30.840 ; + END + END din_a[150] + PIN din_a[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.024 30.888 ; + END + END din_a[151] + PIN din_a[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.912 0.024 30.936 ; + END + END din_a[152] + PIN din_a[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.960 0.024 30.984 ; + END + END din_a[153] + PIN din_a[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.024 31.032 ; + END + END din_a[154] + PIN din_a[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.056 0.024 31.080 ; + END + END din_a[155] + PIN din_a[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.104 0.024 31.128 ; + END + END din_a[156] + PIN din_a[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END din_a[157] + PIN din_a[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.200 0.024 31.224 ; + END + END din_a[158] + PIN din_a[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.248 0.024 31.272 ; + END + END din_a[159] + PIN din_a[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.024 31.320 ; + END + END din_a[160] + PIN din_a[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.344 0.024 31.368 ; + END + END din_a[161] + PIN din_a[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.392 0.024 31.416 ; + END + END din_a[162] + PIN din_a[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.024 31.464 ; + END + END din_a[163] + PIN din_a[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.488 0.024 31.512 ; + END + END din_a[164] + PIN din_a[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.536 0.024 31.560 ; + END + END din_a[165] + PIN din_a[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.024 31.608 ; + END + END din_a[166] + PIN din_a[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.632 0.024 31.656 ; + END + END din_a[167] + PIN din_a[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.680 0.024 31.704 ; + END + END din_a[168] + PIN din_a[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.024 31.752 ; + END + END din_a[169] + PIN din_a[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.776 0.024 31.800 ; + END + END din_a[170] + PIN din_a[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.824 0.024 31.848 ; + END + END din_a[171] + PIN din_a[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.872 0.024 31.896 ; + END + END din_a[172] + PIN din_a[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.920 0.024 31.944 ; + END + END din_a[173] + PIN din_a[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.968 0.024 31.992 ; + END + END din_a[174] + PIN din_a[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.016 0.024 32.040 ; + END + END din_a[175] + PIN din_a[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.064 0.024 32.088 ; + END + END din_a[176] + PIN din_a[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.112 0.024 32.136 ; + END + END din_a[177] + PIN din_a[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.160 0.024 32.184 ; + END + END din_a[178] + PIN din_a[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.208 0.024 32.232 ; + END + END din_a[179] + PIN din_a[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.256 0.024 32.280 ; + END + END din_a[180] + PIN din_a[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.304 0.024 32.328 ; + END + END din_a[181] + PIN din_a[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.352 0.024 32.376 ; + END + END din_a[182] + PIN din_a[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.400 0.024 32.424 ; + END + END din_a[183] + PIN din_a[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.448 0.024 32.472 ; + END + END din_a[184] + PIN din_a[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.496 0.024 32.520 ; + END + END din_a[185] + PIN din_a[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.544 0.024 32.568 ; + END + END din_a[186] + PIN din_a[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.592 0.024 32.616 ; + END + END din_a[187] + PIN din_a[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.640 0.024 32.664 ; + END + END din_a[188] + PIN din_a[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.688 0.024 32.712 ; + END + END din_a[189] + PIN din_a[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.736 0.024 32.760 ; + END + END din_a[190] + PIN din_a[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.784 0.024 32.808 ; + END + END din_a[191] + PIN din_a[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.832 0.024 32.856 ; + END + END din_a[192] + PIN din_a[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.880 0.024 32.904 ; + END + END din_a[193] + PIN din_a[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.928 0.024 32.952 ; + END + END din_a[194] + PIN din_a[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.976 0.024 33.000 ; + END + END din_a[195] + PIN din_a[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.024 0.024 33.048 ; + END + END din_a[196] + PIN din_a[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.072 0.024 33.096 ; + END + END din_a[197] + PIN din_a[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.120 0.024 33.144 ; + END + END din_a[198] + PIN din_a[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.168 0.024 33.192 ; + END + END din_a[199] + PIN din_a[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.216 0.024 33.240 ; + END + END din_a[200] + PIN din_a[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.264 0.024 33.288 ; + END + END din_a[201] + PIN din_a[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.312 0.024 33.336 ; + END + END din_a[202] + PIN din_a[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.360 0.024 33.384 ; + END + END din_a[203] + PIN din_a[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.408 0.024 33.432 ; + END + END din_a[204] + PIN din_a[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.456 0.024 33.480 ; + END + END din_a[205] + PIN din_a[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.504 0.024 33.528 ; + END + END din_a[206] + PIN din_a[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.552 0.024 33.576 ; + END + END din_a[207] + PIN din_a[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.600 0.024 33.624 ; + END + END din_a[208] + PIN din_a[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.648 0.024 33.672 ; + END + END din_a[209] + PIN din_a[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.696 0.024 33.720 ; + END + END din_a[210] + PIN din_a[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.744 0.024 33.768 ; + END + END din_a[211] + PIN din_a[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.792 0.024 33.816 ; + END + END din_a[212] + PIN din_a[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.840 0.024 33.864 ; + END + END din_a[213] + PIN din_a[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.888 0.024 33.912 ; + END + END din_a[214] + PIN din_a[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.936 0.024 33.960 ; + END + END din_a[215] + PIN din_a[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.984 0.024 34.008 ; + END + END din_a[216] + PIN din_a[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.032 0.024 34.056 ; + END + END din_a[217] + PIN din_a[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.080 0.024 34.104 ; + END + END din_a[218] + PIN din_a[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.128 0.024 34.152 ; + END + END din_a[219] + PIN din_a[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.176 0.024 34.200 ; + END + END din_a[220] + PIN din_a[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.224 0.024 34.248 ; + END + END din_a[221] + PIN din_a[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.272 0.024 34.296 ; + END + END din_a[222] + PIN din_a[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.320 0.024 34.344 ; + END + END din_a[223] + PIN din_a[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.368 0.024 34.392 ; + END + END din_a[224] + PIN din_a[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.416 0.024 34.440 ; + END + END din_a[225] + PIN din_a[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.464 0.024 34.488 ; + END + END din_a[226] + PIN din_a[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.512 0.024 34.536 ; + END + END din_a[227] + PIN din_a[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.560 0.024 34.584 ; + END + END din_a[228] + PIN din_a[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.608 0.024 34.632 ; + END + END din_a[229] + PIN din_a[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.656 0.024 34.680 ; + END + END din_a[230] + PIN din_a[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.704 0.024 34.728 ; + END + END din_a[231] + PIN din_a[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.752 0.024 34.776 ; + END + END din_a[232] + PIN din_a[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.800 0.024 34.824 ; + END + END din_a[233] + PIN din_a[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.848 0.024 34.872 ; + END + END din_a[234] + PIN din_a[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.896 0.024 34.920 ; + END + END din_a[235] + PIN din_a[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.944 0.024 34.968 ; + END + END din_a[236] + PIN din_a[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.992 0.024 35.016 ; + END + END din_a[237] + PIN din_a[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.040 0.024 35.064 ; + END + END din_a[238] + PIN din_a[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.088 0.024 35.112 ; + END + END din_a[239] + PIN din_a[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.136 0.024 35.160 ; + END + END din_a[240] + PIN din_a[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.184 0.024 35.208 ; + END + END din_a[241] + PIN din_a[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.232 0.024 35.256 ; + END + END din_a[242] + PIN din_a[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.280 0.024 35.304 ; + END + END din_a[243] + PIN din_a[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.328 0.024 35.352 ; + END + END din_a[244] + PIN din_a[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.376 0.024 35.400 ; + END + END din_a[245] + PIN din_a[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.424 0.024 35.448 ; + END + END din_a[246] + PIN din_a[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.472 0.024 35.496 ; + END + END din_a[247] + PIN din_a[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.520 0.024 35.544 ; + END + END din_a[248] + PIN din_a[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.568 0.024 35.592 ; + END + END din_a[249] + PIN din_a[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.616 0.024 35.640 ; + END + END din_a[250] + PIN din_a[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.664 0.024 35.688 ; + END + END din_a[251] + PIN din_a[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.712 0.024 35.736 ; + END + END din_a[252] + PIN din_a[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END din_a[253] + PIN din_a[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.808 0.024 35.832 ; + END + END din_a[254] + PIN din_a[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.856 0.024 35.880 ; + END + END din_a[255] + PIN addr_a[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.184 0.024 47.208 ; + END + END addr_a[0] + PIN addr_a[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.232 0.024 47.256 ; + END + END addr_a[1] + PIN addr_a[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.280 0.024 47.304 ; + END + END addr_a[2] + PIN addr_a[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.328 0.024 47.352 ; + END + END addr_a[3] + PIN addr_a[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.376 0.024 47.400 ; + END + END addr_a[4] + PIN addr_a[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.424 0.024 47.448 ; + END + END addr_a[5] + PIN addr_a[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.472 0.024 47.496 ; + END + END addr_a[6] + PIN addr_a[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.520 0.024 47.544 ; + END + END addr_a[7] + PIN dout_b[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.848 0.024 58.872 ; + END + END dout_b[0] + PIN dout_b[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.896 0.024 58.920 ; + END + END dout_b[1] + PIN dout_b[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.944 0.024 58.968 ; + END + END dout_b[2] + PIN dout_b[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.992 0.024 59.016 ; + END + END dout_b[3] + PIN dout_b[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.040 0.024 59.064 ; + END + END dout_b[4] + PIN dout_b[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.088 0.024 59.112 ; + END + END dout_b[5] + PIN dout_b[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.136 0.024 59.160 ; + END + END dout_b[6] + PIN dout_b[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.184 0.024 59.208 ; + END + END dout_b[7] + PIN dout_b[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.232 0.024 59.256 ; + END + END dout_b[8] + PIN dout_b[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.280 0.024 59.304 ; + END + END dout_b[9] + PIN dout_b[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.328 0.024 59.352 ; + END + END dout_b[10] + PIN dout_b[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.376 0.024 59.400 ; + END + END dout_b[11] + PIN dout_b[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.424 0.024 59.448 ; + END + END dout_b[12] + PIN dout_b[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.472 0.024 59.496 ; + END + END dout_b[13] + PIN dout_b[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.520 0.024 59.544 ; + END + END dout_b[14] + PIN dout_b[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.568 0.024 59.592 ; + END + END dout_b[15] + PIN dout_b[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.616 0.024 59.640 ; + END + END dout_b[16] + PIN dout_b[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.664 0.024 59.688 ; + END + END dout_b[17] + PIN dout_b[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.712 0.024 59.736 ; + END + END dout_b[18] + PIN dout_b[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.760 0.024 59.784 ; + END + END dout_b[19] + PIN dout_b[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.808 0.024 59.832 ; + END + END dout_b[20] + PIN dout_b[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.856 0.024 59.880 ; + END + END dout_b[21] + PIN dout_b[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.904 0.024 59.928 ; + END + END dout_b[22] + PIN dout_b[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.952 0.024 59.976 ; + END + END dout_b[23] + PIN dout_b[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.000 0.024 60.024 ; + END + END dout_b[24] + PIN dout_b[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.048 0.024 60.072 ; + END + END dout_b[25] + PIN dout_b[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.096 0.024 60.120 ; + END + END dout_b[26] + PIN dout_b[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.144 0.024 60.168 ; + END + END dout_b[27] + PIN dout_b[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.192 0.024 60.216 ; + END + END dout_b[28] + PIN dout_b[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.240 0.024 60.264 ; + END + END dout_b[29] + PIN dout_b[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.288 0.024 60.312 ; + END + END dout_b[30] + PIN dout_b[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.336 0.024 60.360 ; + END + END dout_b[31] + PIN dout_b[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.384 0.024 60.408 ; + END + END dout_b[32] + PIN dout_b[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.432 0.024 60.456 ; + END + END dout_b[33] + PIN dout_b[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.480 0.024 60.504 ; + END + END dout_b[34] + PIN dout_b[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.528 0.024 60.552 ; + END + END dout_b[35] + PIN dout_b[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.576 0.024 60.600 ; + END + END dout_b[36] + PIN dout_b[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.624 0.024 60.648 ; + END + END dout_b[37] + PIN dout_b[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.672 0.024 60.696 ; + END + END dout_b[38] + PIN dout_b[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.720 0.024 60.744 ; + END + END dout_b[39] + PIN dout_b[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.768 0.024 60.792 ; + END + END dout_b[40] + PIN dout_b[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.816 0.024 60.840 ; + END + END dout_b[41] + PIN dout_b[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.864 0.024 60.888 ; + END + END dout_b[42] + PIN dout_b[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.912 0.024 60.936 ; + END + END dout_b[43] + PIN dout_b[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.960 0.024 60.984 ; + END + END dout_b[44] + PIN dout_b[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.008 0.024 61.032 ; + END + END dout_b[45] + PIN dout_b[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.056 0.024 61.080 ; + END + END dout_b[46] + PIN dout_b[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.104 0.024 61.128 ; + END + END dout_b[47] + PIN dout_b[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.152 0.024 61.176 ; + END + END dout_b[48] + PIN dout_b[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.200 0.024 61.224 ; + END + END dout_b[49] + PIN dout_b[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.248 0.024 61.272 ; + END + END dout_b[50] + PIN dout_b[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.296 0.024 61.320 ; + END + END dout_b[51] + PIN dout_b[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.344 0.024 61.368 ; + END + END dout_b[52] + PIN dout_b[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.392 0.024 61.416 ; + END + END dout_b[53] + PIN dout_b[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.440 0.024 61.464 ; + END + END dout_b[54] + PIN dout_b[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.488 0.024 61.512 ; + END + END dout_b[55] + PIN dout_b[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.536 0.024 61.560 ; + END + END dout_b[56] + PIN dout_b[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.584 0.024 61.608 ; + END + END dout_b[57] + PIN dout_b[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.632 0.024 61.656 ; + END + END dout_b[58] + PIN dout_b[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.680 0.024 61.704 ; + END + END dout_b[59] + PIN dout_b[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.728 0.024 61.752 ; + END + END dout_b[60] + PIN dout_b[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.776 0.024 61.800 ; + END + END dout_b[61] + PIN dout_b[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.824 0.024 61.848 ; + END + END dout_b[62] + PIN dout_b[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.872 0.024 61.896 ; + END + END dout_b[63] + PIN dout_b[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.920 0.024 61.944 ; + END + END dout_b[64] + PIN dout_b[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.968 0.024 61.992 ; + END + END dout_b[65] + PIN dout_b[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.016 0.024 62.040 ; + END + END dout_b[66] + PIN dout_b[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.064 0.024 62.088 ; + END + END dout_b[67] + PIN dout_b[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.112 0.024 62.136 ; + END + END dout_b[68] + PIN dout_b[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.160 0.024 62.184 ; + END + END dout_b[69] + PIN dout_b[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.208 0.024 62.232 ; + END + END dout_b[70] + PIN dout_b[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.256 0.024 62.280 ; + END + END dout_b[71] + PIN dout_b[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.304 0.024 62.328 ; + END + END dout_b[72] + PIN dout_b[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.352 0.024 62.376 ; + END + END dout_b[73] + PIN dout_b[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.400 0.024 62.424 ; + END + END dout_b[74] + PIN dout_b[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.448 0.024 62.472 ; + END + END dout_b[75] + PIN dout_b[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.496 0.024 62.520 ; + END + END dout_b[76] + PIN dout_b[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.544 0.024 62.568 ; + END + END dout_b[77] + PIN dout_b[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.592 0.024 62.616 ; + END + END dout_b[78] + PIN dout_b[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.640 0.024 62.664 ; + END + END dout_b[79] + PIN dout_b[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.688 0.024 62.712 ; + END + END dout_b[80] + PIN dout_b[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.736 0.024 62.760 ; + END + END dout_b[81] + PIN dout_b[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.784 0.024 62.808 ; + END + END dout_b[82] + PIN dout_b[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.832 0.024 62.856 ; + END + END dout_b[83] + PIN dout_b[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.880 0.024 62.904 ; + END + END dout_b[84] + PIN dout_b[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.928 0.024 62.952 ; + END + END dout_b[85] + PIN dout_b[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.976 0.024 63.000 ; + END + END dout_b[86] + PIN dout_b[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.024 0.024 63.048 ; + END + END dout_b[87] + PIN dout_b[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.072 0.024 63.096 ; + END + END dout_b[88] + PIN dout_b[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.120 0.024 63.144 ; + END + END dout_b[89] + PIN dout_b[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.168 0.024 63.192 ; + END + END dout_b[90] + PIN dout_b[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.216 0.024 63.240 ; + END + END dout_b[91] + PIN dout_b[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.264 0.024 63.288 ; + END + END dout_b[92] + PIN dout_b[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.312 0.024 63.336 ; + END + END dout_b[93] + PIN dout_b[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.360 0.024 63.384 ; + END + END dout_b[94] + PIN dout_b[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.408 0.024 63.432 ; + END + END dout_b[95] + PIN dout_b[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.456 0.024 63.480 ; + END + END dout_b[96] + PIN dout_b[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.504 0.024 63.528 ; + END + END dout_b[97] + PIN dout_b[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.552 0.024 63.576 ; + END + END dout_b[98] + PIN dout_b[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.600 0.024 63.624 ; + END + END dout_b[99] + PIN dout_b[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.648 0.024 63.672 ; + END + END dout_b[100] + PIN dout_b[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.696 0.024 63.720 ; + END + END dout_b[101] + PIN dout_b[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.744 0.024 63.768 ; + END + END dout_b[102] + PIN dout_b[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.792 0.024 63.816 ; + END + END dout_b[103] + PIN dout_b[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.840 0.024 63.864 ; + END + END dout_b[104] + PIN dout_b[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.888 0.024 63.912 ; + END + END dout_b[105] + PIN dout_b[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.936 0.024 63.960 ; + END + END dout_b[106] + PIN dout_b[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.984 0.024 64.008 ; + END + END dout_b[107] + PIN dout_b[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.032 0.024 64.056 ; + END + END dout_b[108] + PIN dout_b[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.080 0.024 64.104 ; + END + END dout_b[109] + PIN dout_b[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.128 0.024 64.152 ; + END + END dout_b[110] + PIN dout_b[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.176 0.024 64.200 ; + END + END dout_b[111] + PIN dout_b[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.224 0.024 64.248 ; + END + END dout_b[112] + PIN dout_b[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.272 0.024 64.296 ; + END + END dout_b[113] + PIN dout_b[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.320 0.024 64.344 ; + END + END dout_b[114] + PIN dout_b[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.368 0.024 64.392 ; + END + END dout_b[115] + PIN dout_b[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.416 0.024 64.440 ; + END + END dout_b[116] + PIN dout_b[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.464 0.024 64.488 ; + END + END dout_b[117] + PIN dout_b[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.512 0.024 64.536 ; + END + END dout_b[118] + PIN dout_b[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.560 0.024 64.584 ; + END + END dout_b[119] + PIN dout_b[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.608 0.024 64.632 ; + END + END dout_b[120] + PIN dout_b[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.656 0.024 64.680 ; + END + END dout_b[121] + PIN dout_b[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.704 0.024 64.728 ; + END + END dout_b[122] + PIN dout_b[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.752 0.024 64.776 ; + END + END dout_b[123] + PIN dout_b[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.800 0.024 64.824 ; + END + END dout_b[124] + PIN dout_b[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.848 0.024 64.872 ; + END + END dout_b[125] + PIN dout_b[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.896 0.024 64.920 ; + END + END dout_b[126] + PIN dout_b[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.944 0.024 64.968 ; + END + END dout_b[127] + PIN dout_b[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.992 0.024 65.016 ; + END + END dout_b[128] + PIN dout_b[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.040 0.024 65.064 ; + END + END dout_b[129] + PIN dout_b[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.088 0.024 65.112 ; + END + END dout_b[130] + PIN dout_b[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.136 0.024 65.160 ; + END + END dout_b[131] + PIN dout_b[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.184 0.024 65.208 ; + END + END dout_b[132] + PIN dout_b[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.232 0.024 65.256 ; + END + END dout_b[133] + PIN dout_b[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.280 0.024 65.304 ; + END + END dout_b[134] + PIN dout_b[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.328 0.024 65.352 ; + END + END dout_b[135] + PIN dout_b[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.376 0.024 65.400 ; + END + END dout_b[136] + PIN dout_b[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.424 0.024 65.448 ; + END + END dout_b[137] + PIN dout_b[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.472 0.024 65.496 ; + END + END dout_b[138] + PIN dout_b[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.520 0.024 65.544 ; + END + END dout_b[139] + PIN dout_b[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.568 0.024 65.592 ; + END + END dout_b[140] + PIN dout_b[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.616 0.024 65.640 ; + END + END dout_b[141] + PIN dout_b[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.664 0.024 65.688 ; + END + END dout_b[142] + PIN dout_b[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.712 0.024 65.736 ; + END + END dout_b[143] + PIN dout_b[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.760 0.024 65.784 ; + END + END dout_b[144] + PIN dout_b[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.808 0.024 65.832 ; + END + END dout_b[145] + PIN dout_b[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.856 0.024 65.880 ; + END + END dout_b[146] + PIN dout_b[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.904 0.024 65.928 ; + END + END dout_b[147] + PIN dout_b[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.952 0.024 65.976 ; + END + END dout_b[148] + PIN dout_b[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.000 0.024 66.024 ; + END + END dout_b[149] + PIN dout_b[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.048 0.024 66.072 ; + END + END dout_b[150] + PIN dout_b[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.096 0.024 66.120 ; + END + END dout_b[151] + PIN dout_b[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.144 0.024 66.168 ; + END + END dout_b[152] + PIN dout_b[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.192 0.024 66.216 ; + END + END dout_b[153] + PIN dout_b[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.240 0.024 66.264 ; + END + END dout_b[154] + PIN dout_b[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.288 0.024 66.312 ; + END + END dout_b[155] + PIN dout_b[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.336 0.024 66.360 ; + END + END dout_b[156] + PIN dout_b[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.384 0.024 66.408 ; + END + END dout_b[157] + PIN dout_b[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.432 0.024 66.456 ; + END + END dout_b[158] + PIN dout_b[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.480 0.024 66.504 ; + END + END dout_b[159] + PIN dout_b[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.528 0.024 66.552 ; + END + END dout_b[160] + PIN dout_b[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.576 0.024 66.600 ; + END + END dout_b[161] + PIN dout_b[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.624 0.024 66.648 ; + END + END dout_b[162] + PIN dout_b[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.672 0.024 66.696 ; + END + END dout_b[163] + PIN dout_b[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.720 0.024 66.744 ; + END + END dout_b[164] + PIN dout_b[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.768 0.024 66.792 ; + END + END dout_b[165] + PIN dout_b[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.816 0.024 66.840 ; + END + END dout_b[166] + PIN dout_b[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.864 0.024 66.888 ; + END + END dout_b[167] + PIN dout_b[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.912 0.024 66.936 ; + END + END dout_b[168] + PIN dout_b[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.960 0.024 66.984 ; + END + END dout_b[169] + PIN dout_b[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.008 0.024 67.032 ; + END + END dout_b[170] + PIN dout_b[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.056 0.024 67.080 ; + END + END dout_b[171] + PIN dout_b[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.104 0.024 67.128 ; + END + END dout_b[172] + PIN dout_b[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.152 0.024 67.176 ; + END + END dout_b[173] + PIN dout_b[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.200 0.024 67.224 ; + END + END dout_b[174] + PIN dout_b[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.248 0.024 67.272 ; + END + END dout_b[175] + PIN dout_b[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.296 0.024 67.320 ; + END + END dout_b[176] + PIN dout_b[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.344 0.024 67.368 ; + END + END dout_b[177] + PIN dout_b[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.392 0.024 67.416 ; + END + END dout_b[178] + PIN dout_b[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.440 0.024 67.464 ; + END + END dout_b[179] + PIN dout_b[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.488 0.024 67.512 ; + END + END dout_b[180] + PIN dout_b[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.536 0.024 67.560 ; + END + END dout_b[181] + PIN dout_b[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.584 0.024 67.608 ; + END + END dout_b[182] + PIN dout_b[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.632 0.024 67.656 ; + END + END dout_b[183] + PIN dout_b[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.680 0.024 67.704 ; + END + END dout_b[184] + PIN dout_b[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.728 0.024 67.752 ; + END + END dout_b[185] + PIN dout_b[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.776 0.024 67.800 ; + END + END dout_b[186] + PIN dout_b[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.824 0.024 67.848 ; + END + END dout_b[187] + PIN dout_b[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.872 0.024 67.896 ; + END + END dout_b[188] + PIN dout_b[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.920 0.024 67.944 ; + END + END dout_b[189] + PIN dout_b[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.968 0.024 67.992 ; + END + END dout_b[190] + PIN dout_b[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.016 0.024 68.040 ; + END + END dout_b[191] + PIN dout_b[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.064 0.024 68.088 ; + END + END dout_b[192] + PIN dout_b[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.112 0.024 68.136 ; + END + END dout_b[193] + PIN dout_b[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.160 0.024 68.184 ; + END + END dout_b[194] + PIN dout_b[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.208 0.024 68.232 ; + END + END dout_b[195] + PIN dout_b[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.256 0.024 68.280 ; + END + END dout_b[196] + PIN dout_b[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.304 0.024 68.328 ; + END + END dout_b[197] + PIN dout_b[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.352 0.024 68.376 ; + END + END dout_b[198] + PIN dout_b[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.400 0.024 68.424 ; + END + END dout_b[199] + PIN dout_b[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.448 0.024 68.472 ; + END + END dout_b[200] + PIN dout_b[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.496 0.024 68.520 ; + END + END dout_b[201] + PIN dout_b[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.544 0.024 68.568 ; + END + END dout_b[202] + PIN dout_b[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.592 0.024 68.616 ; + END + END dout_b[203] + PIN dout_b[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.640 0.024 68.664 ; + END + END dout_b[204] + PIN dout_b[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.688 0.024 68.712 ; + END + END dout_b[205] + PIN dout_b[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.736 0.024 68.760 ; + END + END dout_b[206] + PIN dout_b[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.784 0.024 68.808 ; + END + END dout_b[207] + PIN dout_b[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.832 0.024 68.856 ; + END + END dout_b[208] + PIN dout_b[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.880 0.024 68.904 ; + END + END dout_b[209] + PIN dout_b[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.928 0.024 68.952 ; + END + END dout_b[210] + PIN dout_b[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.976 0.024 69.000 ; + END + END dout_b[211] + PIN dout_b[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.024 0.024 69.048 ; + END + END dout_b[212] + PIN dout_b[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.072 0.024 69.096 ; + END + END dout_b[213] + PIN dout_b[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.120 0.024 69.144 ; + END + END dout_b[214] + PIN dout_b[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.168 0.024 69.192 ; + END + END dout_b[215] + PIN dout_b[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.216 0.024 69.240 ; + END + END dout_b[216] + PIN dout_b[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.264 0.024 69.288 ; + END + END dout_b[217] + PIN dout_b[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.312 0.024 69.336 ; + END + END dout_b[218] + PIN dout_b[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.360 0.024 69.384 ; + END + END dout_b[219] + PIN dout_b[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.408 0.024 69.432 ; + END + END dout_b[220] + PIN dout_b[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.456 0.024 69.480 ; + END + END dout_b[221] + PIN dout_b[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.504 0.024 69.528 ; + END + END dout_b[222] + PIN dout_b[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.552 0.024 69.576 ; + END + END dout_b[223] + PIN dout_b[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.600 0.024 69.624 ; + END + END dout_b[224] + PIN dout_b[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.648 0.024 69.672 ; + END + END dout_b[225] + PIN dout_b[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.696 0.024 69.720 ; + END + END dout_b[226] + PIN dout_b[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.744 0.024 69.768 ; + END + END dout_b[227] + PIN dout_b[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.792 0.024 69.816 ; + END + END dout_b[228] + PIN dout_b[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.840 0.024 69.864 ; + END + END dout_b[229] + PIN dout_b[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.888 0.024 69.912 ; + END + END dout_b[230] + PIN dout_b[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.936 0.024 69.960 ; + END + END dout_b[231] + PIN dout_b[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.984 0.024 70.008 ; + END + END dout_b[232] + PIN dout_b[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.032 0.024 70.056 ; + END + END dout_b[233] + PIN dout_b[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.080 0.024 70.104 ; + END + END dout_b[234] + PIN dout_b[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.128 0.024 70.152 ; + END + END dout_b[235] + PIN dout_b[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.176 0.024 70.200 ; + END + END dout_b[236] + PIN dout_b[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.224 0.024 70.248 ; + END + END dout_b[237] + PIN dout_b[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.272 0.024 70.296 ; + END + END dout_b[238] + PIN dout_b[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.320 0.024 70.344 ; + END + END dout_b[239] + PIN dout_b[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.368 0.024 70.392 ; + END + END dout_b[240] + PIN dout_b[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.416 0.024 70.440 ; + END + END dout_b[241] + PIN dout_b[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.464 0.024 70.488 ; + END + END dout_b[242] + PIN dout_b[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.512 0.024 70.536 ; + END + END dout_b[243] + PIN dout_b[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.560 0.024 70.584 ; + END + END dout_b[244] + PIN dout_b[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.608 0.024 70.632 ; + END + END dout_b[245] + PIN dout_b[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.656 0.024 70.680 ; + END + END dout_b[246] + PIN dout_b[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.704 0.024 70.728 ; + END + END dout_b[247] + PIN dout_b[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.752 0.024 70.776 ; + END + END dout_b[248] + PIN dout_b[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.800 0.024 70.824 ; + END + END dout_b[249] + PIN dout_b[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.848 0.024 70.872 ; + END + END dout_b[250] + PIN dout_b[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.896 0.024 70.920 ; + END + END dout_b[251] + PIN dout_b[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.944 0.024 70.968 ; + END + END dout_b[252] + PIN dout_b[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.992 0.024 71.016 ; + END + END dout_b[253] + PIN dout_b[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.040 0.024 71.064 ; + END + END dout_b[254] + PIN dout_b[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.088 0.024 71.112 ; + END + END dout_b[255] + PIN din_b[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.416 0.024 82.440 ; + END + END din_b[0] + PIN din_b[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.464 0.024 82.488 ; + END + END din_b[1] + PIN din_b[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.512 0.024 82.536 ; + END + END din_b[2] + PIN din_b[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.560 0.024 82.584 ; + END + END din_b[3] + PIN din_b[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.608 0.024 82.632 ; + END + END din_b[4] + PIN din_b[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.656 0.024 82.680 ; + END + END din_b[5] + PIN din_b[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.704 0.024 82.728 ; + END + END din_b[6] + PIN din_b[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.752 0.024 82.776 ; + END + END din_b[7] + PIN din_b[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.800 0.024 82.824 ; + END + END din_b[8] + PIN din_b[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.848 0.024 82.872 ; + END + END din_b[9] + PIN din_b[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.896 0.024 82.920 ; + END + END din_b[10] + PIN din_b[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.944 0.024 82.968 ; + END + END din_b[11] + PIN din_b[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.992 0.024 83.016 ; + END + END din_b[12] + PIN din_b[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.040 0.024 83.064 ; + END + END din_b[13] + PIN din_b[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.088 0.024 83.112 ; + END + END din_b[14] + PIN din_b[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.136 0.024 83.160 ; + END + END din_b[15] + PIN din_b[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.184 0.024 83.208 ; + END + END din_b[16] + PIN din_b[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.232 0.024 83.256 ; + END + END din_b[17] + PIN din_b[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.280 0.024 83.304 ; + END + END din_b[18] + PIN din_b[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.328 0.024 83.352 ; + END + END din_b[19] + PIN din_b[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.376 0.024 83.400 ; + END + END din_b[20] + PIN din_b[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.424 0.024 83.448 ; + END + END din_b[21] + PIN din_b[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.472 0.024 83.496 ; + END + END din_b[22] + PIN din_b[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.520 0.024 83.544 ; + END + END din_b[23] + PIN din_b[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.568 0.024 83.592 ; + END + END din_b[24] + PIN din_b[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.616 0.024 83.640 ; + END + END din_b[25] + PIN din_b[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.664 0.024 83.688 ; + END + END din_b[26] + PIN din_b[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.712 0.024 83.736 ; + END + END din_b[27] + PIN din_b[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.760 0.024 83.784 ; + END + END din_b[28] + PIN din_b[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.808 0.024 83.832 ; + END + END din_b[29] + PIN din_b[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.856 0.024 83.880 ; + END + END din_b[30] + PIN din_b[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.904 0.024 83.928 ; + END + END din_b[31] + PIN din_b[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.952 0.024 83.976 ; + END + END din_b[32] + PIN din_b[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.000 0.024 84.024 ; + END + END din_b[33] + PIN din_b[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.048 0.024 84.072 ; + END + END din_b[34] + PIN din_b[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.096 0.024 84.120 ; + END + END din_b[35] + PIN din_b[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.144 0.024 84.168 ; + END + END din_b[36] + PIN din_b[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.192 0.024 84.216 ; + END + END din_b[37] + PIN din_b[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.240 0.024 84.264 ; + END + END din_b[38] + PIN din_b[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.288 0.024 84.312 ; + END + END din_b[39] + PIN din_b[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.336 0.024 84.360 ; + END + END din_b[40] + PIN din_b[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.384 0.024 84.408 ; + END + END din_b[41] + PIN din_b[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.432 0.024 84.456 ; + END + END din_b[42] + PIN din_b[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.480 0.024 84.504 ; + END + END din_b[43] + PIN din_b[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.528 0.024 84.552 ; + END + END din_b[44] + PIN din_b[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.576 0.024 84.600 ; + END + END din_b[45] + PIN din_b[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.624 0.024 84.648 ; + END + END din_b[46] + PIN din_b[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.672 0.024 84.696 ; + END + END din_b[47] + PIN din_b[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.720 0.024 84.744 ; + END + END din_b[48] + PIN din_b[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.768 0.024 84.792 ; + END + END din_b[49] + PIN din_b[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.816 0.024 84.840 ; + END + END din_b[50] + PIN din_b[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.864 0.024 84.888 ; + END + END din_b[51] + PIN din_b[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.912 0.024 84.936 ; + END + END din_b[52] + PIN din_b[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.960 0.024 84.984 ; + END + END din_b[53] + PIN din_b[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.008 0.024 85.032 ; + END + END din_b[54] + PIN din_b[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.056 0.024 85.080 ; + END + END din_b[55] + PIN din_b[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.104 0.024 85.128 ; + END + END din_b[56] + PIN din_b[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.152 0.024 85.176 ; + END + END din_b[57] + PIN din_b[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.200 0.024 85.224 ; + END + END din_b[58] + PIN din_b[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.248 0.024 85.272 ; + END + END din_b[59] + PIN din_b[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.296 0.024 85.320 ; + END + END din_b[60] + PIN din_b[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.344 0.024 85.368 ; + END + END din_b[61] + PIN din_b[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.392 0.024 85.416 ; + END + END din_b[62] + PIN din_b[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.440 0.024 85.464 ; + END + END din_b[63] + PIN din_b[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.488 0.024 85.512 ; + END + END din_b[64] + PIN din_b[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.536 0.024 85.560 ; + END + END din_b[65] + PIN din_b[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.584 0.024 85.608 ; + END + END din_b[66] + PIN din_b[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.632 0.024 85.656 ; + END + END din_b[67] + PIN din_b[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.680 0.024 85.704 ; + END + END din_b[68] + PIN din_b[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.728 0.024 85.752 ; + END + END din_b[69] + PIN din_b[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.776 0.024 85.800 ; + END + END din_b[70] + PIN din_b[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.824 0.024 85.848 ; + END + END din_b[71] + PIN din_b[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.872 0.024 85.896 ; + END + END din_b[72] + PIN din_b[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.920 0.024 85.944 ; + END + END din_b[73] + PIN din_b[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.968 0.024 85.992 ; + END + END din_b[74] + PIN din_b[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.016 0.024 86.040 ; + END + END din_b[75] + PIN din_b[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.064 0.024 86.088 ; + END + END din_b[76] + PIN din_b[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.112 0.024 86.136 ; + END + END din_b[77] + PIN din_b[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.160 0.024 86.184 ; + END + END din_b[78] + PIN din_b[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.208 0.024 86.232 ; + END + END din_b[79] + PIN din_b[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.256 0.024 86.280 ; + END + END din_b[80] + PIN din_b[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.304 0.024 86.328 ; + END + END din_b[81] + PIN din_b[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.352 0.024 86.376 ; + END + END din_b[82] + PIN din_b[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.400 0.024 86.424 ; + END + END din_b[83] + PIN din_b[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.448 0.024 86.472 ; + END + END din_b[84] + PIN din_b[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.496 0.024 86.520 ; + END + END din_b[85] + PIN din_b[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.544 0.024 86.568 ; + END + END din_b[86] + PIN din_b[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.592 0.024 86.616 ; + END + END din_b[87] + PIN din_b[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.640 0.024 86.664 ; + END + END din_b[88] + PIN din_b[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.688 0.024 86.712 ; + END + END din_b[89] + PIN din_b[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.736 0.024 86.760 ; + END + END din_b[90] + PIN din_b[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.784 0.024 86.808 ; + END + END din_b[91] + PIN din_b[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.832 0.024 86.856 ; + END + END din_b[92] + PIN din_b[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.880 0.024 86.904 ; + END + END din_b[93] + PIN din_b[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.928 0.024 86.952 ; + END + END din_b[94] + PIN din_b[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.976 0.024 87.000 ; + END + END din_b[95] + PIN din_b[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.024 0.024 87.048 ; + END + END din_b[96] + PIN din_b[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.072 0.024 87.096 ; + END + END din_b[97] + PIN din_b[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.120 0.024 87.144 ; + END + END din_b[98] + PIN din_b[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.168 0.024 87.192 ; + END + END din_b[99] + PIN din_b[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.216 0.024 87.240 ; + END + END din_b[100] + PIN din_b[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.264 0.024 87.288 ; + END + END din_b[101] + PIN din_b[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.312 0.024 87.336 ; + END + END din_b[102] + PIN din_b[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.360 0.024 87.384 ; + END + END din_b[103] + PIN din_b[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.408 0.024 87.432 ; + END + END din_b[104] + PIN din_b[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.456 0.024 87.480 ; + END + END din_b[105] + PIN din_b[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.504 0.024 87.528 ; + END + END din_b[106] + PIN din_b[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.552 0.024 87.576 ; + END + END din_b[107] + PIN din_b[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.600 0.024 87.624 ; + END + END din_b[108] + PIN din_b[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.648 0.024 87.672 ; + END + END din_b[109] + PIN din_b[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.696 0.024 87.720 ; + END + END din_b[110] + PIN din_b[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.744 0.024 87.768 ; + END + END din_b[111] + PIN din_b[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.792 0.024 87.816 ; + END + END din_b[112] + PIN din_b[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.840 0.024 87.864 ; + END + END din_b[113] + PIN din_b[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.888 0.024 87.912 ; + END + END din_b[114] + PIN din_b[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.936 0.024 87.960 ; + END + END din_b[115] + PIN din_b[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.984 0.024 88.008 ; + END + END din_b[116] + PIN din_b[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.032 0.024 88.056 ; + END + END din_b[117] + PIN din_b[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.080 0.024 88.104 ; + END + END din_b[118] + PIN din_b[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.128 0.024 88.152 ; + END + END din_b[119] + PIN din_b[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.176 0.024 88.200 ; + END + END din_b[120] + PIN din_b[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.224 0.024 88.248 ; + END + END din_b[121] + PIN din_b[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.272 0.024 88.296 ; + END + END din_b[122] + PIN din_b[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.320 0.024 88.344 ; + END + END din_b[123] + PIN din_b[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.368 0.024 88.392 ; + END + END din_b[124] + PIN din_b[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.416 0.024 88.440 ; + END + END din_b[125] + PIN din_b[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.464 0.024 88.488 ; + END + END din_b[126] + PIN din_b[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.512 0.024 88.536 ; + END + END din_b[127] + PIN din_b[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.560 0.024 88.584 ; + END + END din_b[128] + PIN din_b[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.608 0.024 88.632 ; + END + END din_b[129] + PIN din_b[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.656 0.024 88.680 ; + END + END din_b[130] + PIN din_b[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.704 0.024 88.728 ; + END + END din_b[131] + PIN din_b[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.752 0.024 88.776 ; + END + END din_b[132] + PIN din_b[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.800 0.024 88.824 ; + END + END din_b[133] + PIN din_b[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.848 0.024 88.872 ; + END + END din_b[134] + PIN din_b[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.896 0.024 88.920 ; + END + END din_b[135] + PIN din_b[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.944 0.024 88.968 ; + END + END din_b[136] + PIN din_b[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.992 0.024 89.016 ; + END + END din_b[137] + PIN din_b[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.040 0.024 89.064 ; + END + END din_b[138] + PIN din_b[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.088 0.024 89.112 ; + END + END din_b[139] + PIN din_b[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.136 0.024 89.160 ; + END + END din_b[140] + PIN din_b[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.184 0.024 89.208 ; + END + END din_b[141] + PIN din_b[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.232 0.024 89.256 ; + END + END din_b[142] + PIN din_b[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.280 0.024 89.304 ; + END + END din_b[143] + PIN din_b[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.328 0.024 89.352 ; + END + END din_b[144] + PIN din_b[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.376 0.024 89.400 ; + END + END din_b[145] + PIN din_b[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.424 0.024 89.448 ; + END + END din_b[146] + PIN din_b[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.472 0.024 89.496 ; + END + END din_b[147] + PIN din_b[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.520 0.024 89.544 ; + END + END din_b[148] + PIN din_b[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.568 0.024 89.592 ; + END + END din_b[149] + PIN din_b[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.616 0.024 89.640 ; + END + END din_b[150] + PIN din_b[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.664 0.024 89.688 ; + END + END din_b[151] + PIN din_b[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.712 0.024 89.736 ; + END + END din_b[152] + PIN din_b[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.760 0.024 89.784 ; + END + END din_b[153] + PIN din_b[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.808 0.024 89.832 ; + END + END din_b[154] + PIN din_b[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.856 0.024 89.880 ; + END + END din_b[155] + PIN din_b[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.904 0.024 89.928 ; + END + END din_b[156] + PIN din_b[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.952 0.024 89.976 ; + END + END din_b[157] + PIN din_b[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.000 0.024 90.024 ; + END + END din_b[158] + PIN din_b[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.048 0.024 90.072 ; + END + END din_b[159] + PIN din_b[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.096 0.024 90.120 ; + END + END din_b[160] + PIN din_b[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.144 0.024 90.168 ; + END + END din_b[161] + PIN din_b[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.192 0.024 90.216 ; + END + END din_b[162] + PIN din_b[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.240 0.024 90.264 ; + END + END din_b[163] + PIN din_b[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.288 0.024 90.312 ; + END + END din_b[164] + PIN din_b[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.336 0.024 90.360 ; + END + END din_b[165] + PIN din_b[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.384 0.024 90.408 ; + END + END din_b[166] + PIN din_b[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.432 0.024 90.456 ; + END + END din_b[167] + PIN din_b[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.480 0.024 90.504 ; + END + END din_b[168] + PIN din_b[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.528 0.024 90.552 ; + END + END din_b[169] + PIN din_b[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.576 0.024 90.600 ; + END + END din_b[170] + PIN din_b[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.624 0.024 90.648 ; + END + END din_b[171] + PIN din_b[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.672 0.024 90.696 ; + END + END din_b[172] + PIN din_b[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.720 0.024 90.744 ; + END + END din_b[173] + PIN din_b[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.768 0.024 90.792 ; + END + END din_b[174] + PIN din_b[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.816 0.024 90.840 ; + END + END din_b[175] + PIN din_b[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.864 0.024 90.888 ; + END + END din_b[176] + PIN din_b[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.912 0.024 90.936 ; + END + END din_b[177] + PIN din_b[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.960 0.024 90.984 ; + END + END din_b[178] + PIN din_b[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.008 0.024 91.032 ; + END + END din_b[179] + PIN din_b[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.056 0.024 91.080 ; + END + END din_b[180] + PIN din_b[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.104 0.024 91.128 ; + END + END din_b[181] + PIN din_b[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.152 0.024 91.176 ; + END + END din_b[182] + PIN din_b[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.200 0.024 91.224 ; + END + END din_b[183] + PIN din_b[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.248 0.024 91.272 ; + END + END din_b[184] + PIN din_b[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.296 0.024 91.320 ; + END + END din_b[185] + PIN din_b[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.344 0.024 91.368 ; + END + END din_b[186] + PIN din_b[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.392 0.024 91.416 ; + END + END din_b[187] + PIN din_b[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.440 0.024 91.464 ; + END + END din_b[188] + PIN din_b[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.488 0.024 91.512 ; + END + END din_b[189] + PIN din_b[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.536 0.024 91.560 ; + END + END din_b[190] + PIN din_b[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.584 0.024 91.608 ; + END + END din_b[191] + PIN din_b[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.632 0.024 91.656 ; + END + END din_b[192] + PIN din_b[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.680 0.024 91.704 ; + END + END din_b[193] + PIN din_b[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.728 0.024 91.752 ; + END + END din_b[194] + PIN din_b[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.776 0.024 91.800 ; + END + END din_b[195] + PIN din_b[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.824 0.024 91.848 ; + END + END din_b[196] + PIN din_b[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.872 0.024 91.896 ; + END + END din_b[197] + PIN din_b[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.920 0.024 91.944 ; + END + END din_b[198] + PIN din_b[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.968 0.024 91.992 ; + END + END din_b[199] + PIN din_b[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.016 0.024 92.040 ; + END + END din_b[200] + PIN din_b[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.064 0.024 92.088 ; + END + END din_b[201] + PIN din_b[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.112 0.024 92.136 ; + END + END din_b[202] + PIN din_b[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.160 0.024 92.184 ; + END + END din_b[203] + PIN din_b[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.208 0.024 92.232 ; + END + END din_b[204] + PIN din_b[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.256 0.024 92.280 ; + END + END din_b[205] + PIN din_b[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.304 0.024 92.328 ; + END + END din_b[206] + PIN din_b[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.352 0.024 92.376 ; + END + END din_b[207] + PIN din_b[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.400 0.024 92.424 ; + END + END din_b[208] + PIN din_b[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.448 0.024 92.472 ; + END + END din_b[209] + PIN din_b[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.496 0.024 92.520 ; + END + END din_b[210] + PIN din_b[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.544 0.024 92.568 ; + END + END din_b[211] + PIN din_b[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.592 0.024 92.616 ; + END + END din_b[212] + PIN din_b[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.640 0.024 92.664 ; + END + END din_b[213] + PIN din_b[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.688 0.024 92.712 ; + END + END din_b[214] + PIN din_b[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.736 0.024 92.760 ; + END + END din_b[215] + PIN din_b[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.784 0.024 92.808 ; + END + END din_b[216] + PIN din_b[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.832 0.024 92.856 ; + END + END din_b[217] + PIN din_b[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.880 0.024 92.904 ; + END + END din_b[218] + PIN din_b[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.928 0.024 92.952 ; + END + END din_b[219] + PIN din_b[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.976 0.024 93.000 ; + END + END din_b[220] + PIN din_b[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.024 0.024 93.048 ; + END + END din_b[221] + PIN din_b[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.072 0.024 93.096 ; + END + END din_b[222] + PIN din_b[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.120 0.024 93.144 ; + END + END din_b[223] + PIN din_b[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.168 0.024 93.192 ; + END + END din_b[224] + PIN din_b[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.216 0.024 93.240 ; + END + END din_b[225] + PIN din_b[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.264 0.024 93.288 ; + END + END din_b[226] + PIN din_b[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.312 0.024 93.336 ; + END + END din_b[227] + PIN din_b[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.360 0.024 93.384 ; + END + END din_b[228] + PIN din_b[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.408 0.024 93.432 ; + END + END din_b[229] + PIN din_b[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.456 0.024 93.480 ; + END + END din_b[230] + PIN din_b[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.504 0.024 93.528 ; + END + END din_b[231] + PIN din_b[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.552 0.024 93.576 ; + END + END din_b[232] + PIN din_b[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.600 0.024 93.624 ; + END + END din_b[233] + PIN din_b[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.648 0.024 93.672 ; + END + END din_b[234] + PIN din_b[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.696 0.024 93.720 ; + END + END din_b[235] + PIN din_b[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.744 0.024 93.768 ; + END + END din_b[236] + PIN din_b[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.792 0.024 93.816 ; + END + END din_b[237] + PIN din_b[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.840 0.024 93.864 ; + END + END din_b[238] + PIN din_b[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.888 0.024 93.912 ; + END + END din_b[239] + PIN din_b[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.936 0.024 93.960 ; + END + END din_b[240] + PIN din_b[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.984 0.024 94.008 ; + END + END din_b[241] + PIN din_b[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.032 0.024 94.056 ; + END + END din_b[242] + PIN din_b[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.080 0.024 94.104 ; + END + END din_b[243] + PIN din_b[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.128 0.024 94.152 ; + END + END din_b[244] + PIN din_b[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.176 0.024 94.200 ; + END + END din_b[245] + PIN din_b[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.224 0.024 94.248 ; + END + END din_b[246] + PIN din_b[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.272 0.024 94.296 ; + END + END din_b[247] + PIN din_b[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.320 0.024 94.344 ; + END + END din_b[248] + PIN din_b[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.368 0.024 94.392 ; + END + END din_b[249] + PIN din_b[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.416 0.024 94.440 ; + END + END din_b[250] + PIN din_b[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.464 0.024 94.488 ; + END + END din_b[251] + PIN din_b[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.512 0.024 94.536 ; + END + END din_b[252] + PIN din_b[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.560 0.024 94.584 ; + END + END din_b[253] + PIN din_b[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.608 0.024 94.632 ; + END + END din_b[254] + PIN din_b[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.656 0.024 94.680 ; + END + END din_b[255] + PIN addr_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 105.984 0.024 106.008 ; + END + END addr_b[0] + PIN addr_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.032 0.024 106.056 ; + END + END addr_b[1] + PIN addr_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.080 0.024 106.104 ; + END + END addr_b[2] + PIN addr_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.128 0.024 106.152 ; + END + END addr_b[3] + PIN addr_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.176 0.024 106.200 ; + END + END addr_b[4] + PIN addr_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.224 0.024 106.248 ; + END + END addr_b[5] + PIN addr_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.272 0.024 106.296 ; + END + END addr_b[6] + PIN addr_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.320 0.024 106.344 ; + END + END addr_b[7] + PIN we_a + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.648 0.024 117.672 ; + END + END we_a + PIN we_b + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.696 0.024 117.720 ; + END + END we_b + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.744 0.024 117.768 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 33.202 0.096 ; + RECT 0.048 0.768 33.202 0.864 ; + RECT 0.048 1.536 33.202 1.632 ; + RECT 0.048 2.304 33.202 2.400 ; + RECT 0.048 3.072 33.202 3.168 ; + RECT 0.048 3.840 33.202 3.936 ; + RECT 0.048 4.608 33.202 4.704 ; + RECT 0.048 5.376 33.202 5.472 ; + RECT 0.048 6.144 33.202 6.240 ; + RECT 0.048 6.912 33.202 7.008 ; + RECT 0.048 7.680 33.202 7.776 ; + RECT 0.048 8.448 33.202 8.544 ; + RECT 0.048 9.216 33.202 9.312 ; + RECT 0.048 9.984 33.202 10.080 ; + RECT 0.048 10.752 33.202 10.848 ; + RECT 0.048 11.520 33.202 11.616 ; + RECT 0.048 12.288 33.202 12.384 ; + RECT 0.048 13.056 33.202 13.152 ; + RECT 0.048 13.824 33.202 13.920 ; + RECT 0.048 14.592 33.202 14.688 ; + RECT 0.048 15.360 33.202 15.456 ; + RECT 0.048 16.128 33.202 16.224 ; + RECT 0.048 16.896 33.202 16.992 ; + RECT 0.048 17.664 33.202 17.760 ; + RECT 0.048 18.432 33.202 18.528 ; + RECT 0.048 19.200 33.202 19.296 ; + RECT 0.048 19.968 33.202 20.064 ; + RECT 0.048 20.736 33.202 20.832 ; + RECT 0.048 21.504 33.202 21.600 ; + RECT 0.048 22.272 33.202 22.368 ; + RECT 0.048 23.040 33.202 23.136 ; + RECT 0.048 23.808 33.202 23.904 ; + RECT 0.048 24.576 33.202 24.672 ; + RECT 0.048 25.344 33.202 25.440 ; + RECT 0.048 26.112 33.202 26.208 ; + RECT 0.048 26.880 33.202 26.976 ; + RECT 0.048 27.648 33.202 27.744 ; + RECT 0.048 28.416 33.202 28.512 ; + RECT 0.048 29.184 33.202 29.280 ; + RECT 0.048 29.952 33.202 30.048 ; + RECT 0.048 30.720 33.202 30.816 ; + RECT 0.048 31.488 33.202 31.584 ; + RECT 0.048 32.256 33.202 32.352 ; + RECT 0.048 33.024 33.202 33.120 ; + RECT 0.048 33.792 33.202 33.888 ; + RECT 0.048 34.560 33.202 34.656 ; + RECT 0.048 35.328 33.202 35.424 ; + RECT 0.048 36.096 33.202 36.192 ; + RECT 0.048 36.864 33.202 36.960 ; + RECT 0.048 37.632 33.202 37.728 ; + RECT 0.048 38.400 33.202 38.496 ; + RECT 0.048 39.168 33.202 39.264 ; + RECT 0.048 39.936 33.202 40.032 ; + RECT 0.048 40.704 33.202 40.800 ; + RECT 0.048 41.472 33.202 41.568 ; + RECT 0.048 42.240 33.202 42.336 ; + RECT 0.048 43.008 33.202 43.104 ; + RECT 0.048 43.776 33.202 43.872 ; + RECT 0.048 44.544 33.202 44.640 ; + RECT 0.048 45.312 33.202 45.408 ; + RECT 0.048 46.080 33.202 46.176 ; + RECT 0.048 46.848 33.202 46.944 ; + RECT 0.048 47.616 33.202 47.712 ; + RECT 0.048 48.384 33.202 48.480 ; + RECT 0.048 49.152 33.202 49.248 ; + RECT 0.048 49.920 33.202 50.016 ; + RECT 0.048 50.688 33.202 50.784 ; + RECT 0.048 51.456 33.202 51.552 ; + RECT 0.048 52.224 33.202 52.320 ; + RECT 0.048 52.992 33.202 53.088 ; + RECT 0.048 53.760 33.202 53.856 ; + RECT 0.048 54.528 33.202 54.624 ; + RECT 0.048 55.296 33.202 55.392 ; + RECT 0.048 56.064 33.202 56.160 ; + RECT 0.048 56.832 33.202 56.928 ; + RECT 0.048 57.600 33.202 57.696 ; + RECT 0.048 58.368 33.202 58.464 ; + RECT 0.048 59.136 33.202 59.232 ; + RECT 0.048 59.904 33.202 60.000 ; + RECT 0.048 60.672 33.202 60.768 ; + RECT 0.048 61.440 33.202 61.536 ; + RECT 0.048 62.208 33.202 62.304 ; + RECT 0.048 62.976 33.202 63.072 ; + RECT 0.048 63.744 33.202 63.840 ; + RECT 0.048 64.512 33.202 64.608 ; + RECT 0.048 65.280 33.202 65.376 ; + RECT 0.048 66.048 33.202 66.144 ; + RECT 0.048 66.816 33.202 66.912 ; + RECT 0.048 67.584 33.202 67.680 ; + RECT 0.048 68.352 33.202 68.448 ; + RECT 0.048 69.120 33.202 69.216 ; + RECT 0.048 69.888 33.202 69.984 ; + RECT 0.048 70.656 33.202 70.752 ; + RECT 0.048 71.424 33.202 71.520 ; + RECT 0.048 72.192 33.202 72.288 ; + RECT 0.048 72.960 33.202 73.056 ; + RECT 0.048 73.728 33.202 73.824 ; + RECT 0.048 74.496 33.202 74.592 ; + RECT 0.048 75.264 33.202 75.360 ; + RECT 0.048 76.032 33.202 76.128 ; + RECT 0.048 76.800 33.202 76.896 ; + RECT 0.048 77.568 33.202 77.664 ; + RECT 0.048 78.336 33.202 78.432 ; + RECT 0.048 79.104 33.202 79.200 ; + RECT 0.048 79.872 33.202 79.968 ; + RECT 0.048 80.640 33.202 80.736 ; + RECT 0.048 81.408 33.202 81.504 ; + RECT 0.048 82.176 33.202 82.272 ; + RECT 0.048 82.944 33.202 83.040 ; + RECT 0.048 83.712 33.202 83.808 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 33.202 0.480 ; + RECT 0.048 1.152 33.202 1.248 ; + RECT 0.048 1.920 33.202 2.016 ; + RECT 0.048 2.688 33.202 2.784 ; + RECT 0.048 3.456 33.202 3.552 ; + RECT 0.048 4.224 33.202 4.320 ; + RECT 0.048 4.992 33.202 5.088 ; + RECT 0.048 5.760 33.202 5.856 ; + RECT 0.048 6.528 33.202 6.624 ; + RECT 0.048 7.296 33.202 7.392 ; + RECT 0.048 8.064 33.202 8.160 ; + RECT 0.048 8.832 33.202 8.928 ; + RECT 0.048 9.600 33.202 9.696 ; + RECT 0.048 10.368 33.202 10.464 ; + RECT 0.048 11.136 33.202 11.232 ; + RECT 0.048 11.904 33.202 12.000 ; + RECT 0.048 12.672 33.202 12.768 ; + RECT 0.048 13.440 33.202 13.536 ; + RECT 0.048 14.208 33.202 14.304 ; + RECT 0.048 14.976 33.202 15.072 ; + RECT 0.048 15.744 33.202 15.840 ; + RECT 0.048 16.512 33.202 16.608 ; + RECT 0.048 17.280 33.202 17.376 ; + RECT 0.048 18.048 33.202 18.144 ; + RECT 0.048 18.816 33.202 18.912 ; + RECT 0.048 19.584 33.202 19.680 ; + RECT 0.048 20.352 33.202 20.448 ; + RECT 0.048 21.120 33.202 21.216 ; + RECT 0.048 21.888 33.202 21.984 ; + RECT 0.048 22.656 33.202 22.752 ; + RECT 0.048 23.424 33.202 23.520 ; + RECT 0.048 24.192 33.202 24.288 ; + RECT 0.048 24.960 33.202 25.056 ; + RECT 0.048 25.728 33.202 25.824 ; + RECT 0.048 26.496 33.202 26.592 ; + RECT 0.048 27.264 33.202 27.360 ; + RECT 0.048 28.032 33.202 28.128 ; + RECT 0.048 28.800 33.202 28.896 ; + RECT 0.048 29.568 33.202 29.664 ; + RECT 0.048 30.336 33.202 30.432 ; + RECT 0.048 31.104 33.202 31.200 ; + RECT 0.048 31.872 33.202 31.968 ; + RECT 0.048 32.640 33.202 32.736 ; + RECT 0.048 33.408 33.202 33.504 ; + RECT 0.048 34.176 33.202 34.272 ; + RECT 0.048 34.944 33.202 35.040 ; + RECT 0.048 35.712 33.202 35.808 ; + RECT 0.048 36.480 33.202 36.576 ; + RECT 0.048 37.248 33.202 37.344 ; + RECT 0.048 38.016 33.202 38.112 ; + RECT 0.048 38.784 33.202 38.880 ; + RECT 0.048 39.552 33.202 39.648 ; + RECT 0.048 40.320 33.202 40.416 ; + RECT 0.048 41.088 33.202 41.184 ; + RECT 0.048 41.856 33.202 41.952 ; + RECT 0.048 42.624 33.202 42.720 ; + RECT 0.048 43.392 33.202 43.488 ; + RECT 0.048 44.160 33.202 44.256 ; + RECT 0.048 44.928 33.202 45.024 ; + RECT 0.048 45.696 33.202 45.792 ; + RECT 0.048 46.464 33.202 46.560 ; + RECT 0.048 47.232 33.202 47.328 ; + RECT 0.048 48.000 33.202 48.096 ; + RECT 0.048 48.768 33.202 48.864 ; + RECT 0.048 49.536 33.202 49.632 ; + RECT 0.048 50.304 33.202 50.400 ; + RECT 0.048 51.072 33.202 51.168 ; + RECT 0.048 51.840 33.202 51.936 ; + RECT 0.048 52.608 33.202 52.704 ; + RECT 0.048 53.376 33.202 53.472 ; + RECT 0.048 54.144 33.202 54.240 ; + RECT 0.048 54.912 33.202 55.008 ; + RECT 0.048 55.680 33.202 55.776 ; + RECT 0.048 56.448 33.202 56.544 ; + RECT 0.048 57.216 33.202 57.312 ; + RECT 0.048 57.984 33.202 58.080 ; + RECT 0.048 58.752 33.202 58.848 ; + RECT 0.048 59.520 33.202 59.616 ; + RECT 0.048 60.288 33.202 60.384 ; + RECT 0.048 61.056 33.202 61.152 ; + RECT 0.048 61.824 33.202 61.920 ; + RECT 0.048 62.592 33.202 62.688 ; + RECT 0.048 63.360 33.202 63.456 ; + RECT 0.048 64.128 33.202 64.224 ; + RECT 0.048 64.896 33.202 64.992 ; + RECT 0.048 65.664 33.202 65.760 ; + RECT 0.048 66.432 33.202 66.528 ; + RECT 0.048 67.200 33.202 67.296 ; + RECT 0.048 67.968 33.202 68.064 ; + RECT 0.048 68.736 33.202 68.832 ; + RECT 0.048 69.504 33.202 69.600 ; + RECT 0.048 70.272 33.202 70.368 ; + RECT 0.048 71.040 33.202 71.136 ; + RECT 0.048 71.808 33.202 71.904 ; + RECT 0.048 72.576 33.202 72.672 ; + RECT 0.048 73.344 33.202 73.440 ; + RECT 0.048 74.112 33.202 74.208 ; + RECT 0.048 74.880 33.202 74.976 ; + RECT 0.048 75.648 33.202 75.744 ; + RECT 0.048 76.416 33.202 76.512 ; + RECT 0.048 77.184 33.202 77.280 ; + RECT 0.048 77.952 33.202 78.048 ; + RECT 0.048 78.720 33.202 78.816 ; + RECT 0.048 79.488 33.202 79.584 ; + RECT 0.048 80.256 33.202 80.352 ; + RECT 0.048 81.024 33.202 81.120 ; + RECT 0.048 81.792 33.202 81.888 ; + RECT 0.048 82.560 33.202 82.656 ; + RECT 0.048 83.328 33.202 83.424 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 84.000 ; + LAYER M2 ; + RECT 0 0 33.250 84.000 ; + LAYER M3 ; + RECT 0 0 33.250 84.000 ; + LAYER M4 ; + RECT 0 0 33.250 84.000 ; + END +END dprf_256x256 + +END LIBRARY +module dprf_256x256 +( + we_a, + addr_a, + din_a, + dout_a, + we_b, + addr_b, + din_b, + dout_b, + clk, +); + parameter DATA_WIDTH = 256; + parameter ADDR_WIDTH = 8; + + // Port A + input wire we_a, + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] din_a, + output reg [DATA_WIDTH-1:0] dout_a, + + // Port B + input wire we_b, + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] din_b, + output reg [DATA_WIDTH-1:0] dout_b, + + input wire clk, + + // Memory array: 256 words of 256 bits + reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1]; + + // Synchronous Port A + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= din_a; + end + dout_a <= mem[addr_a]; // Read occurs after write (read-after-write OK) + end + + // Synchronous Port B + always @(posedge clk) begin + if (we_b) begin + mem[addr_b] <= din_b; + end + dout_b <= mem[addr_b]; // Read occurs after write (read-after-write OK) + end + +endmodule +(* blackbox *) +module dprf_256x256 ( + input we_a, + input [7:0] addr_a, + input [255:0] din_a, + output reg [255:0] dout_a, + input we_b, + input [7:0] addr_b, + input [255:0] din_b, + output reg [255:0] dout_b, + clk, +); +endmodule +library(dprf_256x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(dprf_256x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(dprf_256x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(dprf_256x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(dprf_256x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(dprf_256x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (dprf_256x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (dprf_256x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(dprf_256x256) { + area : 2751.883; + interface_timing : true; + pin(we_a){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_a) { + bus_type : dprf_256x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_a) { + bus_type : dprf_256x256_DATA; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_a) { + bus_type : dprf_256x256_DATA; + direction : output; + max_capacitance : 0.500; + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(dprf_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(dprf_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(dprf_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(dprf_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_b){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_b) { + bus_type : dprf_256x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_b) { + bus_type : dprf_256x256_DATA; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_b) { + bus_type : dprf_256x256_DATA; + direction : output; + max_capacitance : 0.500; + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(dprf_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(dprf_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(dprf_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(dprf_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(dprf_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(dprf_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + cell_leakage_power : 128.900; +} + +} diff --git a/test/au/dprf_256x32.au b/test/au/dprf_256x32.au new file mode 100644 index 0000000..b5a4bc1 --- /dev/null +++ b/test/au/dprf_256x32.au @@ -0,0 +1,2070 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO dprf_256x32 + PROPERTY width 32 ; + PROPERTY depth 256 ; + PROPERTY banks 2 ; + FOREIGN dprf_256x32 0 0 ; + SYMMETRY X Y R90 ; + SIZE 8.360 BY 42.000 ; + CLASS BLOCK ; + PIN dout_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END dout_a[0] + PIN dout_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.024 0.312 ; + END + END dout_a[1] + PIN dout_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.024 0.552 ; + END + END dout_a[2] + PIN dout_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END dout_a[3] + PIN dout_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.024 1.032 ; + END + END dout_a[4] + PIN dout_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.024 1.272 ; + END + END dout_a[5] + PIN dout_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END dout_a[6] + PIN dout_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.728 0.024 1.752 ; + END + END dout_a[7] + PIN dout_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.024 1.992 ; + END + END dout_a[8] + PIN dout_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END dout_a[9] + PIN dout_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.024 2.472 ; + END + END dout_a[10] + PIN dout_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END dout_a[11] + PIN dout_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END dout_a[12] + PIN dout_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.024 3.192 ; + END + END dout_a[13] + PIN dout_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.024 3.432 ; + END + END dout_a[14] + PIN dout_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END dout_a[15] + PIN dout_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.888 0.024 3.912 ; + END + END dout_a[16] + PIN dout_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.024 4.152 ; + END + END dout_a[17] + PIN dout_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END dout_a[18] + PIN dout_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.024 4.632 ; + END + END dout_a[19] + PIN dout_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.848 0.024 4.872 ; + END + END dout_a[20] + PIN dout_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END dout_a[21] + PIN dout_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END dout_a[22] + PIN dout_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.024 5.592 ; + END + END dout_a[23] + PIN dout_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END dout_a[24] + PIN dout_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.048 0.024 6.072 ; + END + END dout_a[25] + PIN dout_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.288 0.024 6.312 ; + END + END dout_a[26] + PIN dout_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END dout_a[27] + PIN dout_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.768 0.024 6.792 ; + END + END dout_a[28] + PIN dout_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.008 0.024 7.032 ; + END + END dout_a[29] + PIN dout_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END dout_a[30] + PIN dout_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.488 0.024 7.512 ; + END + END dout_a[31] + PIN din_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.024 9.960 ; + END + END din_a[0] + PIN din_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.176 0.024 10.200 ; + END + END din_a[1] + PIN din_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END din_a[2] + PIN din_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.024 10.680 ; + END + END din_a[3] + PIN din_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.896 0.024 10.920 ; + END + END din_a[4] + PIN din_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END din_a[5] + PIN din_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.024 11.400 ; + END + END din_a[6] + PIN din_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.616 0.024 11.640 ; + END + END din_a[7] + PIN din_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END din_a[8] + PIN din_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.024 12.120 ; + END + END din_a[9] + PIN din_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.336 0.024 12.360 ; + END + END din_a[10] + PIN din_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.576 0.024 12.600 ; + END + END din_a[11] + PIN din_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.816 0.024 12.840 ; + END + END din_a[12] + PIN din_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.056 0.024 13.080 ; + END + END din_a[13] + PIN din_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.296 0.024 13.320 ; + END + END din_a[14] + PIN din_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.536 0.024 13.560 ; + END + END din_a[15] + PIN din_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.776 0.024 13.800 ; + END + END din_a[16] + PIN din_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.016 0.024 14.040 ; + END + END din_a[17] + PIN din_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.256 0.024 14.280 ; + END + END din_a[18] + PIN din_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.496 0.024 14.520 ; + END + END din_a[19] + PIN din_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.736 0.024 14.760 ; + END + END din_a[20] + PIN din_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.976 0.024 15.000 ; + END + END din_a[21] + PIN din_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.216 0.024 15.240 ; + END + END din_a[22] + PIN din_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.456 0.024 15.480 ; + END + END din_a[23] + PIN din_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.696 0.024 15.720 ; + END + END din_a[24] + PIN din_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.936 0.024 15.960 ; + END + END din_a[25] + PIN din_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.176 0.024 16.200 ; + END + END din_a[26] + PIN din_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.416 0.024 16.440 ; + END + END din_a[27] + PIN din_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.656 0.024 16.680 ; + END + END din_a[28] + PIN din_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.896 0.024 16.920 ; + END + END din_a[29] + PIN din_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.136 0.024 17.160 ; + END + END din_a[30] + PIN din_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.376 0.024 17.400 ; + END + END din_a[31] + PIN addr_a[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.024 19.848 ; + END + END addr_a[0] + PIN addr_a[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.024 20.088 ; + END + END addr_a[1] + PIN addr_a[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.304 0.024 20.328 ; + END + END addr_a[2] + PIN addr_a[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.544 0.024 20.568 ; + END + END addr_a[3] + PIN addr_a[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.024 20.808 ; + END + END addr_a[4] + PIN addr_a[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.024 0.024 21.048 ; + END + END addr_a[5] + PIN addr_a[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.264 0.024 21.288 ; + END + END addr_a[6] + PIN addr_a[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.024 21.528 ; + END + END addr_a[7] + PIN dout_b[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.024 23.976 ; + END + END dout_b[0] + PIN dout_b[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.024 24.216 ; + END + END dout_b[1] + PIN dout_b[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.432 0.024 24.456 ; + END + END dout_b[2] + PIN dout_b[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.024 24.696 ; + END + END dout_b[3] + PIN dout_b[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.912 0.024 24.936 ; + END + END dout_b[4] + PIN dout_b[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.152 0.024 25.176 ; + END + END dout_b[5] + PIN dout_b[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END dout_b[6] + PIN dout_b[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.024 25.656 ; + END + END dout_b[7] + PIN dout_b[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.872 0.024 25.896 ; + END + END dout_b[8] + PIN dout_b[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.024 26.136 ; + END + END dout_b[9] + PIN dout_b[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.352 0.024 26.376 ; + END + END dout_b[10] + PIN dout_b[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.592 0.024 26.616 ; + END + END dout_b[11] + PIN dout_b[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END dout_b[12] + PIN dout_b[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.072 0.024 27.096 ; + END + END dout_b[13] + PIN dout_b[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.312 0.024 27.336 ; + END + END dout_b[14] + PIN dout_b[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.024 27.576 ; + END + END dout_b[15] + PIN dout_b[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.792 0.024 27.816 ; + END + END dout_b[16] + PIN dout_b[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.032 0.024 28.056 ; + END + END dout_b[17] + PIN dout_b[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END dout_b[18] + PIN dout_b[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.512 0.024 28.536 ; + END + END dout_b[19] + PIN dout_b[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.752 0.024 28.776 ; + END + END dout_b[20] + PIN dout_b[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.024 29.016 ; + END + END dout_b[21] + PIN dout_b[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.232 0.024 29.256 ; + END + END dout_b[22] + PIN dout_b[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.472 0.024 29.496 ; + END + END dout_b[23] + PIN dout_b[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.024 29.736 ; + END + END dout_b[24] + PIN dout_b[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.952 0.024 29.976 ; + END + END dout_b[25] + PIN dout_b[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.192 0.024 30.216 ; + END + END dout_b[26] + PIN dout_b[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.024 30.456 ; + END + END dout_b[27] + PIN dout_b[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.672 0.024 30.696 ; + END + END dout_b[28] + PIN dout_b[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.912 0.024 30.936 ; + END + END dout_b[29] + PIN dout_b[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END dout_b[30] + PIN dout_b[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.392 0.024 31.416 ; + END + END dout_b[31] + PIN din_b[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.840 0.024 33.864 ; + END + END din_b[0] + PIN din_b[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.080 0.024 34.104 ; + END + END din_b[1] + PIN din_b[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.320 0.024 34.344 ; + END + END din_b[2] + PIN din_b[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.560 0.024 34.584 ; + END + END din_b[3] + PIN din_b[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.800 0.024 34.824 ; + END + END din_b[4] + PIN din_b[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.040 0.024 35.064 ; + END + END din_b[5] + PIN din_b[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.280 0.024 35.304 ; + END + END din_b[6] + PIN din_b[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.520 0.024 35.544 ; + END + END din_b[7] + PIN din_b[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END din_b[8] + PIN din_b[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.000 0.024 36.024 ; + END + END din_b[9] + PIN din_b[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.240 0.024 36.264 ; + END + END din_b[10] + PIN din_b[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.480 0.024 36.504 ; + END + END din_b[11] + PIN din_b[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.720 0.024 36.744 ; + END + END din_b[12] + PIN din_b[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.960 0.024 36.984 ; + END + END din_b[13] + PIN din_b[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.200 0.024 37.224 ; + END + END din_b[14] + PIN din_b[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.440 0.024 37.464 ; + END + END din_b[15] + PIN din_b[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.680 0.024 37.704 ; + END + END din_b[16] + PIN din_b[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.920 0.024 37.944 ; + END + END din_b[17] + PIN din_b[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.160 0.024 38.184 ; + END + END din_b[18] + PIN din_b[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.400 0.024 38.424 ; + END + END din_b[19] + PIN din_b[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.640 0.024 38.664 ; + END + END din_b[20] + PIN din_b[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.880 0.024 38.904 ; + END + END din_b[21] + PIN din_b[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.120 0.024 39.144 ; + END + END din_b[22] + PIN din_b[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.360 0.024 39.384 ; + END + END din_b[23] + PIN din_b[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.600 0.024 39.624 ; + END + END din_b[24] + PIN din_b[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.840 0.024 39.864 ; + END + END din_b[25] + PIN din_b[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.080 0.024 40.104 ; + END + END din_b[26] + PIN din_b[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.320 0.024 40.344 ; + END + END din_b[27] + PIN din_b[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.560 0.024 40.584 ; + END + END din_b[28] + PIN din_b[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.800 0.024 40.824 ; + END + END din_b[29] + PIN din_b[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.040 0.024 41.064 ; + END + END din_b[30] + PIN din_b[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.280 0.024 41.304 ; + END + END din_b[31] + PIN addr_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.728 0.024 43.752 ; + END + END addr_b[0] + PIN addr_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.968 0.024 43.992 ; + END + END addr_b[1] + PIN addr_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.208 0.024 44.232 ; + END + END addr_b[2] + PIN addr_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.448 0.024 44.472 ; + END + END addr_b[3] + PIN addr_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.688 0.024 44.712 ; + END + END addr_b[4] + PIN addr_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.928 0.024 44.952 ; + END + END addr_b[5] + PIN addr_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.168 0.024 45.192 ; + END + END addr_b[6] + PIN addr_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.408 0.024 45.432 ; + END + END addr_b[7] + PIN we_a + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.856 0.024 47.880 ; + END + END we_a + PIN we_b + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.096 0.024 48.120 ; + END + END we_b + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.336 0.024 48.360 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 8.312 0.096 ; + RECT 0.048 0.768 8.312 0.864 ; + RECT 0.048 1.536 8.312 1.632 ; + RECT 0.048 2.304 8.312 2.400 ; + RECT 0.048 3.072 8.312 3.168 ; + RECT 0.048 3.840 8.312 3.936 ; + RECT 0.048 4.608 8.312 4.704 ; + RECT 0.048 5.376 8.312 5.472 ; + RECT 0.048 6.144 8.312 6.240 ; + RECT 0.048 6.912 8.312 7.008 ; + RECT 0.048 7.680 8.312 7.776 ; + RECT 0.048 8.448 8.312 8.544 ; + RECT 0.048 9.216 8.312 9.312 ; + RECT 0.048 9.984 8.312 10.080 ; + RECT 0.048 10.752 8.312 10.848 ; + RECT 0.048 11.520 8.312 11.616 ; + RECT 0.048 12.288 8.312 12.384 ; + RECT 0.048 13.056 8.312 13.152 ; + RECT 0.048 13.824 8.312 13.920 ; + RECT 0.048 14.592 8.312 14.688 ; + RECT 0.048 15.360 8.312 15.456 ; + RECT 0.048 16.128 8.312 16.224 ; + RECT 0.048 16.896 8.312 16.992 ; + RECT 0.048 17.664 8.312 17.760 ; + RECT 0.048 18.432 8.312 18.528 ; + RECT 0.048 19.200 8.312 19.296 ; + RECT 0.048 19.968 8.312 20.064 ; + RECT 0.048 20.736 8.312 20.832 ; + RECT 0.048 21.504 8.312 21.600 ; + RECT 0.048 22.272 8.312 22.368 ; + RECT 0.048 23.040 8.312 23.136 ; + RECT 0.048 23.808 8.312 23.904 ; + RECT 0.048 24.576 8.312 24.672 ; + RECT 0.048 25.344 8.312 25.440 ; + RECT 0.048 26.112 8.312 26.208 ; + RECT 0.048 26.880 8.312 26.976 ; + RECT 0.048 27.648 8.312 27.744 ; + RECT 0.048 28.416 8.312 28.512 ; + RECT 0.048 29.184 8.312 29.280 ; + RECT 0.048 29.952 8.312 30.048 ; + RECT 0.048 30.720 8.312 30.816 ; + RECT 0.048 31.488 8.312 31.584 ; + RECT 0.048 32.256 8.312 32.352 ; + RECT 0.048 33.024 8.312 33.120 ; + RECT 0.048 33.792 8.312 33.888 ; + RECT 0.048 34.560 8.312 34.656 ; + RECT 0.048 35.328 8.312 35.424 ; + RECT 0.048 36.096 8.312 36.192 ; + RECT 0.048 36.864 8.312 36.960 ; + RECT 0.048 37.632 8.312 37.728 ; + RECT 0.048 38.400 8.312 38.496 ; + RECT 0.048 39.168 8.312 39.264 ; + RECT 0.048 39.936 8.312 40.032 ; + RECT 0.048 40.704 8.312 40.800 ; + RECT 0.048 41.472 8.312 41.568 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 8.312 0.480 ; + RECT 0.048 1.152 8.312 1.248 ; + RECT 0.048 1.920 8.312 2.016 ; + RECT 0.048 2.688 8.312 2.784 ; + RECT 0.048 3.456 8.312 3.552 ; + RECT 0.048 4.224 8.312 4.320 ; + RECT 0.048 4.992 8.312 5.088 ; + RECT 0.048 5.760 8.312 5.856 ; + RECT 0.048 6.528 8.312 6.624 ; + RECT 0.048 7.296 8.312 7.392 ; + RECT 0.048 8.064 8.312 8.160 ; + RECT 0.048 8.832 8.312 8.928 ; + RECT 0.048 9.600 8.312 9.696 ; + RECT 0.048 10.368 8.312 10.464 ; + RECT 0.048 11.136 8.312 11.232 ; + RECT 0.048 11.904 8.312 12.000 ; + RECT 0.048 12.672 8.312 12.768 ; + RECT 0.048 13.440 8.312 13.536 ; + RECT 0.048 14.208 8.312 14.304 ; + RECT 0.048 14.976 8.312 15.072 ; + RECT 0.048 15.744 8.312 15.840 ; + RECT 0.048 16.512 8.312 16.608 ; + RECT 0.048 17.280 8.312 17.376 ; + RECT 0.048 18.048 8.312 18.144 ; + RECT 0.048 18.816 8.312 18.912 ; + RECT 0.048 19.584 8.312 19.680 ; + RECT 0.048 20.352 8.312 20.448 ; + RECT 0.048 21.120 8.312 21.216 ; + RECT 0.048 21.888 8.312 21.984 ; + RECT 0.048 22.656 8.312 22.752 ; + RECT 0.048 23.424 8.312 23.520 ; + RECT 0.048 24.192 8.312 24.288 ; + RECT 0.048 24.960 8.312 25.056 ; + RECT 0.048 25.728 8.312 25.824 ; + RECT 0.048 26.496 8.312 26.592 ; + RECT 0.048 27.264 8.312 27.360 ; + RECT 0.048 28.032 8.312 28.128 ; + RECT 0.048 28.800 8.312 28.896 ; + RECT 0.048 29.568 8.312 29.664 ; + RECT 0.048 30.336 8.312 30.432 ; + RECT 0.048 31.104 8.312 31.200 ; + RECT 0.048 31.872 8.312 31.968 ; + RECT 0.048 32.640 8.312 32.736 ; + RECT 0.048 33.408 8.312 33.504 ; + RECT 0.048 34.176 8.312 34.272 ; + RECT 0.048 34.944 8.312 35.040 ; + RECT 0.048 35.712 8.312 35.808 ; + RECT 0.048 36.480 8.312 36.576 ; + RECT 0.048 37.248 8.312 37.344 ; + RECT 0.048 38.016 8.312 38.112 ; + RECT 0.048 38.784 8.312 38.880 ; + RECT 0.048 39.552 8.312 39.648 ; + RECT 0.048 40.320 8.312 40.416 ; + RECT 0.048 41.088 8.312 41.184 ; + RECT 0.048 41.856 8.312 41.952 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 8.360 42.000 ; + LAYER M2 ; + RECT 0 0 8.360 42.000 ; + LAYER M3 ; + RECT 0 0 8.360 42.000 ; + LAYER M4 ; + RECT 0 0 8.360 42.000 ; + END +END dprf_256x32 + +END LIBRARY +module dprf_256x32 +( + we_a, + addr_a, + din_a, + dout_a, + we_b, + addr_b, + din_b, + dout_b, + clk, +); + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 8; + + // Port A + input wire we_a, + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] din_a, + output reg [DATA_WIDTH-1:0] dout_a, + + // Port B + input wire we_b, + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] din_b, + output reg [DATA_WIDTH-1:0] dout_b, + + input wire clk, + + // Memory array: 256 words of 32 bits + reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1]; + + // Synchronous Port A + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= din_a; + end + dout_a <= mem[addr_a]; // Read occurs after write (read-after-write OK) + end + + // Synchronous Port B + always @(posedge clk) begin + if (we_b) begin + mem[addr_b] <= din_b; + end + dout_b <= mem[addr_b]; // Read occurs after write (read-after-write OK) + end + +endmodule +(* blackbox *) +module dprf_256x32 ( + input we_a, + input [7:0] addr_a, + input [31:0] din_a, + output reg [31:0] dout_a, + input we_b, + input [7:0] addr_b, + input [31:0] din_b, + output reg [31:0] dout_b, + clk, +); +endmodule +library(dprf_256x32) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(dprf_256x32_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(dprf_256x32_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(dprf_256x32_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(dprf_256x32_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(dprf_256x32_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (dprf_256x32_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 32; + bit_from : 31; + bit_to : 0 ; + downto : true ; + } + type (dprf_256x32_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(dprf_256x32) { + area : 343.985; + interface_timing : true; + pin(we_a){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_a) { + bus_type : dprf_256x32_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_a) { + bus_type : dprf_256x32_DATA; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_a) { + bus_type : dprf_256x32_DATA; + direction : output; + max_capacitance : 0.500; + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(dprf_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(dprf_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(dprf_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(dprf_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_b){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_b) { + bus_type : dprf_256x32_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_b) { + bus_type : dprf_256x32_DATA; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_b) { + bus_type : dprf_256x32_DATA; + direction : output; + max_capacitance : 0.500; + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(dprf_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(dprf_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(dprf_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(dprf_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(dprf_256x32_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(dprf_256x32_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + cell_leakage_power : 128.900; +} + +} diff --git a/test/au/dpsram_256x256.au b/test/au/dpsram_256x256.au new file mode 100644 index 0000000..4278c3e --- /dev/null +++ b/test/au/dpsram_256x256.au @@ -0,0 +1,10275 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO dpsram_256x256 + PROPERTY width 256 ; + PROPERTY depth 256 ; + PROPERTY banks 1 ; + FOREIGN dpsram_256x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 84.000 ; + CLASS BLOCK ; + PIN dout_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END dout_a[0] + PIN dout_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.096 0.024 0.120 ; + END + END dout_a[1] + PIN dout_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.024 0.168 ; + END + END dout_a[2] + PIN dout_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END dout_a[3] + PIN dout_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.024 0.264 ; + END + END dout_a[4] + PIN dout_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.024 0.312 ; + END + END dout_a[5] + PIN dout_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END dout_a[6] + PIN dout_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.384 0.024 0.408 ; + END + END dout_a[7] + PIN dout_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.024 0.456 ; + END + END dout_a[8] + PIN dout_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END dout_a[9] + PIN dout_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.024 0.552 ; + END + END dout_a[10] + PIN dout_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.024 0.600 ; + END + END dout_a[11] + PIN dout_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END dout_a[12] + PIN dout_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.672 0.024 0.696 ; + END + END dout_a[13] + PIN dout_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.024 0.744 ; + END + END dout_a[14] + PIN dout_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END dout_a[15] + PIN dout_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.024 0.840 ; + END + END dout_a[16] + PIN dout_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.864 0.024 0.888 ; + END + END dout_a[17] + PIN dout_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END dout_a[18] + PIN dout_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.960 0.024 0.984 ; + END + END dout_a[19] + PIN dout_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.024 1.032 ; + END + END dout_a[20] + PIN dout_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END dout_a[21] + PIN dout_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.024 1.128 ; + END + END dout_a[22] + PIN dout_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.152 0.024 1.176 ; + END + END dout_a[23] + PIN dout_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END dout_a[24] + PIN dout_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.024 1.272 ; + END + END dout_a[25] + PIN dout_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.024 1.320 ; + END + END dout_a[26] + PIN dout_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END dout_a[27] + PIN dout_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.024 1.416 ; + END + END dout_a[28] + PIN dout_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.440 0.024 1.464 ; + END + END dout_a[29] + PIN dout_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END dout_a[30] + PIN dout_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.536 0.024 1.560 ; + END + END dout_a[31] + PIN dout_a[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.024 1.608 ; + END + END dout_a[32] + PIN dout_a[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END dout_a[33] + PIN dout_a[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.024 1.704 ; + END + END dout_a[34] + PIN dout_a[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.728 0.024 1.752 ; + END + END dout_a[35] + PIN dout_a[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END dout_a[36] + PIN dout_a[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.824 0.024 1.848 ; + END + END dout_a[37] + PIN dout_a[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.024 1.896 ; + END + END dout_a[38] + PIN dout_a[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END dout_a[39] + PIN dout_a[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.024 1.992 ; + END + END dout_a[40] + PIN dout_a[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.016 0.024 2.040 ; + END + END dout_a[41] + PIN dout_a[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END dout_a[42] + PIN dout_a[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.112 0.024 2.136 ; + END + END dout_a[43] + PIN dout_a[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.024 2.184 ; + END + END dout_a[44] + PIN dout_a[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END dout_a[45] + PIN dout_a[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.024 2.280 ; + END + END dout_a[46] + PIN dout_a[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.304 0.024 2.328 ; + END + END dout_a[47] + PIN dout_a[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END dout_a[48] + PIN dout_a[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.400 0.024 2.424 ; + END + END dout_a[49] + PIN dout_a[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.024 2.472 ; + END + END dout_a[50] + PIN dout_a[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END dout_a[51] + PIN dout_a[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.024 2.568 ; + END + END dout_a[52] + PIN dout_a[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.024 2.616 ; + END + END dout_a[53] + PIN dout_a[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END dout_a[54] + PIN dout_a[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END dout_a[55] + PIN dout_a[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.024 2.760 ; + END + END dout_a[56] + PIN dout_a[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END dout_a[57] + PIN dout_a[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.024 2.856 ; + END + END dout_a[58] + PIN dout_a[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.024 2.904 ; + END + END dout_a[59] + PIN dout_a[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END dout_a[60] + PIN dout_a[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.024 3.000 ; + END + END dout_a[61] + PIN dout_a[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.024 3.048 ; + END + END dout_a[62] + PIN dout_a[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END dout_a[63] + PIN dout_a[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.024 3.144 ; + END + END dout_a[64] + PIN dout_a[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.024 3.192 ; + END + END dout_a[65] + PIN dout_a[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END dout_a[66] + PIN dout_a[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.024 3.288 ; + END + END dout_a[67] + PIN dout_a[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.024 3.336 ; + END + END dout_a[68] + PIN dout_a[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END dout_a[69] + PIN dout_a[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.024 3.432 ; + END + END dout_a[70] + PIN dout_a[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.024 3.480 ; + END + END dout_a[71] + PIN dout_a[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END dout_a[72] + PIN dout_a[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.024 3.576 ; + END + END dout_a[73] + PIN dout_a[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.024 3.624 ; + END + END dout_a[74] + PIN dout_a[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END dout_a[75] + PIN dout_a[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.696 0.024 3.720 ; + END + END dout_a[76] + PIN dout_a[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.024 3.768 ; + END + END dout_a[77] + PIN dout_a[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END dout_a[78] + PIN dout_a[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.840 0.024 3.864 ; + END + END dout_a[79] + PIN dout_a[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.888 0.024 3.912 ; + END + END dout_a[80] + PIN dout_a[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END dout_a[81] + PIN dout_a[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.984 0.024 4.008 ; + END + END dout_a[82] + PIN dout_a[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.032 0.024 4.056 ; + END + END dout_a[83] + PIN dout_a[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END dout_a[84] + PIN dout_a[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.024 4.152 ; + END + END dout_a[85] + PIN dout_a[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.176 0.024 4.200 ; + END + END dout_a[86] + PIN dout_a[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END dout_a[87] + PIN dout_a[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.272 0.024 4.296 ; + END + END dout_a[88] + PIN dout_a[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.320 0.024 4.344 ; + END + END dout_a[89] + PIN dout_a[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END dout_a[90] + PIN dout_a[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.416 0.024 4.440 ; + END + END dout_a[91] + PIN dout_a[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.464 0.024 4.488 ; + END + END dout_a[92] + PIN dout_a[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END dout_a[93] + PIN dout_a[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.024 4.584 ; + END + END dout_a[94] + PIN dout_a[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.024 4.632 ; + END + END dout_a[95] + PIN dout_a[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END dout_a[96] + PIN dout_a[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.024 4.728 ; + END + END dout_a[97] + PIN dout_a[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.024 4.776 ; + END + END dout_a[98] + PIN dout_a[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END dout_a[99] + PIN dout_a[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.848 0.024 4.872 ; + END + END dout_a[100] + PIN dout_a[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.896 0.024 4.920 ; + END + END dout_a[101] + PIN dout_a[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END dout_a[102] + PIN dout_a[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.992 0.024 5.016 ; + END + END dout_a[103] + PIN dout_a[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.024 5.064 ; + END + END dout_a[104] + PIN dout_a[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END dout_a[105] + PIN dout_a[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.024 5.160 ; + END + END dout_a[106] + PIN dout_a[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.184 0.024 5.208 ; + END + END dout_a[107] + PIN dout_a[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END dout_a[108] + PIN dout_a[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.280 0.024 5.304 ; + END + END dout_a[109] + PIN dout_a[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END dout_a[110] + PIN dout_a[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END dout_a[111] + PIN dout_a[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.024 5.448 ; + END + END dout_a[112] + PIN dout_a[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.472 0.024 5.496 ; + END + END dout_a[113] + PIN dout_a[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END dout_a[114] + PIN dout_a[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.024 5.592 ; + END + END dout_a[115] + PIN dout_a[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.616 0.024 5.640 ; + END + END dout_a[116] + PIN dout_a[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END dout_a[117] + PIN dout_a[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.712 0.024 5.736 ; + END + END dout_a[118] + PIN dout_a[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.024 5.784 ; + END + END dout_a[119] + PIN dout_a[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END dout_a[120] + PIN dout_a[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.024 5.880 ; + END + END dout_a[121] + PIN dout_a[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.904 0.024 5.928 ; + END + END dout_a[122] + PIN dout_a[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END dout_a[123] + PIN dout_a[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.000 0.024 6.024 ; + END + END dout_a[124] + PIN dout_a[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.048 0.024 6.072 ; + END + END dout_a[125] + PIN dout_a[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END dout_a[126] + PIN dout_a[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.144 0.024 6.168 ; + END + END dout_a[127] + PIN dout_a[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.192 0.024 6.216 ; + END + END dout_a[128] + PIN dout_a[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END dout_a[129] + PIN dout_a[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.288 0.024 6.312 ; + END + END dout_a[130] + PIN dout_a[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.336 0.024 6.360 ; + END + END dout_a[131] + PIN dout_a[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END dout_a[132] + PIN dout_a[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.432 0.024 6.456 ; + END + END dout_a[133] + PIN dout_a[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.480 0.024 6.504 ; + END + END dout_a[134] + PIN dout_a[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END dout_a[135] + PIN dout_a[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.576 0.024 6.600 ; + END + END dout_a[136] + PIN dout_a[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.624 0.024 6.648 ; + END + END dout_a[137] + PIN dout_a[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END dout_a[138] + PIN dout_a[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.720 0.024 6.744 ; + END + END dout_a[139] + PIN dout_a[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.768 0.024 6.792 ; + END + END dout_a[140] + PIN dout_a[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END dout_a[141] + PIN dout_a[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.864 0.024 6.888 ; + END + END dout_a[142] + PIN dout_a[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.912 0.024 6.936 ; + END + END dout_a[143] + PIN dout_a[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END dout_a[144] + PIN dout_a[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.008 0.024 7.032 ; + END + END dout_a[145] + PIN dout_a[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.056 0.024 7.080 ; + END + END dout_a[146] + PIN dout_a[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END dout_a[147] + PIN dout_a[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.152 0.024 7.176 ; + END + END dout_a[148] + PIN dout_a[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.200 0.024 7.224 ; + END + END dout_a[149] + PIN dout_a[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END dout_a[150] + PIN dout_a[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.296 0.024 7.320 ; + END + END dout_a[151] + PIN dout_a[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.344 0.024 7.368 ; + END + END dout_a[152] + PIN dout_a[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END dout_a[153] + PIN dout_a[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.440 0.024 7.464 ; + END + END dout_a[154] + PIN dout_a[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.488 0.024 7.512 ; + END + END dout_a[155] + PIN dout_a[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END dout_a[156] + PIN dout_a[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.584 0.024 7.608 ; + END + END dout_a[157] + PIN dout_a[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.632 0.024 7.656 ; + END + END dout_a[158] + PIN dout_a[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END dout_a[159] + PIN dout_a[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.728 0.024 7.752 ; + END + END dout_a[160] + PIN dout_a[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.776 0.024 7.800 ; + END + END dout_a[161] + PIN dout_a[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END dout_a[162] + PIN dout_a[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.872 0.024 7.896 ; + END + END dout_a[163] + PIN dout_a[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.920 0.024 7.944 ; + END + END dout_a[164] + PIN dout_a[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END dout_a[165] + PIN dout_a[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.016 0.024 8.040 ; + END + END dout_a[166] + PIN dout_a[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.064 0.024 8.088 ; + END + END dout_a[167] + PIN dout_a[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END dout_a[168] + PIN dout_a[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.160 0.024 8.184 ; + END + END dout_a[169] + PIN dout_a[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.208 0.024 8.232 ; + END + END dout_a[170] + PIN dout_a[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END dout_a[171] + PIN dout_a[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.304 0.024 8.328 ; + END + END dout_a[172] + PIN dout_a[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.352 0.024 8.376 ; + END + END dout_a[173] + PIN dout_a[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END dout_a[174] + PIN dout_a[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.448 0.024 8.472 ; + END + END dout_a[175] + PIN dout_a[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.496 0.024 8.520 ; + END + END dout_a[176] + PIN dout_a[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END dout_a[177] + PIN dout_a[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.592 0.024 8.616 ; + END + END dout_a[178] + PIN dout_a[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.640 0.024 8.664 ; + END + END dout_a[179] + PIN dout_a[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END dout_a[180] + PIN dout_a[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.736 0.024 8.760 ; + END + END dout_a[181] + PIN dout_a[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.784 0.024 8.808 ; + END + END dout_a[182] + PIN dout_a[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END dout_a[183] + PIN dout_a[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.880 0.024 8.904 ; + END + END dout_a[184] + PIN dout_a[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.928 0.024 8.952 ; + END + END dout_a[185] + PIN dout_a[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END dout_a[186] + PIN dout_a[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.024 0.024 9.048 ; + END + END dout_a[187] + PIN dout_a[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.072 0.024 9.096 ; + END + END dout_a[188] + PIN dout_a[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END dout_a[189] + PIN dout_a[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.168 0.024 9.192 ; + END + END dout_a[190] + PIN dout_a[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.216 0.024 9.240 ; + END + END dout_a[191] + PIN dout_a[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.024 9.288 ; + END + END dout_a[192] + PIN dout_a[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.312 0.024 9.336 ; + END + END dout_a[193] + PIN dout_a[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.360 0.024 9.384 ; + END + END dout_a[194] + PIN dout_a[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.024 9.432 ; + END + END dout_a[195] + PIN dout_a[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.456 0.024 9.480 ; + END + END dout_a[196] + PIN dout_a[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.504 0.024 9.528 ; + END + END dout_a[197] + PIN dout_a[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END dout_a[198] + PIN dout_a[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.600 0.024 9.624 ; + END + END dout_a[199] + PIN dout_a[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.648 0.024 9.672 ; + END + END dout_a[200] + PIN dout_a[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.024 9.720 ; + END + END dout_a[201] + PIN dout_a[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.744 0.024 9.768 ; + END + END dout_a[202] + PIN dout_a[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.024 9.816 ; + END + END dout_a[203] + PIN dout_a[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.024 9.864 ; + END + END dout_a[204] + PIN dout_a[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.888 0.024 9.912 ; + END + END dout_a[205] + PIN dout_a[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.024 9.960 ; + END + END dout_a[206] + PIN dout_a[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.024 10.008 ; + END + END dout_a[207] + PIN dout_a[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.032 0.024 10.056 ; + END + END dout_a[208] + PIN dout_a[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.024 10.104 ; + END + END dout_a[209] + PIN dout_a[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.024 10.152 ; + END + END dout_a[210] + PIN dout_a[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.176 0.024 10.200 ; + END + END dout_a[211] + PIN dout_a[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.224 0.024 10.248 ; + END + END dout_a[212] + PIN dout_a[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.024 10.296 ; + END + END dout_a[213] + PIN dout_a[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.320 0.024 10.344 ; + END + END dout_a[214] + PIN dout_a[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.024 10.392 ; + END + END dout_a[215] + PIN dout_a[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END dout_a[216] + PIN dout_a[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.464 0.024 10.488 ; + END + END dout_a[217] + PIN dout_a[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.512 0.024 10.536 ; + END + END dout_a[218] + PIN dout_a[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.024 10.584 ; + END + END dout_a[219] + PIN dout_a[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.608 0.024 10.632 ; + END + END dout_a[220] + PIN dout_a[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.024 10.680 ; + END + END dout_a[221] + PIN dout_a[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.024 10.728 ; + END + END dout_a[222] + PIN dout_a[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.752 0.024 10.776 ; + END + END dout_a[223] + PIN dout_a[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.800 0.024 10.824 ; + END + END dout_a[224] + PIN dout_a[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.024 10.872 ; + END + END dout_a[225] + PIN dout_a[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.896 0.024 10.920 ; + END + END dout_a[226] + PIN dout_a[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.024 10.968 ; + END + END dout_a[227] + PIN dout_a[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.024 11.016 ; + END + END dout_a[228] + PIN dout_a[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.040 0.024 11.064 ; + END + END dout_a[229] + PIN dout_a[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.088 0.024 11.112 ; + END + END dout_a[230] + PIN dout_a[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END dout_a[231] + PIN dout_a[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.184 0.024 11.208 ; + END + END dout_a[232] + PIN dout_a[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.024 11.256 ; + END + END dout_a[233] + PIN dout_a[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.024 11.304 ; + END + END dout_a[234] + PIN dout_a[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.328 0.024 11.352 ; + END + END dout_a[235] + PIN dout_a[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.024 11.400 ; + END + END dout_a[236] + PIN dout_a[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.024 11.448 ; + END + END dout_a[237] + PIN dout_a[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.472 0.024 11.496 ; + END + END dout_a[238] + PIN dout_a[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.024 11.544 ; + END + END dout_a[239] + PIN dout_a[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.024 11.592 ; + END + END dout_a[240] + PIN dout_a[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.616 0.024 11.640 ; + END + END dout_a[241] + PIN dout_a[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.024 11.688 ; + END + END dout_a[242] + PIN dout_a[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.024 11.736 ; + END + END dout_a[243] + PIN dout_a[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.760 0.024 11.784 ; + END + END dout_a[244] + PIN dout_a[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.024 11.832 ; + END + END dout_a[245] + PIN dout_a[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END dout_a[246] + PIN dout_a[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.904 0.024 11.928 ; + END + END dout_a[247] + PIN dout_a[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.952 0.024 11.976 ; + END + END dout_a[248] + PIN dout_a[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.024 12.024 ; + END + END dout_a[249] + PIN dout_a[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.048 0.024 12.072 ; + END + END dout_a[250] + PIN dout_a[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.024 12.120 ; + END + END dout_a[251] + PIN dout_a[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.024 12.168 ; + END + END dout_a[252] + PIN dout_a[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.192 0.024 12.216 ; + END + END dout_a[253] + PIN dout_a[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.240 0.024 12.264 ; + END + END dout_a[254] + PIN dout_a[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.024 12.312 ; + END + END dout_a[255] + PIN din_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.616 0.024 23.640 ; + END + END din_a[0] + PIN din_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.024 23.688 ; + END + END din_a[1] + PIN din_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.712 0.024 23.736 ; + END + END din_a[2] + PIN din_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.760 0.024 23.784 ; + END + END din_a[3] + PIN din_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.024 23.832 ; + END + END din_a[4] + PIN din_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.856 0.024 23.880 ; + END + END din_a[5] + PIN din_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.904 0.024 23.928 ; + END + END din_a[6] + PIN din_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.024 23.976 ; + END + END din_a[7] + PIN din_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.000 0.024 24.024 ; + END + END din_a[8] + PIN din_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.048 0.024 24.072 ; + END + END din_a[9] + PIN din_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.024 24.120 ; + END + END din_a[10] + PIN din_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.144 0.024 24.168 ; + END + END din_a[11] + PIN din_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.024 24.216 ; + END + END din_a[12] + PIN din_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.024 24.264 ; + END + END din_a[13] + PIN din_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.288 0.024 24.312 ; + END + END din_a[14] + PIN din_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.336 0.024 24.360 ; + END + END din_a[15] + PIN din_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.024 24.408 ; + END + END din_a[16] + PIN din_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.432 0.024 24.456 ; + END + END din_a[17] + PIN din_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.480 0.024 24.504 ; + END + END din_a[18] + PIN din_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.024 24.552 ; + END + END din_a[19] + PIN din_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.576 0.024 24.600 ; + END + END din_a[20] + PIN din_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.624 0.024 24.648 ; + END + END din_a[21] + PIN din_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.024 24.696 ; + END + END din_a[22] + PIN din_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.720 0.024 24.744 ; + END + END din_a[23] + PIN din_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.768 0.024 24.792 ; + END + END din_a[24] + PIN din_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.024 24.840 ; + END + END din_a[25] + PIN din_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.864 0.024 24.888 ; + END + END din_a[26] + PIN din_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.912 0.024 24.936 ; + END + END din_a[27] + PIN din_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.024 24.984 ; + END + END din_a[28] + PIN din_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.008 0.024 25.032 ; + END + END din_a[29] + PIN din_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.056 0.024 25.080 ; + END + END din_a[30] + PIN din_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.024 25.128 ; + END + END din_a[31] + PIN din_a[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.152 0.024 25.176 ; + END + END din_a[32] + PIN din_a[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.200 0.024 25.224 ; + END + END din_a[33] + PIN din_a[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.024 25.272 ; + END + END din_a[34] + PIN din_a[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.296 0.024 25.320 ; + END + END din_a[35] + PIN din_a[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.344 0.024 25.368 ; + END + END din_a[36] + PIN din_a[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END din_a[37] + PIN din_a[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.440 0.024 25.464 ; + END + END din_a[38] + PIN din_a[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.488 0.024 25.512 ; + END + END din_a[39] + PIN din_a[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.024 25.560 ; + END + END din_a[40] + PIN din_a[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.584 0.024 25.608 ; + END + END din_a[41] + PIN din_a[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.024 25.656 ; + END + END din_a[42] + PIN din_a[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.024 25.704 ; + END + END din_a[43] + PIN din_a[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.728 0.024 25.752 ; + END + END din_a[44] + PIN din_a[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.776 0.024 25.800 ; + END + END din_a[45] + PIN din_a[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.024 25.848 ; + END + END din_a[46] + PIN din_a[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.872 0.024 25.896 ; + END + END din_a[47] + PIN din_a[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.920 0.024 25.944 ; + END + END din_a[48] + PIN din_a[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.024 25.992 ; + END + END din_a[49] + PIN din_a[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.016 0.024 26.040 ; + END + END din_a[50] + PIN din_a[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.064 0.024 26.088 ; + END + END din_a[51] + PIN din_a[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.024 26.136 ; + END + END din_a[52] + PIN din_a[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.160 0.024 26.184 ; + END + END din_a[53] + PIN din_a[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.208 0.024 26.232 ; + END + END din_a[54] + PIN din_a[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.024 26.280 ; + END + END din_a[55] + PIN din_a[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.304 0.024 26.328 ; + END + END din_a[56] + PIN din_a[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.352 0.024 26.376 ; + END + END din_a[57] + PIN din_a[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.024 26.424 ; + END + END din_a[58] + PIN din_a[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.448 0.024 26.472 ; + END + END din_a[59] + PIN din_a[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.496 0.024 26.520 ; + END + END din_a[60] + PIN din_a[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.024 26.568 ; + END + END din_a[61] + PIN din_a[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.592 0.024 26.616 ; + END + END din_a[62] + PIN din_a[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.640 0.024 26.664 ; + END + END din_a[63] + PIN din_a[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.024 26.712 ; + END + END din_a[64] + PIN din_a[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.736 0.024 26.760 ; + END + END din_a[65] + PIN din_a[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.784 0.024 26.808 ; + END + END din_a[66] + PIN din_a[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END din_a[67] + PIN din_a[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.880 0.024 26.904 ; + END + END din_a[68] + PIN din_a[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.928 0.024 26.952 ; + END + END din_a[69] + PIN din_a[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.024 27.000 ; + END + END din_a[70] + PIN din_a[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.024 0.024 27.048 ; + END + END din_a[71] + PIN din_a[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.072 0.024 27.096 ; + END + END din_a[72] + PIN din_a[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.024 27.144 ; + END + END din_a[73] + PIN din_a[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.168 0.024 27.192 ; + END + END din_a[74] + PIN din_a[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.216 0.024 27.240 ; + END + END din_a[75] + PIN din_a[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.024 27.288 ; + END + END din_a[76] + PIN din_a[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.312 0.024 27.336 ; + END + END din_a[77] + PIN din_a[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.360 0.024 27.384 ; + END + END din_a[78] + PIN din_a[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.024 27.432 ; + END + END din_a[79] + PIN din_a[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.456 0.024 27.480 ; + END + END din_a[80] + PIN din_a[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.504 0.024 27.528 ; + END + END din_a[81] + PIN din_a[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.024 27.576 ; + END + END din_a[82] + PIN din_a[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.600 0.024 27.624 ; + END + END din_a[83] + PIN din_a[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.648 0.024 27.672 ; + END + END din_a[84] + PIN din_a[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.024 27.720 ; + END + END din_a[85] + PIN din_a[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.744 0.024 27.768 ; + END + END din_a[86] + PIN din_a[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.792 0.024 27.816 ; + END + END din_a[87] + PIN din_a[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.024 27.864 ; + END + END din_a[88] + PIN din_a[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.888 0.024 27.912 ; + END + END din_a[89] + PIN din_a[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.936 0.024 27.960 ; + END + END din_a[90] + PIN din_a[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.024 28.008 ; + END + END din_a[91] + PIN din_a[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.032 0.024 28.056 ; + END + END din_a[92] + PIN din_a[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.080 0.024 28.104 ; + END + END din_a[93] + PIN din_a[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.024 28.152 ; + END + END din_a[94] + PIN din_a[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.176 0.024 28.200 ; + END + END din_a[95] + PIN din_a[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.224 0.024 28.248 ; + END + END din_a[96] + PIN din_a[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END din_a[97] + PIN din_a[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.320 0.024 28.344 ; + END + END din_a[98] + PIN din_a[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.368 0.024 28.392 ; + END + END din_a[99] + PIN din_a[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.024 28.440 ; + END + END din_a[100] + PIN din_a[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.464 0.024 28.488 ; + END + END din_a[101] + PIN din_a[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.512 0.024 28.536 ; + END + END din_a[102] + PIN din_a[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.024 28.584 ; + END + END din_a[103] + PIN din_a[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.608 0.024 28.632 ; + END + END din_a[104] + PIN din_a[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.656 0.024 28.680 ; + END + END din_a[105] + PIN din_a[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.024 28.728 ; + END + END din_a[106] + PIN din_a[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.752 0.024 28.776 ; + END + END din_a[107] + PIN din_a[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.800 0.024 28.824 ; + END + END din_a[108] + PIN din_a[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.024 28.872 ; + END + END din_a[109] + PIN din_a[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.896 0.024 28.920 ; + END + END din_a[110] + PIN din_a[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.944 0.024 28.968 ; + END + END din_a[111] + PIN din_a[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.024 29.016 ; + END + END din_a[112] + PIN din_a[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.040 0.024 29.064 ; + END + END din_a[113] + PIN din_a[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.088 0.024 29.112 ; + END + END din_a[114] + PIN din_a[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.024 29.160 ; + END + END din_a[115] + PIN din_a[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.184 0.024 29.208 ; + END + END din_a[116] + PIN din_a[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.232 0.024 29.256 ; + END + END din_a[117] + PIN din_a[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.024 29.304 ; + END + END din_a[118] + PIN din_a[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.328 0.024 29.352 ; + END + END din_a[119] + PIN din_a[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.376 0.024 29.400 ; + END + END din_a[120] + PIN din_a[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.024 29.448 ; + END + END din_a[121] + PIN din_a[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.472 0.024 29.496 ; + END + END din_a[122] + PIN din_a[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.520 0.024 29.544 ; + END + END din_a[123] + PIN din_a[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.024 29.592 ; + END + END din_a[124] + PIN din_a[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.616 0.024 29.640 ; + END + END din_a[125] + PIN din_a[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.664 0.024 29.688 ; + END + END din_a[126] + PIN din_a[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.024 29.736 ; + END + END din_a[127] + PIN din_a[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.760 0.024 29.784 ; + END + END din_a[128] + PIN din_a[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.808 0.024 29.832 ; + END + END din_a[129] + PIN din_a[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.024 29.880 ; + END + END din_a[130] + PIN din_a[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.904 0.024 29.928 ; + END + END din_a[131] + PIN din_a[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.952 0.024 29.976 ; + END + END din_a[132] + PIN din_a[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.024 30.024 ; + END + END din_a[133] + PIN din_a[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.048 0.024 30.072 ; + END + END din_a[134] + PIN din_a[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.096 0.024 30.120 ; + END + END din_a[135] + PIN din_a[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.024 30.168 ; + END + END din_a[136] + PIN din_a[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.192 0.024 30.216 ; + END + END din_a[137] + PIN din_a[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.240 0.024 30.264 ; + END + END din_a[138] + PIN din_a[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.024 30.312 ; + END + END din_a[139] + PIN din_a[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.336 0.024 30.360 ; + END + END din_a[140] + PIN din_a[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.384 0.024 30.408 ; + END + END din_a[141] + PIN din_a[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.024 30.456 ; + END + END din_a[142] + PIN din_a[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.480 0.024 30.504 ; + END + END din_a[143] + PIN din_a[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.528 0.024 30.552 ; + END + END din_a[144] + PIN din_a[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.024 30.600 ; + END + END din_a[145] + PIN din_a[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.624 0.024 30.648 ; + END + END din_a[146] + PIN din_a[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.672 0.024 30.696 ; + END + END din_a[147] + PIN din_a[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.024 30.744 ; + END + END din_a[148] + PIN din_a[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.768 0.024 30.792 ; + END + END din_a[149] + PIN din_a[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.816 0.024 30.840 ; + END + END din_a[150] + PIN din_a[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.024 30.888 ; + END + END din_a[151] + PIN din_a[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.912 0.024 30.936 ; + END + END din_a[152] + PIN din_a[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.960 0.024 30.984 ; + END + END din_a[153] + PIN din_a[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.024 31.032 ; + END + END din_a[154] + PIN din_a[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.056 0.024 31.080 ; + END + END din_a[155] + PIN din_a[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.104 0.024 31.128 ; + END + END din_a[156] + PIN din_a[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END din_a[157] + PIN din_a[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.200 0.024 31.224 ; + END + END din_a[158] + PIN din_a[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.248 0.024 31.272 ; + END + END din_a[159] + PIN din_a[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.024 31.320 ; + END + END din_a[160] + PIN din_a[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.344 0.024 31.368 ; + END + END din_a[161] + PIN din_a[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.392 0.024 31.416 ; + END + END din_a[162] + PIN din_a[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.024 31.464 ; + END + END din_a[163] + PIN din_a[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.488 0.024 31.512 ; + END + END din_a[164] + PIN din_a[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.536 0.024 31.560 ; + END + END din_a[165] + PIN din_a[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.024 31.608 ; + END + END din_a[166] + PIN din_a[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.632 0.024 31.656 ; + END + END din_a[167] + PIN din_a[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.680 0.024 31.704 ; + END + END din_a[168] + PIN din_a[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.024 31.752 ; + END + END din_a[169] + PIN din_a[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.776 0.024 31.800 ; + END + END din_a[170] + PIN din_a[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.824 0.024 31.848 ; + END + END din_a[171] + PIN din_a[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.872 0.024 31.896 ; + END + END din_a[172] + PIN din_a[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.920 0.024 31.944 ; + END + END din_a[173] + PIN din_a[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.968 0.024 31.992 ; + END + END din_a[174] + PIN din_a[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.016 0.024 32.040 ; + END + END din_a[175] + PIN din_a[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.064 0.024 32.088 ; + END + END din_a[176] + PIN din_a[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.112 0.024 32.136 ; + END + END din_a[177] + PIN din_a[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.160 0.024 32.184 ; + END + END din_a[178] + PIN din_a[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.208 0.024 32.232 ; + END + END din_a[179] + PIN din_a[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.256 0.024 32.280 ; + END + END din_a[180] + PIN din_a[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.304 0.024 32.328 ; + END + END din_a[181] + PIN din_a[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.352 0.024 32.376 ; + END + END din_a[182] + PIN din_a[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.400 0.024 32.424 ; + END + END din_a[183] + PIN din_a[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.448 0.024 32.472 ; + END + END din_a[184] + PIN din_a[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.496 0.024 32.520 ; + END + END din_a[185] + PIN din_a[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.544 0.024 32.568 ; + END + END din_a[186] + PIN din_a[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.592 0.024 32.616 ; + END + END din_a[187] + PIN din_a[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.640 0.024 32.664 ; + END + END din_a[188] + PIN din_a[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.688 0.024 32.712 ; + END + END din_a[189] + PIN din_a[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.736 0.024 32.760 ; + END + END din_a[190] + PIN din_a[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.784 0.024 32.808 ; + END + END din_a[191] + PIN din_a[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.832 0.024 32.856 ; + END + END din_a[192] + PIN din_a[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.880 0.024 32.904 ; + END + END din_a[193] + PIN din_a[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.928 0.024 32.952 ; + END + END din_a[194] + PIN din_a[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.976 0.024 33.000 ; + END + END din_a[195] + PIN din_a[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.024 0.024 33.048 ; + END + END din_a[196] + PIN din_a[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.072 0.024 33.096 ; + END + END din_a[197] + PIN din_a[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.120 0.024 33.144 ; + END + END din_a[198] + PIN din_a[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.168 0.024 33.192 ; + END + END din_a[199] + PIN din_a[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.216 0.024 33.240 ; + END + END din_a[200] + PIN din_a[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.264 0.024 33.288 ; + END + END din_a[201] + PIN din_a[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.312 0.024 33.336 ; + END + END din_a[202] + PIN din_a[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.360 0.024 33.384 ; + END + END din_a[203] + PIN din_a[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.408 0.024 33.432 ; + END + END din_a[204] + PIN din_a[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.456 0.024 33.480 ; + END + END din_a[205] + PIN din_a[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.504 0.024 33.528 ; + END + END din_a[206] + PIN din_a[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.552 0.024 33.576 ; + END + END din_a[207] + PIN din_a[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.600 0.024 33.624 ; + END + END din_a[208] + PIN din_a[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.648 0.024 33.672 ; + END + END din_a[209] + PIN din_a[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.696 0.024 33.720 ; + END + END din_a[210] + PIN din_a[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.744 0.024 33.768 ; + END + END din_a[211] + PIN din_a[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.792 0.024 33.816 ; + END + END din_a[212] + PIN din_a[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.840 0.024 33.864 ; + END + END din_a[213] + PIN din_a[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.888 0.024 33.912 ; + END + END din_a[214] + PIN din_a[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.936 0.024 33.960 ; + END + END din_a[215] + PIN din_a[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.984 0.024 34.008 ; + END + END din_a[216] + PIN din_a[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.032 0.024 34.056 ; + END + END din_a[217] + PIN din_a[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.080 0.024 34.104 ; + END + END din_a[218] + PIN din_a[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.128 0.024 34.152 ; + END + END din_a[219] + PIN din_a[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.176 0.024 34.200 ; + END + END din_a[220] + PIN din_a[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.224 0.024 34.248 ; + END + END din_a[221] + PIN din_a[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.272 0.024 34.296 ; + END + END din_a[222] + PIN din_a[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.320 0.024 34.344 ; + END + END din_a[223] + PIN din_a[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.368 0.024 34.392 ; + END + END din_a[224] + PIN din_a[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.416 0.024 34.440 ; + END + END din_a[225] + PIN din_a[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.464 0.024 34.488 ; + END + END din_a[226] + PIN din_a[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.512 0.024 34.536 ; + END + END din_a[227] + PIN din_a[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.560 0.024 34.584 ; + END + END din_a[228] + PIN din_a[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.608 0.024 34.632 ; + END + END din_a[229] + PIN din_a[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.656 0.024 34.680 ; + END + END din_a[230] + PIN din_a[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.704 0.024 34.728 ; + END + END din_a[231] + PIN din_a[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.752 0.024 34.776 ; + END + END din_a[232] + PIN din_a[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.800 0.024 34.824 ; + END + END din_a[233] + PIN din_a[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.848 0.024 34.872 ; + END + END din_a[234] + PIN din_a[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.896 0.024 34.920 ; + END + END din_a[235] + PIN din_a[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.944 0.024 34.968 ; + END + END din_a[236] + PIN din_a[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.992 0.024 35.016 ; + END + END din_a[237] + PIN din_a[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.040 0.024 35.064 ; + END + END din_a[238] + PIN din_a[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.088 0.024 35.112 ; + END + END din_a[239] + PIN din_a[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.136 0.024 35.160 ; + END + END din_a[240] + PIN din_a[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.184 0.024 35.208 ; + END + END din_a[241] + PIN din_a[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.232 0.024 35.256 ; + END + END din_a[242] + PIN din_a[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.280 0.024 35.304 ; + END + END din_a[243] + PIN din_a[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.328 0.024 35.352 ; + END + END din_a[244] + PIN din_a[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.376 0.024 35.400 ; + END + END din_a[245] + PIN din_a[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.424 0.024 35.448 ; + END + END din_a[246] + PIN din_a[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.472 0.024 35.496 ; + END + END din_a[247] + PIN din_a[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.520 0.024 35.544 ; + END + END din_a[248] + PIN din_a[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.568 0.024 35.592 ; + END + END din_a[249] + PIN din_a[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.616 0.024 35.640 ; + END + END din_a[250] + PIN din_a[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.664 0.024 35.688 ; + END + END din_a[251] + PIN din_a[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.712 0.024 35.736 ; + END + END din_a[252] + PIN din_a[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END din_a[253] + PIN din_a[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.808 0.024 35.832 ; + END + END din_a[254] + PIN din_a[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.856 0.024 35.880 ; + END + END din_a[255] + PIN addr_a[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.184 0.024 47.208 ; + END + END addr_a[0] + PIN addr_a[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.232 0.024 47.256 ; + END + END addr_a[1] + PIN addr_a[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.280 0.024 47.304 ; + END + END addr_a[2] + PIN addr_a[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.328 0.024 47.352 ; + END + END addr_a[3] + PIN addr_a[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.376 0.024 47.400 ; + END + END addr_a[4] + PIN addr_a[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.424 0.024 47.448 ; + END + END addr_a[5] + PIN addr_a[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.472 0.024 47.496 ; + END + END addr_a[6] + PIN addr_a[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.520 0.024 47.544 ; + END + END addr_a[7] + PIN dout_b[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.848 0.024 58.872 ; + END + END dout_b[0] + PIN dout_b[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.896 0.024 58.920 ; + END + END dout_b[1] + PIN dout_b[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.944 0.024 58.968 ; + END + END dout_b[2] + PIN dout_b[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.992 0.024 59.016 ; + END + END dout_b[3] + PIN dout_b[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.040 0.024 59.064 ; + END + END dout_b[4] + PIN dout_b[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.088 0.024 59.112 ; + END + END dout_b[5] + PIN dout_b[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.136 0.024 59.160 ; + END + END dout_b[6] + PIN dout_b[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.184 0.024 59.208 ; + END + END dout_b[7] + PIN dout_b[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.232 0.024 59.256 ; + END + END dout_b[8] + PIN dout_b[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.280 0.024 59.304 ; + END + END dout_b[9] + PIN dout_b[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.328 0.024 59.352 ; + END + END dout_b[10] + PIN dout_b[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.376 0.024 59.400 ; + END + END dout_b[11] + PIN dout_b[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.424 0.024 59.448 ; + END + END dout_b[12] + PIN dout_b[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.472 0.024 59.496 ; + END + END dout_b[13] + PIN dout_b[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.520 0.024 59.544 ; + END + END dout_b[14] + PIN dout_b[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.568 0.024 59.592 ; + END + END dout_b[15] + PIN dout_b[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.616 0.024 59.640 ; + END + END dout_b[16] + PIN dout_b[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.664 0.024 59.688 ; + END + END dout_b[17] + PIN dout_b[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.712 0.024 59.736 ; + END + END dout_b[18] + PIN dout_b[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.760 0.024 59.784 ; + END + END dout_b[19] + PIN dout_b[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.808 0.024 59.832 ; + END + END dout_b[20] + PIN dout_b[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.856 0.024 59.880 ; + END + END dout_b[21] + PIN dout_b[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.904 0.024 59.928 ; + END + END dout_b[22] + PIN dout_b[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.952 0.024 59.976 ; + END + END dout_b[23] + PIN dout_b[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.000 0.024 60.024 ; + END + END dout_b[24] + PIN dout_b[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.048 0.024 60.072 ; + END + END dout_b[25] + PIN dout_b[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.096 0.024 60.120 ; + END + END dout_b[26] + PIN dout_b[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.144 0.024 60.168 ; + END + END dout_b[27] + PIN dout_b[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.192 0.024 60.216 ; + END + END dout_b[28] + PIN dout_b[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.240 0.024 60.264 ; + END + END dout_b[29] + PIN dout_b[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.288 0.024 60.312 ; + END + END dout_b[30] + PIN dout_b[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.336 0.024 60.360 ; + END + END dout_b[31] + PIN dout_b[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.384 0.024 60.408 ; + END + END dout_b[32] + PIN dout_b[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.432 0.024 60.456 ; + END + END dout_b[33] + PIN dout_b[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.480 0.024 60.504 ; + END + END dout_b[34] + PIN dout_b[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.528 0.024 60.552 ; + END + END dout_b[35] + PIN dout_b[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.576 0.024 60.600 ; + END + END dout_b[36] + PIN dout_b[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.624 0.024 60.648 ; + END + END dout_b[37] + PIN dout_b[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.672 0.024 60.696 ; + END + END dout_b[38] + PIN dout_b[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.720 0.024 60.744 ; + END + END dout_b[39] + PIN dout_b[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.768 0.024 60.792 ; + END + END dout_b[40] + PIN dout_b[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.816 0.024 60.840 ; + END + END dout_b[41] + PIN dout_b[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.864 0.024 60.888 ; + END + END dout_b[42] + PIN dout_b[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.912 0.024 60.936 ; + END + END dout_b[43] + PIN dout_b[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.960 0.024 60.984 ; + END + END dout_b[44] + PIN dout_b[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.008 0.024 61.032 ; + END + END dout_b[45] + PIN dout_b[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.056 0.024 61.080 ; + END + END dout_b[46] + PIN dout_b[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.104 0.024 61.128 ; + END + END dout_b[47] + PIN dout_b[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.152 0.024 61.176 ; + END + END dout_b[48] + PIN dout_b[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.200 0.024 61.224 ; + END + END dout_b[49] + PIN dout_b[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.248 0.024 61.272 ; + END + END dout_b[50] + PIN dout_b[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.296 0.024 61.320 ; + END + END dout_b[51] + PIN dout_b[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.344 0.024 61.368 ; + END + END dout_b[52] + PIN dout_b[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.392 0.024 61.416 ; + END + END dout_b[53] + PIN dout_b[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.440 0.024 61.464 ; + END + END dout_b[54] + PIN dout_b[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.488 0.024 61.512 ; + END + END dout_b[55] + PIN dout_b[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.536 0.024 61.560 ; + END + END dout_b[56] + PIN dout_b[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.584 0.024 61.608 ; + END + END dout_b[57] + PIN dout_b[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.632 0.024 61.656 ; + END + END dout_b[58] + PIN dout_b[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.680 0.024 61.704 ; + END + END dout_b[59] + PIN dout_b[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.728 0.024 61.752 ; + END + END dout_b[60] + PIN dout_b[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.776 0.024 61.800 ; + END + END dout_b[61] + PIN dout_b[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.824 0.024 61.848 ; + END + END dout_b[62] + PIN dout_b[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.872 0.024 61.896 ; + END + END dout_b[63] + PIN dout_b[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.920 0.024 61.944 ; + END + END dout_b[64] + PIN dout_b[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.968 0.024 61.992 ; + END + END dout_b[65] + PIN dout_b[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.016 0.024 62.040 ; + END + END dout_b[66] + PIN dout_b[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.064 0.024 62.088 ; + END + END dout_b[67] + PIN dout_b[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.112 0.024 62.136 ; + END + END dout_b[68] + PIN dout_b[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.160 0.024 62.184 ; + END + END dout_b[69] + PIN dout_b[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.208 0.024 62.232 ; + END + END dout_b[70] + PIN dout_b[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.256 0.024 62.280 ; + END + END dout_b[71] + PIN dout_b[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.304 0.024 62.328 ; + END + END dout_b[72] + PIN dout_b[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.352 0.024 62.376 ; + END + END dout_b[73] + PIN dout_b[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.400 0.024 62.424 ; + END + END dout_b[74] + PIN dout_b[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.448 0.024 62.472 ; + END + END dout_b[75] + PIN dout_b[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.496 0.024 62.520 ; + END + END dout_b[76] + PIN dout_b[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.544 0.024 62.568 ; + END + END dout_b[77] + PIN dout_b[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.592 0.024 62.616 ; + END + END dout_b[78] + PIN dout_b[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.640 0.024 62.664 ; + END + END dout_b[79] + PIN dout_b[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.688 0.024 62.712 ; + END + END dout_b[80] + PIN dout_b[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.736 0.024 62.760 ; + END + END dout_b[81] + PIN dout_b[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.784 0.024 62.808 ; + END + END dout_b[82] + PIN dout_b[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.832 0.024 62.856 ; + END + END dout_b[83] + PIN dout_b[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.880 0.024 62.904 ; + END + END dout_b[84] + PIN dout_b[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.928 0.024 62.952 ; + END + END dout_b[85] + PIN dout_b[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.976 0.024 63.000 ; + END + END dout_b[86] + PIN dout_b[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.024 0.024 63.048 ; + END + END dout_b[87] + PIN dout_b[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.072 0.024 63.096 ; + END + END dout_b[88] + PIN dout_b[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.120 0.024 63.144 ; + END + END dout_b[89] + PIN dout_b[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.168 0.024 63.192 ; + END + END dout_b[90] + PIN dout_b[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.216 0.024 63.240 ; + END + END dout_b[91] + PIN dout_b[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.264 0.024 63.288 ; + END + END dout_b[92] + PIN dout_b[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.312 0.024 63.336 ; + END + END dout_b[93] + PIN dout_b[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.360 0.024 63.384 ; + END + END dout_b[94] + PIN dout_b[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.408 0.024 63.432 ; + END + END dout_b[95] + PIN dout_b[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.456 0.024 63.480 ; + END + END dout_b[96] + PIN dout_b[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.504 0.024 63.528 ; + END + END dout_b[97] + PIN dout_b[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.552 0.024 63.576 ; + END + END dout_b[98] + PIN dout_b[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.600 0.024 63.624 ; + END + END dout_b[99] + PIN dout_b[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.648 0.024 63.672 ; + END + END dout_b[100] + PIN dout_b[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.696 0.024 63.720 ; + END + END dout_b[101] + PIN dout_b[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.744 0.024 63.768 ; + END + END dout_b[102] + PIN dout_b[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.792 0.024 63.816 ; + END + END dout_b[103] + PIN dout_b[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.840 0.024 63.864 ; + END + END dout_b[104] + PIN dout_b[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.888 0.024 63.912 ; + END + END dout_b[105] + PIN dout_b[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.936 0.024 63.960 ; + END + END dout_b[106] + PIN dout_b[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.984 0.024 64.008 ; + END + END dout_b[107] + PIN dout_b[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.032 0.024 64.056 ; + END + END dout_b[108] + PIN dout_b[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.080 0.024 64.104 ; + END + END dout_b[109] + PIN dout_b[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.128 0.024 64.152 ; + END + END dout_b[110] + PIN dout_b[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.176 0.024 64.200 ; + END + END dout_b[111] + PIN dout_b[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.224 0.024 64.248 ; + END + END dout_b[112] + PIN dout_b[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.272 0.024 64.296 ; + END + END dout_b[113] + PIN dout_b[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.320 0.024 64.344 ; + END + END dout_b[114] + PIN dout_b[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.368 0.024 64.392 ; + END + END dout_b[115] + PIN dout_b[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.416 0.024 64.440 ; + END + END dout_b[116] + PIN dout_b[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.464 0.024 64.488 ; + END + END dout_b[117] + PIN dout_b[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.512 0.024 64.536 ; + END + END dout_b[118] + PIN dout_b[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.560 0.024 64.584 ; + END + END dout_b[119] + PIN dout_b[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.608 0.024 64.632 ; + END + END dout_b[120] + PIN dout_b[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.656 0.024 64.680 ; + END + END dout_b[121] + PIN dout_b[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.704 0.024 64.728 ; + END + END dout_b[122] + PIN dout_b[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.752 0.024 64.776 ; + END + END dout_b[123] + PIN dout_b[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.800 0.024 64.824 ; + END + END dout_b[124] + PIN dout_b[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.848 0.024 64.872 ; + END + END dout_b[125] + PIN dout_b[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.896 0.024 64.920 ; + END + END dout_b[126] + PIN dout_b[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.944 0.024 64.968 ; + END + END dout_b[127] + PIN dout_b[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.992 0.024 65.016 ; + END + END dout_b[128] + PIN dout_b[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.040 0.024 65.064 ; + END + END dout_b[129] + PIN dout_b[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.088 0.024 65.112 ; + END + END dout_b[130] + PIN dout_b[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.136 0.024 65.160 ; + END + END dout_b[131] + PIN dout_b[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.184 0.024 65.208 ; + END + END dout_b[132] + PIN dout_b[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.232 0.024 65.256 ; + END + END dout_b[133] + PIN dout_b[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.280 0.024 65.304 ; + END + END dout_b[134] + PIN dout_b[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.328 0.024 65.352 ; + END + END dout_b[135] + PIN dout_b[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.376 0.024 65.400 ; + END + END dout_b[136] + PIN dout_b[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.424 0.024 65.448 ; + END + END dout_b[137] + PIN dout_b[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.472 0.024 65.496 ; + END + END dout_b[138] + PIN dout_b[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.520 0.024 65.544 ; + END + END dout_b[139] + PIN dout_b[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.568 0.024 65.592 ; + END + END dout_b[140] + PIN dout_b[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.616 0.024 65.640 ; + END + END dout_b[141] + PIN dout_b[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.664 0.024 65.688 ; + END + END dout_b[142] + PIN dout_b[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.712 0.024 65.736 ; + END + END dout_b[143] + PIN dout_b[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.760 0.024 65.784 ; + END + END dout_b[144] + PIN dout_b[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.808 0.024 65.832 ; + END + END dout_b[145] + PIN dout_b[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.856 0.024 65.880 ; + END + END dout_b[146] + PIN dout_b[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.904 0.024 65.928 ; + END + END dout_b[147] + PIN dout_b[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.952 0.024 65.976 ; + END + END dout_b[148] + PIN dout_b[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.000 0.024 66.024 ; + END + END dout_b[149] + PIN dout_b[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.048 0.024 66.072 ; + END + END dout_b[150] + PIN dout_b[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.096 0.024 66.120 ; + END + END dout_b[151] + PIN dout_b[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.144 0.024 66.168 ; + END + END dout_b[152] + PIN dout_b[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.192 0.024 66.216 ; + END + END dout_b[153] + PIN dout_b[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.240 0.024 66.264 ; + END + END dout_b[154] + PIN dout_b[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.288 0.024 66.312 ; + END + END dout_b[155] + PIN dout_b[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.336 0.024 66.360 ; + END + END dout_b[156] + PIN dout_b[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.384 0.024 66.408 ; + END + END dout_b[157] + PIN dout_b[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.432 0.024 66.456 ; + END + END dout_b[158] + PIN dout_b[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.480 0.024 66.504 ; + END + END dout_b[159] + PIN dout_b[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.528 0.024 66.552 ; + END + END dout_b[160] + PIN dout_b[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.576 0.024 66.600 ; + END + END dout_b[161] + PIN dout_b[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.624 0.024 66.648 ; + END + END dout_b[162] + PIN dout_b[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.672 0.024 66.696 ; + END + END dout_b[163] + PIN dout_b[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.720 0.024 66.744 ; + END + END dout_b[164] + PIN dout_b[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.768 0.024 66.792 ; + END + END dout_b[165] + PIN dout_b[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.816 0.024 66.840 ; + END + END dout_b[166] + PIN dout_b[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.864 0.024 66.888 ; + END + END dout_b[167] + PIN dout_b[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.912 0.024 66.936 ; + END + END dout_b[168] + PIN dout_b[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.960 0.024 66.984 ; + END + END dout_b[169] + PIN dout_b[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.008 0.024 67.032 ; + END + END dout_b[170] + PIN dout_b[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.056 0.024 67.080 ; + END + END dout_b[171] + PIN dout_b[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.104 0.024 67.128 ; + END + END dout_b[172] + PIN dout_b[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.152 0.024 67.176 ; + END + END dout_b[173] + PIN dout_b[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.200 0.024 67.224 ; + END + END dout_b[174] + PIN dout_b[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.248 0.024 67.272 ; + END + END dout_b[175] + PIN dout_b[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.296 0.024 67.320 ; + END + END dout_b[176] + PIN dout_b[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.344 0.024 67.368 ; + END + END dout_b[177] + PIN dout_b[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.392 0.024 67.416 ; + END + END dout_b[178] + PIN dout_b[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.440 0.024 67.464 ; + END + END dout_b[179] + PIN dout_b[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.488 0.024 67.512 ; + END + END dout_b[180] + PIN dout_b[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.536 0.024 67.560 ; + END + END dout_b[181] + PIN dout_b[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.584 0.024 67.608 ; + END + END dout_b[182] + PIN dout_b[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.632 0.024 67.656 ; + END + END dout_b[183] + PIN dout_b[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.680 0.024 67.704 ; + END + END dout_b[184] + PIN dout_b[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.728 0.024 67.752 ; + END + END dout_b[185] + PIN dout_b[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.776 0.024 67.800 ; + END + END dout_b[186] + PIN dout_b[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.824 0.024 67.848 ; + END + END dout_b[187] + PIN dout_b[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.872 0.024 67.896 ; + END + END dout_b[188] + PIN dout_b[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.920 0.024 67.944 ; + END + END dout_b[189] + PIN dout_b[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.968 0.024 67.992 ; + END + END dout_b[190] + PIN dout_b[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.016 0.024 68.040 ; + END + END dout_b[191] + PIN dout_b[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.064 0.024 68.088 ; + END + END dout_b[192] + PIN dout_b[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.112 0.024 68.136 ; + END + END dout_b[193] + PIN dout_b[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.160 0.024 68.184 ; + END + END dout_b[194] + PIN dout_b[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.208 0.024 68.232 ; + END + END dout_b[195] + PIN dout_b[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.256 0.024 68.280 ; + END + END dout_b[196] + PIN dout_b[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.304 0.024 68.328 ; + END + END dout_b[197] + PIN dout_b[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.352 0.024 68.376 ; + END + END dout_b[198] + PIN dout_b[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.400 0.024 68.424 ; + END + END dout_b[199] + PIN dout_b[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.448 0.024 68.472 ; + END + END dout_b[200] + PIN dout_b[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.496 0.024 68.520 ; + END + END dout_b[201] + PIN dout_b[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.544 0.024 68.568 ; + END + END dout_b[202] + PIN dout_b[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.592 0.024 68.616 ; + END + END dout_b[203] + PIN dout_b[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.640 0.024 68.664 ; + END + END dout_b[204] + PIN dout_b[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.688 0.024 68.712 ; + END + END dout_b[205] + PIN dout_b[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.736 0.024 68.760 ; + END + END dout_b[206] + PIN dout_b[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.784 0.024 68.808 ; + END + END dout_b[207] + PIN dout_b[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.832 0.024 68.856 ; + END + END dout_b[208] + PIN dout_b[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.880 0.024 68.904 ; + END + END dout_b[209] + PIN dout_b[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.928 0.024 68.952 ; + END + END dout_b[210] + PIN dout_b[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.976 0.024 69.000 ; + END + END dout_b[211] + PIN dout_b[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.024 0.024 69.048 ; + END + END dout_b[212] + PIN dout_b[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.072 0.024 69.096 ; + END + END dout_b[213] + PIN dout_b[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.120 0.024 69.144 ; + END + END dout_b[214] + PIN dout_b[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.168 0.024 69.192 ; + END + END dout_b[215] + PIN dout_b[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.216 0.024 69.240 ; + END + END dout_b[216] + PIN dout_b[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.264 0.024 69.288 ; + END + END dout_b[217] + PIN dout_b[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.312 0.024 69.336 ; + END + END dout_b[218] + PIN dout_b[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.360 0.024 69.384 ; + END + END dout_b[219] + PIN dout_b[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.408 0.024 69.432 ; + END + END dout_b[220] + PIN dout_b[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.456 0.024 69.480 ; + END + END dout_b[221] + PIN dout_b[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.504 0.024 69.528 ; + END + END dout_b[222] + PIN dout_b[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.552 0.024 69.576 ; + END + END dout_b[223] + PIN dout_b[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.600 0.024 69.624 ; + END + END dout_b[224] + PIN dout_b[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.648 0.024 69.672 ; + END + END dout_b[225] + PIN dout_b[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.696 0.024 69.720 ; + END + END dout_b[226] + PIN dout_b[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.744 0.024 69.768 ; + END + END dout_b[227] + PIN dout_b[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.792 0.024 69.816 ; + END + END dout_b[228] + PIN dout_b[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.840 0.024 69.864 ; + END + END dout_b[229] + PIN dout_b[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.888 0.024 69.912 ; + END + END dout_b[230] + PIN dout_b[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.936 0.024 69.960 ; + END + END dout_b[231] + PIN dout_b[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.984 0.024 70.008 ; + END + END dout_b[232] + PIN dout_b[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.032 0.024 70.056 ; + END + END dout_b[233] + PIN dout_b[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.080 0.024 70.104 ; + END + END dout_b[234] + PIN dout_b[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.128 0.024 70.152 ; + END + END dout_b[235] + PIN dout_b[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.176 0.024 70.200 ; + END + END dout_b[236] + PIN dout_b[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.224 0.024 70.248 ; + END + END dout_b[237] + PIN dout_b[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.272 0.024 70.296 ; + END + END dout_b[238] + PIN dout_b[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.320 0.024 70.344 ; + END + END dout_b[239] + PIN dout_b[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.368 0.024 70.392 ; + END + END dout_b[240] + PIN dout_b[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.416 0.024 70.440 ; + END + END dout_b[241] + PIN dout_b[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.464 0.024 70.488 ; + END + END dout_b[242] + PIN dout_b[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.512 0.024 70.536 ; + END + END dout_b[243] + PIN dout_b[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.560 0.024 70.584 ; + END + END dout_b[244] + PIN dout_b[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.608 0.024 70.632 ; + END + END dout_b[245] + PIN dout_b[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.656 0.024 70.680 ; + END + END dout_b[246] + PIN dout_b[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.704 0.024 70.728 ; + END + END dout_b[247] + PIN dout_b[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.752 0.024 70.776 ; + END + END dout_b[248] + PIN dout_b[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.800 0.024 70.824 ; + END + END dout_b[249] + PIN dout_b[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.848 0.024 70.872 ; + END + END dout_b[250] + PIN dout_b[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.896 0.024 70.920 ; + END + END dout_b[251] + PIN dout_b[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.944 0.024 70.968 ; + END + END dout_b[252] + PIN dout_b[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.992 0.024 71.016 ; + END + END dout_b[253] + PIN dout_b[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.040 0.024 71.064 ; + END + END dout_b[254] + PIN dout_b[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.088 0.024 71.112 ; + END + END dout_b[255] + PIN din_b[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.416 0.024 82.440 ; + END + END din_b[0] + PIN din_b[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.464 0.024 82.488 ; + END + END din_b[1] + PIN din_b[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.512 0.024 82.536 ; + END + END din_b[2] + PIN din_b[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.560 0.024 82.584 ; + END + END din_b[3] + PIN din_b[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.608 0.024 82.632 ; + END + END din_b[4] + PIN din_b[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.656 0.024 82.680 ; + END + END din_b[5] + PIN din_b[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.704 0.024 82.728 ; + END + END din_b[6] + PIN din_b[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.752 0.024 82.776 ; + END + END din_b[7] + PIN din_b[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.800 0.024 82.824 ; + END + END din_b[8] + PIN din_b[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.848 0.024 82.872 ; + END + END din_b[9] + PIN din_b[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.896 0.024 82.920 ; + END + END din_b[10] + PIN din_b[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.944 0.024 82.968 ; + END + END din_b[11] + PIN din_b[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.992 0.024 83.016 ; + END + END din_b[12] + PIN din_b[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.040 0.024 83.064 ; + END + END din_b[13] + PIN din_b[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.088 0.024 83.112 ; + END + END din_b[14] + PIN din_b[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.136 0.024 83.160 ; + END + END din_b[15] + PIN din_b[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.184 0.024 83.208 ; + END + END din_b[16] + PIN din_b[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.232 0.024 83.256 ; + END + END din_b[17] + PIN din_b[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.280 0.024 83.304 ; + END + END din_b[18] + PIN din_b[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.328 0.024 83.352 ; + END + END din_b[19] + PIN din_b[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.376 0.024 83.400 ; + END + END din_b[20] + PIN din_b[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.424 0.024 83.448 ; + END + END din_b[21] + PIN din_b[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.472 0.024 83.496 ; + END + END din_b[22] + PIN din_b[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.520 0.024 83.544 ; + END + END din_b[23] + PIN din_b[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.568 0.024 83.592 ; + END + END din_b[24] + PIN din_b[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.616 0.024 83.640 ; + END + END din_b[25] + PIN din_b[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.664 0.024 83.688 ; + END + END din_b[26] + PIN din_b[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.712 0.024 83.736 ; + END + END din_b[27] + PIN din_b[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.760 0.024 83.784 ; + END + END din_b[28] + PIN din_b[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.808 0.024 83.832 ; + END + END din_b[29] + PIN din_b[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.856 0.024 83.880 ; + END + END din_b[30] + PIN din_b[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.904 0.024 83.928 ; + END + END din_b[31] + PIN din_b[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.952 0.024 83.976 ; + END + END din_b[32] + PIN din_b[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.000 0.024 84.024 ; + END + END din_b[33] + PIN din_b[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.048 0.024 84.072 ; + END + END din_b[34] + PIN din_b[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.096 0.024 84.120 ; + END + END din_b[35] + PIN din_b[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.144 0.024 84.168 ; + END + END din_b[36] + PIN din_b[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.192 0.024 84.216 ; + END + END din_b[37] + PIN din_b[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.240 0.024 84.264 ; + END + END din_b[38] + PIN din_b[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.288 0.024 84.312 ; + END + END din_b[39] + PIN din_b[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.336 0.024 84.360 ; + END + END din_b[40] + PIN din_b[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.384 0.024 84.408 ; + END + END din_b[41] + PIN din_b[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.432 0.024 84.456 ; + END + END din_b[42] + PIN din_b[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.480 0.024 84.504 ; + END + END din_b[43] + PIN din_b[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.528 0.024 84.552 ; + END + END din_b[44] + PIN din_b[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.576 0.024 84.600 ; + END + END din_b[45] + PIN din_b[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.624 0.024 84.648 ; + END + END din_b[46] + PIN din_b[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.672 0.024 84.696 ; + END + END din_b[47] + PIN din_b[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.720 0.024 84.744 ; + END + END din_b[48] + PIN din_b[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.768 0.024 84.792 ; + END + END din_b[49] + PIN din_b[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.816 0.024 84.840 ; + END + END din_b[50] + PIN din_b[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.864 0.024 84.888 ; + END + END din_b[51] + PIN din_b[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.912 0.024 84.936 ; + END + END din_b[52] + PIN din_b[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.960 0.024 84.984 ; + END + END din_b[53] + PIN din_b[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.008 0.024 85.032 ; + END + END din_b[54] + PIN din_b[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.056 0.024 85.080 ; + END + END din_b[55] + PIN din_b[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.104 0.024 85.128 ; + END + END din_b[56] + PIN din_b[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.152 0.024 85.176 ; + END + END din_b[57] + PIN din_b[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.200 0.024 85.224 ; + END + END din_b[58] + PIN din_b[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.248 0.024 85.272 ; + END + END din_b[59] + PIN din_b[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.296 0.024 85.320 ; + END + END din_b[60] + PIN din_b[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.344 0.024 85.368 ; + END + END din_b[61] + PIN din_b[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.392 0.024 85.416 ; + END + END din_b[62] + PIN din_b[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.440 0.024 85.464 ; + END + END din_b[63] + PIN din_b[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.488 0.024 85.512 ; + END + END din_b[64] + PIN din_b[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.536 0.024 85.560 ; + END + END din_b[65] + PIN din_b[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.584 0.024 85.608 ; + END + END din_b[66] + PIN din_b[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.632 0.024 85.656 ; + END + END din_b[67] + PIN din_b[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.680 0.024 85.704 ; + END + END din_b[68] + PIN din_b[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.728 0.024 85.752 ; + END + END din_b[69] + PIN din_b[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.776 0.024 85.800 ; + END + END din_b[70] + PIN din_b[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.824 0.024 85.848 ; + END + END din_b[71] + PIN din_b[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.872 0.024 85.896 ; + END + END din_b[72] + PIN din_b[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.920 0.024 85.944 ; + END + END din_b[73] + PIN din_b[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.968 0.024 85.992 ; + END + END din_b[74] + PIN din_b[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.016 0.024 86.040 ; + END + END din_b[75] + PIN din_b[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.064 0.024 86.088 ; + END + END din_b[76] + PIN din_b[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.112 0.024 86.136 ; + END + END din_b[77] + PIN din_b[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.160 0.024 86.184 ; + END + END din_b[78] + PIN din_b[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.208 0.024 86.232 ; + END + END din_b[79] + PIN din_b[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.256 0.024 86.280 ; + END + END din_b[80] + PIN din_b[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.304 0.024 86.328 ; + END + END din_b[81] + PIN din_b[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.352 0.024 86.376 ; + END + END din_b[82] + PIN din_b[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.400 0.024 86.424 ; + END + END din_b[83] + PIN din_b[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.448 0.024 86.472 ; + END + END din_b[84] + PIN din_b[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.496 0.024 86.520 ; + END + END din_b[85] + PIN din_b[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.544 0.024 86.568 ; + END + END din_b[86] + PIN din_b[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.592 0.024 86.616 ; + END + END din_b[87] + PIN din_b[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.640 0.024 86.664 ; + END + END din_b[88] + PIN din_b[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.688 0.024 86.712 ; + END + END din_b[89] + PIN din_b[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.736 0.024 86.760 ; + END + END din_b[90] + PIN din_b[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.784 0.024 86.808 ; + END + END din_b[91] + PIN din_b[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.832 0.024 86.856 ; + END + END din_b[92] + PIN din_b[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.880 0.024 86.904 ; + END + END din_b[93] + PIN din_b[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.928 0.024 86.952 ; + END + END din_b[94] + PIN din_b[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.976 0.024 87.000 ; + END + END din_b[95] + PIN din_b[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.024 0.024 87.048 ; + END + END din_b[96] + PIN din_b[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.072 0.024 87.096 ; + END + END din_b[97] + PIN din_b[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.120 0.024 87.144 ; + END + END din_b[98] + PIN din_b[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.168 0.024 87.192 ; + END + END din_b[99] + PIN din_b[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.216 0.024 87.240 ; + END + END din_b[100] + PIN din_b[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.264 0.024 87.288 ; + END + END din_b[101] + PIN din_b[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.312 0.024 87.336 ; + END + END din_b[102] + PIN din_b[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.360 0.024 87.384 ; + END + END din_b[103] + PIN din_b[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.408 0.024 87.432 ; + END + END din_b[104] + PIN din_b[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.456 0.024 87.480 ; + END + END din_b[105] + PIN din_b[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.504 0.024 87.528 ; + END + END din_b[106] + PIN din_b[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.552 0.024 87.576 ; + END + END din_b[107] + PIN din_b[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.600 0.024 87.624 ; + END + END din_b[108] + PIN din_b[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.648 0.024 87.672 ; + END + END din_b[109] + PIN din_b[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.696 0.024 87.720 ; + END + END din_b[110] + PIN din_b[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.744 0.024 87.768 ; + END + END din_b[111] + PIN din_b[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.792 0.024 87.816 ; + END + END din_b[112] + PIN din_b[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.840 0.024 87.864 ; + END + END din_b[113] + PIN din_b[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.888 0.024 87.912 ; + END + END din_b[114] + PIN din_b[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.936 0.024 87.960 ; + END + END din_b[115] + PIN din_b[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.984 0.024 88.008 ; + END + END din_b[116] + PIN din_b[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.032 0.024 88.056 ; + END + END din_b[117] + PIN din_b[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.080 0.024 88.104 ; + END + END din_b[118] + PIN din_b[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.128 0.024 88.152 ; + END + END din_b[119] + PIN din_b[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.176 0.024 88.200 ; + END + END din_b[120] + PIN din_b[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.224 0.024 88.248 ; + END + END din_b[121] + PIN din_b[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.272 0.024 88.296 ; + END + END din_b[122] + PIN din_b[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.320 0.024 88.344 ; + END + END din_b[123] + PIN din_b[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.368 0.024 88.392 ; + END + END din_b[124] + PIN din_b[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.416 0.024 88.440 ; + END + END din_b[125] + PIN din_b[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.464 0.024 88.488 ; + END + END din_b[126] + PIN din_b[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.512 0.024 88.536 ; + END + END din_b[127] + PIN din_b[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.560 0.024 88.584 ; + END + END din_b[128] + PIN din_b[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.608 0.024 88.632 ; + END + END din_b[129] + PIN din_b[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.656 0.024 88.680 ; + END + END din_b[130] + PIN din_b[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.704 0.024 88.728 ; + END + END din_b[131] + PIN din_b[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.752 0.024 88.776 ; + END + END din_b[132] + PIN din_b[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.800 0.024 88.824 ; + END + END din_b[133] + PIN din_b[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.848 0.024 88.872 ; + END + END din_b[134] + PIN din_b[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.896 0.024 88.920 ; + END + END din_b[135] + PIN din_b[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.944 0.024 88.968 ; + END + END din_b[136] + PIN din_b[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.992 0.024 89.016 ; + END + END din_b[137] + PIN din_b[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.040 0.024 89.064 ; + END + END din_b[138] + PIN din_b[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.088 0.024 89.112 ; + END + END din_b[139] + PIN din_b[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.136 0.024 89.160 ; + END + END din_b[140] + PIN din_b[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.184 0.024 89.208 ; + END + END din_b[141] + PIN din_b[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.232 0.024 89.256 ; + END + END din_b[142] + PIN din_b[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.280 0.024 89.304 ; + END + END din_b[143] + PIN din_b[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.328 0.024 89.352 ; + END + END din_b[144] + PIN din_b[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.376 0.024 89.400 ; + END + END din_b[145] + PIN din_b[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.424 0.024 89.448 ; + END + END din_b[146] + PIN din_b[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.472 0.024 89.496 ; + END + END din_b[147] + PIN din_b[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.520 0.024 89.544 ; + END + END din_b[148] + PIN din_b[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.568 0.024 89.592 ; + END + END din_b[149] + PIN din_b[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.616 0.024 89.640 ; + END + END din_b[150] + PIN din_b[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.664 0.024 89.688 ; + END + END din_b[151] + PIN din_b[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.712 0.024 89.736 ; + END + END din_b[152] + PIN din_b[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.760 0.024 89.784 ; + END + END din_b[153] + PIN din_b[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.808 0.024 89.832 ; + END + END din_b[154] + PIN din_b[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.856 0.024 89.880 ; + END + END din_b[155] + PIN din_b[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.904 0.024 89.928 ; + END + END din_b[156] + PIN din_b[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.952 0.024 89.976 ; + END + END din_b[157] + PIN din_b[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.000 0.024 90.024 ; + END + END din_b[158] + PIN din_b[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.048 0.024 90.072 ; + END + END din_b[159] + PIN din_b[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.096 0.024 90.120 ; + END + END din_b[160] + PIN din_b[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.144 0.024 90.168 ; + END + END din_b[161] + PIN din_b[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.192 0.024 90.216 ; + END + END din_b[162] + PIN din_b[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.240 0.024 90.264 ; + END + END din_b[163] + PIN din_b[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.288 0.024 90.312 ; + END + END din_b[164] + PIN din_b[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.336 0.024 90.360 ; + END + END din_b[165] + PIN din_b[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.384 0.024 90.408 ; + END + END din_b[166] + PIN din_b[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.432 0.024 90.456 ; + END + END din_b[167] + PIN din_b[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.480 0.024 90.504 ; + END + END din_b[168] + PIN din_b[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.528 0.024 90.552 ; + END + END din_b[169] + PIN din_b[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.576 0.024 90.600 ; + END + END din_b[170] + PIN din_b[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.624 0.024 90.648 ; + END + END din_b[171] + PIN din_b[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.672 0.024 90.696 ; + END + END din_b[172] + PIN din_b[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.720 0.024 90.744 ; + END + END din_b[173] + PIN din_b[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.768 0.024 90.792 ; + END + END din_b[174] + PIN din_b[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.816 0.024 90.840 ; + END + END din_b[175] + PIN din_b[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.864 0.024 90.888 ; + END + END din_b[176] + PIN din_b[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.912 0.024 90.936 ; + END + END din_b[177] + PIN din_b[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.960 0.024 90.984 ; + END + END din_b[178] + PIN din_b[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.008 0.024 91.032 ; + END + END din_b[179] + PIN din_b[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.056 0.024 91.080 ; + END + END din_b[180] + PIN din_b[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.104 0.024 91.128 ; + END + END din_b[181] + PIN din_b[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.152 0.024 91.176 ; + END + END din_b[182] + PIN din_b[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.200 0.024 91.224 ; + END + END din_b[183] + PIN din_b[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.248 0.024 91.272 ; + END + END din_b[184] + PIN din_b[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.296 0.024 91.320 ; + END + END din_b[185] + PIN din_b[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.344 0.024 91.368 ; + END + END din_b[186] + PIN din_b[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.392 0.024 91.416 ; + END + END din_b[187] + PIN din_b[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.440 0.024 91.464 ; + END + END din_b[188] + PIN din_b[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.488 0.024 91.512 ; + END + END din_b[189] + PIN din_b[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.536 0.024 91.560 ; + END + END din_b[190] + PIN din_b[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.584 0.024 91.608 ; + END + END din_b[191] + PIN din_b[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.632 0.024 91.656 ; + END + END din_b[192] + PIN din_b[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.680 0.024 91.704 ; + END + END din_b[193] + PIN din_b[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.728 0.024 91.752 ; + END + END din_b[194] + PIN din_b[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.776 0.024 91.800 ; + END + END din_b[195] + PIN din_b[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.824 0.024 91.848 ; + END + END din_b[196] + PIN din_b[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.872 0.024 91.896 ; + END + END din_b[197] + PIN din_b[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.920 0.024 91.944 ; + END + END din_b[198] + PIN din_b[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.968 0.024 91.992 ; + END + END din_b[199] + PIN din_b[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.016 0.024 92.040 ; + END + END din_b[200] + PIN din_b[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.064 0.024 92.088 ; + END + END din_b[201] + PIN din_b[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.112 0.024 92.136 ; + END + END din_b[202] + PIN din_b[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.160 0.024 92.184 ; + END + END din_b[203] + PIN din_b[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.208 0.024 92.232 ; + END + END din_b[204] + PIN din_b[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.256 0.024 92.280 ; + END + END din_b[205] + PIN din_b[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.304 0.024 92.328 ; + END + END din_b[206] + PIN din_b[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.352 0.024 92.376 ; + END + END din_b[207] + PIN din_b[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.400 0.024 92.424 ; + END + END din_b[208] + PIN din_b[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.448 0.024 92.472 ; + END + END din_b[209] + PIN din_b[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.496 0.024 92.520 ; + END + END din_b[210] + PIN din_b[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.544 0.024 92.568 ; + END + END din_b[211] + PIN din_b[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.592 0.024 92.616 ; + END + END din_b[212] + PIN din_b[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.640 0.024 92.664 ; + END + END din_b[213] + PIN din_b[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.688 0.024 92.712 ; + END + END din_b[214] + PIN din_b[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.736 0.024 92.760 ; + END + END din_b[215] + PIN din_b[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.784 0.024 92.808 ; + END + END din_b[216] + PIN din_b[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.832 0.024 92.856 ; + END + END din_b[217] + PIN din_b[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.880 0.024 92.904 ; + END + END din_b[218] + PIN din_b[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.928 0.024 92.952 ; + END + END din_b[219] + PIN din_b[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.976 0.024 93.000 ; + END + END din_b[220] + PIN din_b[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.024 0.024 93.048 ; + END + END din_b[221] + PIN din_b[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.072 0.024 93.096 ; + END + END din_b[222] + PIN din_b[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.120 0.024 93.144 ; + END + END din_b[223] + PIN din_b[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.168 0.024 93.192 ; + END + END din_b[224] + PIN din_b[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.216 0.024 93.240 ; + END + END din_b[225] + PIN din_b[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.264 0.024 93.288 ; + END + END din_b[226] + PIN din_b[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.312 0.024 93.336 ; + END + END din_b[227] + PIN din_b[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.360 0.024 93.384 ; + END + END din_b[228] + PIN din_b[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.408 0.024 93.432 ; + END + END din_b[229] + PIN din_b[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.456 0.024 93.480 ; + END + END din_b[230] + PIN din_b[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.504 0.024 93.528 ; + END + END din_b[231] + PIN din_b[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.552 0.024 93.576 ; + END + END din_b[232] + PIN din_b[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.600 0.024 93.624 ; + END + END din_b[233] + PIN din_b[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.648 0.024 93.672 ; + END + END din_b[234] + PIN din_b[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.696 0.024 93.720 ; + END + END din_b[235] + PIN din_b[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.744 0.024 93.768 ; + END + END din_b[236] + PIN din_b[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.792 0.024 93.816 ; + END + END din_b[237] + PIN din_b[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.840 0.024 93.864 ; + END + END din_b[238] + PIN din_b[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.888 0.024 93.912 ; + END + END din_b[239] + PIN din_b[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.936 0.024 93.960 ; + END + END din_b[240] + PIN din_b[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.984 0.024 94.008 ; + END + END din_b[241] + PIN din_b[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.032 0.024 94.056 ; + END + END din_b[242] + PIN din_b[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.080 0.024 94.104 ; + END + END din_b[243] + PIN din_b[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.128 0.024 94.152 ; + END + END din_b[244] + PIN din_b[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.176 0.024 94.200 ; + END + END din_b[245] + PIN din_b[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.224 0.024 94.248 ; + END + END din_b[246] + PIN din_b[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.272 0.024 94.296 ; + END + END din_b[247] + PIN din_b[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.320 0.024 94.344 ; + END + END din_b[248] + PIN din_b[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.368 0.024 94.392 ; + END + END din_b[249] + PIN din_b[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.416 0.024 94.440 ; + END + END din_b[250] + PIN din_b[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.464 0.024 94.488 ; + END + END din_b[251] + PIN din_b[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.512 0.024 94.536 ; + END + END din_b[252] + PIN din_b[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.560 0.024 94.584 ; + END + END din_b[253] + PIN din_b[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.608 0.024 94.632 ; + END + END din_b[254] + PIN din_b[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.656 0.024 94.680 ; + END + END din_b[255] + PIN addr_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 105.984 0.024 106.008 ; + END + END addr_b[0] + PIN addr_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.032 0.024 106.056 ; + END + END addr_b[1] + PIN addr_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.080 0.024 106.104 ; + END + END addr_b[2] + PIN addr_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.128 0.024 106.152 ; + END + END addr_b[3] + PIN addr_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.176 0.024 106.200 ; + END + END addr_b[4] + PIN addr_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.224 0.024 106.248 ; + END + END addr_b[5] + PIN addr_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.272 0.024 106.296 ; + END + END addr_b[6] + PIN addr_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.320 0.024 106.344 ; + END + END addr_b[7] + PIN we_a + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.648 0.024 117.672 ; + END + END we_a + PIN we_b + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.696 0.024 117.720 ; + END + END we_b + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.744 0.024 117.768 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 33.202 0.096 ; + RECT 0.048 0.768 33.202 0.864 ; + RECT 0.048 1.536 33.202 1.632 ; + RECT 0.048 2.304 33.202 2.400 ; + RECT 0.048 3.072 33.202 3.168 ; + RECT 0.048 3.840 33.202 3.936 ; + RECT 0.048 4.608 33.202 4.704 ; + RECT 0.048 5.376 33.202 5.472 ; + RECT 0.048 6.144 33.202 6.240 ; + RECT 0.048 6.912 33.202 7.008 ; + RECT 0.048 7.680 33.202 7.776 ; + RECT 0.048 8.448 33.202 8.544 ; + RECT 0.048 9.216 33.202 9.312 ; + RECT 0.048 9.984 33.202 10.080 ; + RECT 0.048 10.752 33.202 10.848 ; + RECT 0.048 11.520 33.202 11.616 ; + RECT 0.048 12.288 33.202 12.384 ; + RECT 0.048 13.056 33.202 13.152 ; + RECT 0.048 13.824 33.202 13.920 ; + RECT 0.048 14.592 33.202 14.688 ; + RECT 0.048 15.360 33.202 15.456 ; + RECT 0.048 16.128 33.202 16.224 ; + RECT 0.048 16.896 33.202 16.992 ; + RECT 0.048 17.664 33.202 17.760 ; + RECT 0.048 18.432 33.202 18.528 ; + RECT 0.048 19.200 33.202 19.296 ; + RECT 0.048 19.968 33.202 20.064 ; + RECT 0.048 20.736 33.202 20.832 ; + RECT 0.048 21.504 33.202 21.600 ; + RECT 0.048 22.272 33.202 22.368 ; + RECT 0.048 23.040 33.202 23.136 ; + RECT 0.048 23.808 33.202 23.904 ; + RECT 0.048 24.576 33.202 24.672 ; + RECT 0.048 25.344 33.202 25.440 ; + RECT 0.048 26.112 33.202 26.208 ; + RECT 0.048 26.880 33.202 26.976 ; + RECT 0.048 27.648 33.202 27.744 ; + RECT 0.048 28.416 33.202 28.512 ; + RECT 0.048 29.184 33.202 29.280 ; + RECT 0.048 29.952 33.202 30.048 ; + RECT 0.048 30.720 33.202 30.816 ; + RECT 0.048 31.488 33.202 31.584 ; + RECT 0.048 32.256 33.202 32.352 ; + RECT 0.048 33.024 33.202 33.120 ; + RECT 0.048 33.792 33.202 33.888 ; + RECT 0.048 34.560 33.202 34.656 ; + RECT 0.048 35.328 33.202 35.424 ; + RECT 0.048 36.096 33.202 36.192 ; + RECT 0.048 36.864 33.202 36.960 ; + RECT 0.048 37.632 33.202 37.728 ; + RECT 0.048 38.400 33.202 38.496 ; + RECT 0.048 39.168 33.202 39.264 ; + RECT 0.048 39.936 33.202 40.032 ; + RECT 0.048 40.704 33.202 40.800 ; + RECT 0.048 41.472 33.202 41.568 ; + RECT 0.048 42.240 33.202 42.336 ; + RECT 0.048 43.008 33.202 43.104 ; + RECT 0.048 43.776 33.202 43.872 ; + RECT 0.048 44.544 33.202 44.640 ; + RECT 0.048 45.312 33.202 45.408 ; + RECT 0.048 46.080 33.202 46.176 ; + RECT 0.048 46.848 33.202 46.944 ; + RECT 0.048 47.616 33.202 47.712 ; + RECT 0.048 48.384 33.202 48.480 ; + RECT 0.048 49.152 33.202 49.248 ; + RECT 0.048 49.920 33.202 50.016 ; + RECT 0.048 50.688 33.202 50.784 ; + RECT 0.048 51.456 33.202 51.552 ; + RECT 0.048 52.224 33.202 52.320 ; + RECT 0.048 52.992 33.202 53.088 ; + RECT 0.048 53.760 33.202 53.856 ; + RECT 0.048 54.528 33.202 54.624 ; + RECT 0.048 55.296 33.202 55.392 ; + RECT 0.048 56.064 33.202 56.160 ; + RECT 0.048 56.832 33.202 56.928 ; + RECT 0.048 57.600 33.202 57.696 ; + RECT 0.048 58.368 33.202 58.464 ; + RECT 0.048 59.136 33.202 59.232 ; + RECT 0.048 59.904 33.202 60.000 ; + RECT 0.048 60.672 33.202 60.768 ; + RECT 0.048 61.440 33.202 61.536 ; + RECT 0.048 62.208 33.202 62.304 ; + RECT 0.048 62.976 33.202 63.072 ; + RECT 0.048 63.744 33.202 63.840 ; + RECT 0.048 64.512 33.202 64.608 ; + RECT 0.048 65.280 33.202 65.376 ; + RECT 0.048 66.048 33.202 66.144 ; + RECT 0.048 66.816 33.202 66.912 ; + RECT 0.048 67.584 33.202 67.680 ; + RECT 0.048 68.352 33.202 68.448 ; + RECT 0.048 69.120 33.202 69.216 ; + RECT 0.048 69.888 33.202 69.984 ; + RECT 0.048 70.656 33.202 70.752 ; + RECT 0.048 71.424 33.202 71.520 ; + RECT 0.048 72.192 33.202 72.288 ; + RECT 0.048 72.960 33.202 73.056 ; + RECT 0.048 73.728 33.202 73.824 ; + RECT 0.048 74.496 33.202 74.592 ; + RECT 0.048 75.264 33.202 75.360 ; + RECT 0.048 76.032 33.202 76.128 ; + RECT 0.048 76.800 33.202 76.896 ; + RECT 0.048 77.568 33.202 77.664 ; + RECT 0.048 78.336 33.202 78.432 ; + RECT 0.048 79.104 33.202 79.200 ; + RECT 0.048 79.872 33.202 79.968 ; + RECT 0.048 80.640 33.202 80.736 ; + RECT 0.048 81.408 33.202 81.504 ; + RECT 0.048 82.176 33.202 82.272 ; + RECT 0.048 82.944 33.202 83.040 ; + RECT 0.048 83.712 33.202 83.808 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 33.202 0.480 ; + RECT 0.048 1.152 33.202 1.248 ; + RECT 0.048 1.920 33.202 2.016 ; + RECT 0.048 2.688 33.202 2.784 ; + RECT 0.048 3.456 33.202 3.552 ; + RECT 0.048 4.224 33.202 4.320 ; + RECT 0.048 4.992 33.202 5.088 ; + RECT 0.048 5.760 33.202 5.856 ; + RECT 0.048 6.528 33.202 6.624 ; + RECT 0.048 7.296 33.202 7.392 ; + RECT 0.048 8.064 33.202 8.160 ; + RECT 0.048 8.832 33.202 8.928 ; + RECT 0.048 9.600 33.202 9.696 ; + RECT 0.048 10.368 33.202 10.464 ; + RECT 0.048 11.136 33.202 11.232 ; + RECT 0.048 11.904 33.202 12.000 ; + RECT 0.048 12.672 33.202 12.768 ; + RECT 0.048 13.440 33.202 13.536 ; + RECT 0.048 14.208 33.202 14.304 ; + RECT 0.048 14.976 33.202 15.072 ; + RECT 0.048 15.744 33.202 15.840 ; + RECT 0.048 16.512 33.202 16.608 ; + RECT 0.048 17.280 33.202 17.376 ; + RECT 0.048 18.048 33.202 18.144 ; + RECT 0.048 18.816 33.202 18.912 ; + RECT 0.048 19.584 33.202 19.680 ; + RECT 0.048 20.352 33.202 20.448 ; + RECT 0.048 21.120 33.202 21.216 ; + RECT 0.048 21.888 33.202 21.984 ; + RECT 0.048 22.656 33.202 22.752 ; + RECT 0.048 23.424 33.202 23.520 ; + RECT 0.048 24.192 33.202 24.288 ; + RECT 0.048 24.960 33.202 25.056 ; + RECT 0.048 25.728 33.202 25.824 ; + RECT 0.048 26.496 33.202 26.592 ; + RECT 0.048 27.264 33.202 27.360 ; + RECT 0.048 28.032 33.202 28.128 ; + RECT 0.048 28.800 33.202 28.896 ; + RECT 0.048 29.568 33.202 29.664 ; + RECT 0.048 30.336 33.202 30.432 ; + RECT 0.048 31.104 33.202 31.200 ; + RECT 0.048 31.872 33.202 31.968 ; + RECT 0.048 32.640 33.202 32.736 ; + RECT 0.048 33.408 33.202 33.504 ; + RECT 0.048 34.176 33.202 34.272 ; + RECT 0.048 34.944 33.202 35.040 ; + RECT 0.048 35.712 33.202 35.808 ; + RECT 0.048 36.480 33.202 36.576 ; + RECT 0.048 37.248 33.202 37.344 ; + RECT 0.048 38.016 33.202 38.112 ; + RECT 0.048 38.784 33.202 38.880 ; + RECT 0.048 39.552 33.202 39.648 ; + RECT 0.048 40.320 33.202 40.416 ; + RECT 0.048 41.088 33.202 41.184 ; + RECT 0.048 41.856 33.202 41.952 ; + RECT 0.048 42.624 33.202 42.720 ; + RECT 0.048 43.392 33.202 43.488 ; + RECT 0.048 44.160 33.202 44.256 ; + RECT 0.048 44.928 33.202 45.024 ; + RECT 0.048 45.696 33.202 45.792 ; + RECT 0.048 46.464 33.202 46.560 ; + RECT 0.048 47.232 33.202 47.328 ; + RECT 0.048 48.000 33.202 48.096 ; + RECT 0.048 48.768 33.202 48.864 ; + RECT 0.048 49.536 33.202 49.632 ; + RECT 0.048 50.304 33.202 50.400 ; + RECT 0.048 51.072 33.202 51.168 ; + RECT 0.048 51.840 33.202 51.936 ; + RECT 0.048 52.608 33.202 52.704 ; + RECT 0.048 53.376 33.202 53.472 ; + RECT 0.048 54.144 33.202 54.240 ; + RECT 0.048 54.912 33.202 55.008 ; + RECT 0.048 55.680 33.202 55.776 ; + RECT 0.048 56.448 33.202 56.544 ; + RECT 0.048 57.216 33.202 57.312 ; + RECT 0.048 57.984 33.202 58.080 ; + RECT 0.048 58.752 33.202 58.848 ; + RECT 0.048 59.520 33.202 59.616 ; + RECT 0.048 60.288 33.202 60.384 ; + RECT 0.048 61.056 33.202 61.152 ; + RECT 0.048 61.824 33.202 61.920 ; + RECT 0.048 62.592 33.202 62.688 ; + RECT 0.048 63.360 33.202 63.456 ; + RECT 0.048 64.128 33.202 64.224 ; + RECT 0.048 64.896 33.202 64.992 ; + RECT 0.048 65.664 33.202 65.760 ; + RECT 0.048 66.432 33.202 66.528 ; + RECT 0.048 67.200 33.202 67.296 ; + RECT 0.048 67.968 33.202 68.064 ; + RECT 0.048 68.736 33.202 68.832 ; + RECT 0.048 69.504 33.202 69.600 ; + RECT 0.048 70.272 33.202 70.368 ; + RECT 0.048 71.040 33.202 71.136 ; + RECT 0.048 71.808 33.202 71.904 ; + RECT 0.048 72.576 33.202 72.672 ; + RECT 0.048 73.344 33.202 73.440 ; + RECT 0.048 74.112 33.202 74.208 ; + RECT 0.048 74.880 33.202 74.976 ; + RECT 0.048 75.648 33.202 75.744 ; + RECT 0.048 76.416 33.202 76.512 ; + RECT 0.048 77.184 33.202 77.280 ; + RECT 0.048 77.952 33.202 78.048 ; + RECT 0.048 78.720 33.202 78.816 ; + RECT 0.048 79.488 33.202 79.584 ; + RECT 0.048 80.256 33.202 80.352 ; + RECT 0.048 81.024 33.202 81.120 ; + RECT 0.048 81.792 33.202 81.888 ; + RECT 0.048 82.560 33.202 82.656 ; + RECT 0.048 83.328 33.202 83.424 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 84.000 ; + LAYER M2 ; + RECT 0 0 33.250 84.000 ; + LAYER M3 ; + RECT 0 0 33.250 84.000 ; + LAYER M4 ; + RECT 0 0 33.250 84.000 ; + END +END dpsram_256x256 + +END LIBRARY +module dpsram_256x256 +( + we_a, + addr_a, + din_a, + dout_a, + we_b, + addr_b, + din_b, + dout_b, + clk, +); + parameter DATA_WIDTH = 256; + parameter ADDR_WIDTH = 8; + + // Port A + input wire we_a, + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] din_a, + output reg [DATA_WIDTH-1:0] dout_a, + + // Port B + input wire we_b, + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] din_b, + output reg [DATA_WIDTH-1:0] dout_b, + + input wire clk, + + // Memory array: 256 words of 256 bits + reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1]; + + // Registers for synchronous reads + reg [ADDR_WIDTH-1:0] addr_a_reg; + reg [ADDR_WIDTH-1:0] addr_b_reg; + + integer i; + + always @(posedge clk) begin + // ==== Port A write ==== + if (^we_a === 1'bx || ^addr_a === 1'bx) begin + // Unknown write enable or address ? corrupt entire memory + for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) + mem[i] <= {DATA_WIDTH{1'bx}}; + end else if (we_a) begin + mem[addr_a] <= din_a; + end + // ==== Port B write ==== + if (^we_b === 1'bx || ^addr_b === 1'bx) begin + // Unknown write enable or address ? corrupt entire memory + for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) + mem[i] <= {DATA_WIDTH{1'bx}}; + end else if (we_b) begin + mem[addr_b] <= din_b; + end + // Synchronous readback + addr_a_reg <= addr_a; + dout_a <= mem[addr_a_reg]; + addr_b_reg <= addr_b; + dout_b <= mem[addr_b_reg]; + end +endmodule +(* blackbox *) +module dpsram_256x256 ( + input we_a, + input [7:0] addr_a, + input [255:0] din_a, + output reg [255:0] dout_a, + input we_b, + input [7:0] addr_b, + input [255:0] din_b, + output reg [255:0] dout_b, + clk, +); +endmodule +library(dpsram_256x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(dpsram_256x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(dpsram_256x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(dpsram_256x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(dpsram_256x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(dpsram_256x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (dpsram_256x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (dpsram_256x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(dpsram_256x256) { + area : 2751.883; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 256; + } + pin(we_a){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_a) { + bus_type : dpsram_256x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_a) { + bus_type : dpsram_256x256_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_a) { + bus_type : dpsram_256x256_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(dpsram_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(dpsram_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(dpsram_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(dpsram_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_b){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_b) { + bus_type : dpsram_256x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_b) { + bus_type : dpsram_256x256_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_b) { + bus_type : dpsram_256x256_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(dpsram_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(dpsram_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(dpsram_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(dpsram_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(dpsram_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(dpsram_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + cell_leakage_power : 128.900; +} + +} diff --git a/test/au/dpsram_256x32.au b/test/au/dpsram_256x32.au new file mode 100644 index 0000000..c0051f7 --- /dev/null +++ b/test/au/dpsram_256x32.au @@ -0,0 +1,2102 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO dpsram_256x32 + PROPERTY width 32 ; + PROPERTY depth 256 ; + PROPERTY banks 2 ; + FOREIGN dpsram_256x32 0 0 ; + SYMMETRY X Y R90 ; + SIZE 8.360 BY 42.000 ; + CLASS BLOCK ; + PIN dout_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END dout_a[0] + PIN dout_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.024 0.312 ; + END + END dout_a[1] + PIN dout_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.024 0.552 ; + END + END dout_a[2] + PIN dout_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END dout_a[3] + PIN dout_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.024 1.032 ; + END + END dout_a[4] + PIN dout_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.024 1.272 ; + END + END dout_a[5] + PIN dout_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END dout_a[6] + PIN dout_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.728 0.024 1.752 ; + END + END dout_a[7] + PIN dout_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.024 1.992 ; + END + END dout_a[8] + PIN dout_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END dout_a[9] + PIN dout_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.024 2.472 ; + END + END dout_a[10] + PIN dout_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END dout_a[11] + PIN dout_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END dout_a[12] + PIN dout_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.024 3.192 ; + END + END dout_a[13] + PIN dout_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.024 3.432 ; + END + END dout_a[14] + PIN dout_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END dout_a[15] + PIN dout_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.888 0.024 3.912 ; + END + END dout_a[16] + PIN dout_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.024 4.152 ; + END + END dout_a[17] + PIN dout_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END dout_a[18] + PIN dout_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.024 4.632 ; + END + END dout_a[19] + PIN dout_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.848 0.024 4.872 ; + END + END dout_a[20] + PIN dout_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END dout_a[21] + PIN dout_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END dout_a[22] + PIN dout_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.024 5.592 ; + END + END dout_a[23] + PIN dout_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END dout_a[24] + PIN dout_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.048 0.024 6.072 ; + END + END dout_a[25] + PIN dout_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.288 0.024 6.312 ; + END + END dout_a[26] + PIN dout_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END dout_a[27] + PIN dout_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.768 0.024 6.792 ; + END + END dout_a[28] + PIN dout_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.008 0.024 7.032 ; + END + END dout_a[29] + PIN dout_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END dout_a[30] + PIN dout_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.488 0.024 7.512 ; + END + END dout_a[31] + PIN din_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.024 9.960 ; + END + END din_a[0] + PIN din_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.176 0.024 10.200 ; + END + END din_a[1] + PIN din_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END din_a[2] + PIN din_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.024 10.680 ; + END + END din_a[3] + PIN din_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.896 0.024 10.920 ; + END + END din_a[4] + PIN din_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END din_a[5] + PIN din_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.024 11.400 ; + END + END din_a[6] + PIN din_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.616 0.024 11.640 ; + END + END din_a[7] + PIN din_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END din_a[8] + PIN din_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.024 12.120 ; + END + END din_a[9] + PIN din_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.336 0.024 12.360 ; + END + END din_a[10] + PIN din_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.576 0.024 12.600 ; + END + END din_a[11] + PIN din_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.816 0.024 12.840 ; + END + END din_a[12] + PIN din_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.056 0.024 13.080 ; + END + END din_a[13] + PIN din_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.296 0.024 13.320 ; + END + END din_a[14] + PIN din_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.536 0.024 13.560 ; + END + END din_a[15] + PIN din_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.776 0.024 13.800 ; + END + END din_a[16] + PIN din_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.016 0.024 14.040 ; + END + END din_a[17] + PIN din_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.256 0.024 14.280 ; + END + END din_a[18] + PIN din_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.496 0.024 14.520 ; + END + END din_a[19] + PIN din_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.736 0.024 14.760 ; + END + END din_a[20] + PIN din_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.976 0.024 15.000 ; + END + END din_a[21] + PIN din_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.216 0.024 15.240 ; + END + END din_a[22] + PIN din_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.456 0.024 15.480 ; + END + END din_a[23] + PIN din_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.696 0.024 15.720 ; + END + END din_a[24] + PIN din_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.936 0.024 15.960 ; + END + END din_a[25] + PIN din_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.176 0.024 16.200 ; + END + END din_a[26] + PIN din_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.416 0.024 16.440 ; + END + END din_a[27] + PIN din_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.656 0.024 16.680 ; + END + END din_a[28] + PIN din_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.896 0.024 16.920 ; + END + END din_a[29] + PIN din_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.136 0.024 17.160 ; + END + END din_a[30] + PIN din_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.376 0.024 17.400 ; + END + END din_a[31] + PIN addr_a[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.024 19.848 ; + END + END addr_a[0] + PIN addr_a[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.024 20.088 ; + END + END addr_a[1] + PIN addr_a[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.304 0.024 20.328 ; + END + END addr_a[2] + PIN addr_a[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.544 0.024 20.568 ; + END + END addr_a[3] + PIN addr_a[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.024 20.808 ; + END + END addr_a[4] + PIN addr_a[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.024 0.024 21.048 ; + END + END addr_a[5] + PIN addr_a[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.264 0.024 21.288 ; + END + END addr_a[6] + PIN addr_a[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.024 21.528 ; + END + END addr_a[7] + PIN dout_b[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.024 23.976 ; + END + END dout_b[0] + PIN dout_b[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.024 24.216 ; + END + END dout_b[1] + PIN dout_b[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.432 0.024 24.456 ; + END + END dout_b[2] + PIN dout_b[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.024 24.696 ; + END + END dout_b[3] + PIN dout_b[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.912 0.024 24.936 ; + END + END dout_b[4] + PIN dout_b[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.152 0.024 25.176 ; + END + END dout_b[5] + PIN dout_b[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END dout_b[6] + PIN dout_b[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.024 25.656 ; + END + END dout_b[7] + PIN dout_b[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.872 0.024 25.896 ; + END + END dout_b[8] + PIN dout_b[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.024 26.136 ; + END + END dout_b[9] + PIN dout_b[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.352 0.024 26.376 ; + END + END dout_b[10] + PIN dout_b[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.592 0.024 26.616 ; + END + END dout_b[11] + PIN dout_b[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END dout_b[12] + PIN dout_b[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.072 0.024 27.096 ; + END + END dout_b[13] + PIN dout_b[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.312 0.024 27.336 ; + END + END dout_b[14] + PIN dout_b[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.024 27.576 ; + END + END dout_b[15] + PIN dout_b[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.792 0.024 27.816 ; + END + END dout_b[16] + PIN dout_b[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.032 0.024 28.056 ; + END + END dout_b[17] + PIN dout_b[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END dout_b[18] + PIN dout_b[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.512 0.024 28.536 ; + END + END dout_b[19] + PIN dout_b[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.752 0.024 28.776 ; + END + END dout_b[20] + PIN dout_b[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.024 29.016 ; + END + END dout_b[21] + PIN dout_b[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.232 0.024 29.256 ; + END + END dout_b[22] + PIN dout_b[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.472 0.024 29.496 ; + END + END dout_b[23] + PIN dout_b[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.024 29.736 ; + END + END dout_b[24] + PIN dout_b[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.952 0.024 29.976 ; + END + END dout_b[25] + PIN dout_b[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.192 0.024 30.216 ; + END + END dout_b[26] + PIN dout_b[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.024 30.456 ; + END + END dout_b[27] + PIN dout_b[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.672 0.024 30.696 ; + END + END dout_b[28] + PIN dout_b[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.912 0.024 30.936 ; + END + END dout_b[29] + PIN dout_b[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END dout_b[30] + PIN dout_b[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.392 0.024 31.416 ; + END + END dout_b[31] + PIN din_b[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.840 0.024 33.864 ; + END + END din_b[0] + PIN din_b[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.080 0.024 34.104 ; + END + END din_b[1] + PIN din_b[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.320 0.024 34.344 ; + END + END din_b[2] + PIN din_b[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.560 0.024 34.584 ; + END + END din_b[3] + PIN din_b[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.800 0.024 34.824 ; + END + END din_b[4] + PIN din_b[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.040 0.024 35.064 ; + END + END din_b[5] + PIN din_b[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.280 0.024 35.304 ; + END + END din_b[6] + PIN din_b[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.520 0.024 35.544 ; + END + END din_b[7] + PIN din_b[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END din_b[8] + PIN din_b[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.000 0.024 36.024 ; + END + END din_b[9] + PIN din_b[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.240 0.024 36.264 ; + END + END din_b[10] + PIN din_b[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.480 0.024 36.504 ; + END + END din_b[11] + PIN din_b[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.720 0.024 36.744 ; + END + END din_b[12] + PIN din_b[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.960 0.024 36.984 ; + END + END din_b[13] + PIN din_b[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.200 0.024 37.224 ; + END + END din_b[14] + PIN din_b[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.440 0.024 37.464 ; + END + END din_b[15] + PIN din_b[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.680 0.024 37.704 ; + END + END din_b[16] + PIN din_b[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.920 0.024 37.944 ; + END + END din_b[17] + PIN din_b[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.160 0.024 38.184 ; + END + END din_b[18] + PIN din_b[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.400 0.024 38.424 ; + END + END din_b[19] + PIN din_b[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.640 0.024 38.664 ; + END + END din_b[20] + PIN din_b[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.880 0.024 38.904 ; + END + END din_b[21] + PIN din_b[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.120 0.024 39.144 ; + END + END din_b[22] + PIN din_b[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.360 0.024 39.384 ; + END + END din_b[23] + PIN din_b[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.600 0.024 39.624 ; + END + END din_b[24] + PIN din_b[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.840 0.024 39.864 ; + END + END din_b[25] + PIN din_b[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.080 0.024 40.104 ; + END + END din_b[26] + PIN din_b[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.320 0.024 40.344 ; + END + END din_b[27] + PIN din_b[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.560 0.024 40.584 ; + END + END din_b[28] + PIN din_b[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.800 0.024 40.824 ; + END + END din_b[29] + PIN din_b[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.040 0.024 41.064 ; + END + END din_b[30] + PIN din_b[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.280 0.024 41.304 ; + END + END din_b[31] + PIN addr_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.728 0.024 43.752 ; + END + END addr_b[0] + PIN addr_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.968 0.024 43.992 ; + END + END addr_b[1] + PIN addr_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.208 0.024 44.232 ; + END + END addr_b[2] + PIN addr_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.448 0.024 44.472 ; + END + END addr_b[3] + PIN addr_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.688 0.024 44.712 ; + END + END addr_b[4] + PIN addr_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.928 0.024 44.952 ; + END + END addr_b[5] + PIN addr_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.168 0.024 45.192 ; + END + END addr_b[6] + PIN addr_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.408 0.024 45.432 ; + END + END addr_b[7] + PIN we_a + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.856 0.024 47.880 ; + END + END we_a + PIN we_b + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.096 0.024 48.120 ; + END + END we_b + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.336 0.024 48.360 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 8.312 0.096 ; + RECT 0.048 0.768 8.312 0.864 ; + RECT 0.048 1.536 8.312 1.632 ; + RECT 0.048 2.304 8.312 2.400 ; + RECT 0.048 3.072 8.312 3.168 ; + RECT 0.048 3.840 8.312 3.936 ; + RECT 0.048 4.608 8.312 4.704 ; + RECT 0.048 5.376 8.312 5.472 ; + RECT 0.048 6.144 8.312 6.240 ; + RECT 0.048 6.912 8.312 7.008 ; + RECT 0.048 7.680 8.312 7.776 ; + RECT 0.048 8.448 8.312 8.544 ; + RECT 0.048 9.216 8.312 9.312 ; + RECT 0.048 9.984 8.312 10.080 ; + RECT 0.048 10.752 8.312 10.848 ; + RECT 0.048 11.520 8.312 11.616 ; + RECT 0.048 12.288 8.312 12.384 ; + RECT 0.048 13.056 8.312 13.152 ; + RECT 0.048 13.824 8.312 13.920 ; + RECT 0.048 14.592 8.312 14.688 ; + RECT 0.048 15.360 8.312 15.456 ; + RECT 0.048 16.128 8.312 16.224 ; + RECT 0.048 16.896 8.312 16.992 ; + RECT 0.048 17.664 8.312 17.760 ; + RECT 0.048 18.432 8.312 18.528 ; + RECT 0.048 19.200 8.312 19.296 ; + RECT 0.048 19.968 8.312 20.064 ; + RECT 0.048 20.736 8.312 20.832 ; + RECT 0.048 21.504 8.312 21.600 ; + RECT 0.048 22.272 8.312 22.368 ; + RECT 0.048 23.040 8.312 23.136 ; + RECT 0.048 23.808 8.312 23.904 ; + RECT 0.048 24.576 8.312 24.672 ; + RECT 0.048 25.344 8.312 25.440 ; + RECT 0.048 26.112 8.312 26.208 ; + RECT 0.048 26.880 8.312 26.976 ; + RECT 0.048 27.648 8.312 27.744 ; + RECT 0.048 28.416 8.312 28.512 ; + RECT 0.048 29.184 8.312 29.280 ; + RECT 0.048 29.952 8.312 30.048 ; + RECT 0.048 30.720 8.312 30.816 ; + RECT 0.048 31.488 8.312 31.584 ; + RECT 0.048 32.256 8.312 32.352 ; + RECT 0.048 33.024 8.312 33.120 ; + RECT 0.048 33.792 8.312 33.888 ; + RECT 0.048 34.560 8.312 34.656 ; + RECT 0.048 35.328 8.312 35.424 ; + RECT 0.048 36.096 8.312 36.192 ; + RECT 0.048 36.864 8.312 36.960 ; + RECT 0.048 37.632 8.312 37.728 ; + RECT 0.048 38.400 8.312 38.496 ; + RECT 0.048 39.168 8.312 39.264 ; + RECT 0.048 39.936 8.312 40.032 ; + RECT 0.048 40.704 8.312 40.800 ; + RECT 0.048 41.472 8.312 41.568 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 8.312 0.480 ; + RECT 0.048 1.152 8.312 1.248 ; + RECT 0.048 1.920 8.312 2.016 ; + RECT 0.048 2.688 8.312 2.784 ; + RECT 0.048 3.456 8.312 3.552 ; + RECT 0.048 4.224 8.312 4.320 ; + RECT 0.048 4.992 8.312 5.088 ; + RECT 0.048 5.760 8.312 5.856 ; + RECT 0.048 6.528 8.312 6.624 ; + RECT 0.048 7.296 8.312 7.392 ; + RECT 0.048 8.064 8.312 8.160 ; + RECT 0.048 8.832 8.312 8.928 ; + RECT 0.048 9.600 8.312 9.696 ; + RECT 0.048 10.368 8.312 10.464 ; + RECT 0.048 11.136 8.312 11.232 ; + RECT 0.048 11.904 8.312 12.000 ; + RECT 0.048 12.672 8.312 12.768 ; + RECT 0.048 13.440 8.312 13.536 ; + RECT 0.048 14.208 8.312 14.304 ; + RECT 0.048 14.976 8.312 15.072 ; + RECT 0.048 15.744 8.312 15.840 ; + RECT 0.048 16.512 8.312 16.608 ; + RECT 0.048 17.280 8.312 17.376 ; + RECT 0.048 18.048 8.312 18.144 ; + RECT 0.048 18.816 8.312 18.912 ; + RECT 0.048 19.584 8.312 19.680 ; + RECT 0.048 20.352 8.312 20.448 ; + RECT 0.048 21.120 8.312 21.216 ; + RECT 0.048 21.888 8.312 21.984 ; + RECT 0.048 22.656 8.312 22.752 ; + RECT 0.048 23.424 8.312 23.520 ; + RECT 0.048 24.192 8.312 24.288 ; + RECT 0.048 24.960 8.312 25.056 ; + RECT 0.048 25.728 8.312 25.824 ; + RECT 0.048 26.496 8.312 26.592 ; + RECT 0.048 27.264 8.312 27.360 ; + RECT 0.048 28.032 8.312 28.128 ; + RECT 0.048 28.800 8.312 28.896 ; + RECT 0.048 29.568 8.312 29.664 ; + RECT 0.048 30.336 8.312 30.432 ; + RECT 0.048 31.104 8.312 31.200 ; + RECT 0.048 31.872 8.312 31.968 ; + RECT 0.048 32.640 8.312 32.736 ; + RECT 0.048 33.408 8.312 33.504 ; + RECT 0.048 34.176 8.312 34.272 ; + RECT 0.048 34.944 8.312 35.040 ; + RECT 0.048 35.712 8.312 35.808 ; + RECT 0.048 36.480 8.312 36.576 ; + RECT 0.048 37.248 8.312 37.344 ; + RECT 0.048 38.016 8.312 38.112 ; + RECT 0.048 38.784 8.312 38.880 ; + RECT 0.048 39.552 8.312 39.648 ; + RECT 0.048 40.320 8.312 40.416 ; + RECT 0.048 41.088 8.312 41.184 ; + RECT 0.048 41.856 8.312 41.952 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 8.360 42.000 ; + LAYER M2 ; + RECT 0 0 8.360 42.000 ; + LAYER M3 ; + RECT 0 0 8.360 42.000 ; + LAYER M4 ; + RECT 0 0 8.360 42.000 ; + END +END dpsram_256x32 + +END LIBRARY +module dpsram_256x32 +( + we_a, + addr_a, + din_a, + dout_a, + we_b, + addr_b, + din_b, + dout_b, + clk, +); + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 8; + + // Port A + input wire we_a, + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] din_a, + output reg [DATA_WIDTH-1:0] dout_a, + + // Port B + input wire we_b, + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] din_b, + output reg [DATA_WIDTH-1:0] dout_b, + + input wire clk, + + // Memory array: 256 words of 32 bits + reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1]; + + // Registers for synchronous reads + reg [ADDR_WIDTH-1:0] addr_a_reg; + reg [ADDR_WIDTH-1:0] addr_b_reg; + + integer i; + + always @(posedge clk) begin + // ==== Port A write ==== + if (^we_a === 1'bx || ^addr_a === 1'bx) begin + // Unknown write enable or address ? corrupt entire memory + for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) + mem[i] <= {DATA_WIDTH{1'bx}}; + end else if (we_a) begin + mem[addr_a] <= din_a; + end + // ==== Port B write ==== + if (^we_b === 1'bx || ^addr_b === 1'bx) begin + // Unknown write enable or address ? corrupt entire memory + for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) + mem[i] <= {DATA_WIDTH{1'bx}}; + end else if (we_b) begin + mem[addr_b] <= din_b; + end + // Synchronous readback + addr_a_reg <= addr_a; + dout_a <= mem[addr_a_reg]; + addr_b_reg <= addr_b; + dout_b <= mem[addr_b_reg]; + end +endmodule +(* blackbox *) +module dpsram_256x32 ( + input we_a, + input [7:0] addr_a, + input [31:0] din_a, + output reg [31:0] dout_a, + input we_b, + input [7:0] addr_b, + input [31:0] din_b, + output reg [31:0] dout_b, + clk, +); +endmodule +library(dpsram_256x32) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(dpsram_256x32_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(dpsram_256x32_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(dpsram_256x32_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(dpsram_256x32_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(dpsram_256x32_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (dpsram_256x32_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 32; + bit_from : 31; + bit_to : 0 ; + downto : true ; + } + type (dpsram_256x32_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(dpsram_256x32) { + area : 343.985; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 32; + } + pin(we_a){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_a) { + bus_type : dpsram_256x32_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_a) { + bus_type : dpsram_256x32_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_a) { + bus_type : dpsram_256x32_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(dpsram_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(dpsram_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(dpsram_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(dpsram_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_b){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_b) { + bus_type : dpsram_256x32_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_b) { + bus_type : dpsram_256x32_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(dpsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(dpsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_b) { + bus_type : dpsram_256x32_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(dpsram_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(dpsram_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(dpsram_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(dpsram_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(dpsram_256x32_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(dpsram_256x32_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + cell_leakage_power : 128.900; +} + +} diff --git a/test/au/sprf_256x256.au b/test/au/sprf_256x256.au new file mode 100644 index 0000000..ec481fa --- /dev/null +++ b/test/au/sprf_256x256.au @@ -0,0 +1,5322 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO sprf_256x256 + PROPERTY width 256 ; + PROPERTY depth 256 ; + PROPERTY banks 1 ; + FOREIGN sprf_256x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 84.000 ; + CLASS BLOCK ; + PIN dout_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END dout_a[0] + PIN dout_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END dout_a[1] + PIN dout_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END dout_a[2] + PIN dout_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END dout_a[3] + PIN dout_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END dout_a[4] + PIN dout_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END dout_a[5] + PIN dout_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END dout_a[6] + PIN dout_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END dout_a[7] + PIN dout_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END dout_a[8] + PIN dout_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END dout_a[9] + PIN dout_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END dout_a[10] + PIN dout_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END dout_a[11] + PIN dout_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END dout_a[12] + PIN dout_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END dout_a[13] + PIN dout_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END dout_a[14] + PIN dout_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END dout_a[15] + PIN dout_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END dout_a[16] + PIN dout_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END dout_a[17] + PIN dout_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END dout_a[18] + PIN dout_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END dout_a[19] + PIN dout_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END dout_a[20] + PIN dout_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END dout_a[21] + PIN dout_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END dout_a[22] + PIN dout_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END dout_a[23] + PIN dout_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END dout_a[24] + PIN dout_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END dout_a[25] + PIN dout_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END dout_a[26] + PIN dout_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END dout_a[27] + PIN dout_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END dout_a[28] + PIN dout_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END dout_a[29] + PIN dout_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END dout_a[30] + PIN dout_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END dout_a[31] + PIN dout_a[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END dout_a[32] + PIN dout_a[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END dout_a[33] + PIN dout_a[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END dout_a[34] + PIN dout_a[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END dout_a[35] + PIN dout_a[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END dout_a[36] + PIN dout_a[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END dout_a[37] + PIN dout_a[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END dout_a[38] + PIN dout_a[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END dout_a[39] + PIN dout_a[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END dout_a[40] + PIN dout_a[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END dout_a[41] + PIN dout_a[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END dout_a[42] + PIN dout_a[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END dout_a[43] + PIN dout_a[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END dout_a[44] + PIN dout_a[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END dout_a[45] + PIN dout_a[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END dout_a[46] + PIN dout_a[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END dout_a[47] + PIN dout_a[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END dout_a[48] + PIN dout_a[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END dout_a[49] + PIN dout_a[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END dout_a[50] + PIN dout_a[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END dout_a[51] + PIN dout_a[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END dout_a[52] + PIN dout_a[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END dout_a[53] + PIN dout_a[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END dout_a[54] + PIN dout_a[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END dout_a[55] + PIN dout_a[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END dout_a[56] + PIN dout_a[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END dout_a[57] + PIN dout_a[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END dout_a[58] + PIN dout_a[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END dout_a[59] + PIN dout_a[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END dout_a[60] + PIN dout_a[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END dout_a[61] + PIN dout_a[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END dout_a[62] + PIN dout_a[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END dout_a[63] + PIN dout_a[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.024 9.288 ; + END + END dout_a[64] + PIN dout_a[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.024 9.432 ; + END + END dout_a[65] + PIN dout_a[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END dout_a[66] + PIN dout_a[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.024 9.720 ; + END + END dout_a[67] + PIN dout_a[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.024 9.864 ; + END + END dout_a[68] + PIN dout_a[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.024 10.008 ; + END + END dout_a[69] + PIN dout_a[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.024 10.152 ; + END + END dout_a[70] + PIN dout_a[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.024 10.296 ; + END + END dout_a[71] + PIN dout_a[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END dout_a[72] + PIN dout_a[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.024 10.584 ; + END + END dout_a[73] + PIN dout_a[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.024 10.728 ; + END + END dout_a[74] + PIN dout_a[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.024 10.872 ; + END + END dout_a[75] + PIN dout_a[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.024 11.016 ; + END + END dout_a[76] + PIN dout_a[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END dout_a[77] + PIN dout_a[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.024 11.304 ; + END + END dout_a[78] + PIN dout_a[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.024 11.448 ; + END + END dout_a[79] + PIN dout_a[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.024 11.592 ; + END + END dout_a[80] + PIN dout_a[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.024 11.736 ; + END + END dout_a[81] + PIN dout_a[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END dout_a[82] + PIN dout_a[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.024 12.024 ; + END + END dout_a[83] + PIN dout_a[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.024 12.168 ; + END + END dout_a[84] + PIN dout_a[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.024 12.312 ; + END + END dout_a[85] + PIN dout_a[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.432 0.024 12.456 ; + END + END dout_a[86] + PIN dout_a[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.576 0.024 12.600 ; + END + END dout_a[87] + PIN dout_a[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.720 0.024 12.744 ; + END + END dout_a[88] + PIN dout_a[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.864 0.024 12.888 ; + END + END dout_a[89] + PIN dout_a[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.008 0.024 13.032 ; + END + END dout_a[90] + PIN dout_a[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.152 0.024 13.176 ; + END + END dout_a[91] + PIN dout_a[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.296 0.024 13.320 ; + END + END dout_a[92] + PIN dout_a[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.440 0.024 13.464 ; + END + END dout_a[93] + PIN dout_a[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.584 0.024 13.608 ; + END + END dout_a[94] + PIN dout_a[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.728 0.024 13.752 ; + END + END dout_a[95] + PIN dout_a[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.872 0.024 13.896 ; + END + END dout_a[96] + PIN dout_a[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.016 0.024 14.040 ; + END + END dout_a[97] + PIN dout_a[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.160 0.024 14.184 ; + END + END dout_a[98] + PIN dout_a[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.304 0.024 14.328 ; + END + END dout_a[99] + PIN dout_a[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.448 0.024 14.472 ; + END + END dout_a[100] + PIN dout_a[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.592 0.024 14.616 ; + END + END dout_a[101] + PIN dout_a[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.736 0.024 14.760 ; + END + END dout_a[102] + PIN dout_a[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.880 0.024 14.904 ; + END + END dout_a[103] + PIN dout_a[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.024 0.024 15.048 ; + END + END dout_a[104] + PIN dout_a[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.168 0.024 15.192 ; + END + END dout_a[105] + PIN dout_a[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.312 0.024 15.336 ; + END + END dout_a[106] + PIN dout_a[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.456 0.024 15.480 ; + END + END dout_a[107] + PIN dout_a[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.600 0.024 15.624 ; + END + END dout_a[108] + PIN dout_a[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.744 0.024 15.768 ; + END + END dout_a[109] + PIN dout_a[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.888 0.024 15.912 ; + END + END dout_a[110] + PIN dout_a[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.032 0.024 16.056 ; + END + END dout_a[111] + PIN dout_a[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.176 0.024 16.200 ; + END + END dout_a[112] + PIN dout_a[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.320 0.024 16.344 ; + END + END dout_a[113] + PIN dout_a[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.464 0.024 16.488 ; + END + END dout_a[114] + PIN dout_a[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.608 0.024 16.632 ; + END + END dout_a[115] + PIN dout_a[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.752 0.024 16.776 ; + END + END dout_a[116] + PIN dout_a[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.896 0.024 16.920 ; + END + END dout_a[117] + PIN dout_a[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.040 0.024 17.064 ; + END + END dout_a[118] + PIN dout_a[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.184 0.024 17.208 ; + END + END dout_a[119] + PIN dout_a[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.328 0.024 17.352 ; + END + END dout_a[120] + PIN dout_a[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.472 0.024 17.496 ; + END + END dout_a[121] + PIN dout_a[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.616 0.024 17.640 ; + END + END dout_a[122] + PIN dout_a[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.760 0.024 17.784 ; + END + END dout_a[123] + PIN dout_a[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.904 0.024 17.928 ; + END + END dout_a[124] + PIN dout_a[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.048 0.024 18.072 ; + END + END dout_a[125] + PIN dout_a[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.192 0.024 18.216 ; + END + END dout_a[126] + PIN dout_a[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.336 0.024 18.360 ; + END + END dout_a[127] + PIN dout_a[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.480 0.024 18.504 ; + END + END dout_a[128] + PIN dout_a[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.624 0.024 18.648 ; + END + END dout_a[129] + PIN dout_a[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.768 0.024 18.792 ; + END + END dout_a[130] + PIN dout_a[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.912 0.024 18.936 ; + END + END dout_a[131] + PIN dout_a[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.056 0.024 19.080 ; + END + END dout_a[132] + PIN dout_a[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.200 0.024 19.224 ; + END + END dout_a[133] + PIN dout_a[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.344 0.024 19.368 ; + END + END dout_a[134] + PIN dout_a[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.488 0.024 19.512 ; + END + END dout_a[135] + PIN dout_a[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.632 0.024 19.656 ; + END + END dout_a[136] + PIN dout_a[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.776 0.024 19.800 ; + END + END dout_a[137] + PIN dout_a[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.920 0.024 19.944 ; + END + END dout_a[138] + PIN dout_a[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.024 20.088 ; + END + END dout_a[139] + PIN dout_a[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.208 0.024 20.232 ; + END + END dout_a[140] + PIN dout_a[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.352 0.024 20.376 ; + END + END dout_a[141] + PIN dout_a[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.496 0.024 20.520 ; + END + END dout_a[142] + PIN dout_a[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.640 0.024 20.664 ; + END + END dout_a[143] + PIN dout_a[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.024 20.808 ; + END + END dout_a[144] + PIN dout_a[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.928 0.024 20.952 ; + END + END dout_a[145] + PIN dout_a[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.024 21.096 ; + END + END dout_a[146] + PIN dout_a[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.024 21.240 ; + END + END dout_a[147] + PIN dout_a[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.024 21.384 ; + END + END dout_a[148] + PIN dout_a[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.024 21.528 ; + END + END dout_a[149] + PIN dout_a[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.648 0.024 21.672 ; + END + END dout_a[150] + PIN dout_a[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.792 0.024 21.816 ; + END + END dout_a[151] + PIN dout_a[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.024 21.960 ; + END + END dout_a[152] + PIN dout_a[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.080 0.024 22.104 ; + END + END dout_a[153] + PIN dout_a[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.224 0.024 22.248 ; + END + END dout_a[154] + PIN dout_a[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.368 0.024 22.392 ; + END + END dout_a[155] + PIN dout_a[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.512 0.024 22.536 ; + END + END dout_a[156] + PIN dout_a[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.656 0.024 22.680 ; + END + END dout_a[157] + PIN dout_a[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.800 0.024 22.824 ; + END + END dout_a[158] + PIN dout_a[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.944 0.024 22.968 ; + END + END dout_a[159] + PIN dout_a[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.088 0.024 23.112 ; + END + END dout_a[160] + PIN dout_a[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.232 0.024 23.256 ; + END + END dout_a[161] + PIN dout_a[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.376 0.024 23.400 ; + END + END dout_a[162] + PIN dout_a[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.520 0.024 23.544 ; + END + END dout_a[163] + PIN dout_a[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.024 23.688 ; + END + END dout_a[164] + PIN dout_a[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.024 23.832 ; + END + END dout_a[165] + PIN dout_a[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.024 23.976 ; + END + END dout_a[166] + PIN dout_a[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.024 24.120 ; + END + END dout_a[167] + PIN dout_a[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.024 24.264 ; + END + END dout_a[168] + PIN dout_a[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.024 24.408 ; + END + END dout_a[169] + PIN dout_a[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.024 24.552 ; + END + END dout_a[170] + PIN dout_a[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.024 24.696 ; + END + END dout_a[171] + PIN dout_a[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.024 24.840 ; + END + END dout_a[172] + PIN dout_a[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.024 24.984 ; + END + END dout_a[173] + PIN dout_a[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.024 25.128 ; + END + END dout_a[174] + PIN dout_a[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.024 25.272 ; + END + END dout_a[175] + PIN dout_a[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END dout_a[176] + PIN dout_a[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.024 25.560 ; + END + END dout_a[177] + PIN dout_a[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.024 25.704 ; + END + END dout_a[178] + PIN dout_a[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.024 25.848 ; + END + END dout_a[179] + PIN dout_a[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.024 25.992 ; + END + END dout_a[180] + PIN dout_a[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.024 26.136 ; + END + END dout_a[181] + PIN dout_a[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.024 26.280 ; + END + END dout_a[182] + PIN dout_a[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.024 26.424 ; + END + END dout_a[183] + PIN dout_a[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.024 26.568 ; + END + END dout_a[184] + PIN dout_a[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.024 26.712 ; + END + END dout_a[185] + PIN dout_a[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END dout_a[186] + PIN dout_a[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.024 27.000 ; + END + END dout_a[187] + PIN dout_a[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.024 27.144 ; + END + END dout_a[188] + PIN dout_a[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.024 27.288 ; + END + END dout_a[189] + PIN dout_a[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.024 27.432 ; + END + END dout_a[190] + PIN dout_a[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.024 27.576 ; + END + END dout_a[191] + PIN dout_a[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.024 27.720 ; + END + END dout_a[192] + PIN dout_a[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.024 27.864 ; + END + END dout_a[193] + PIN dout_a[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.024 28.008 ; + END + END dout_a[194] + PIN dout_a[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.024 28.152 ; + END + END dout_a[195] + PIN dout_a[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END dout_a[196] + PIN dout_a[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.024 28.440 ; + END + END dout_a[197] + PIN dout_a[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.024 28.584 ; + END + END dout_a[198] + PIN dout_a[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.024 28.728 ; + END + END dout_a[199] + PIN dout_a[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.024 28.872 ; + END + END dout_a[200] + PIN dout_a[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.024 29.016 ; + END + END dout_a[201] + PIN dout_a[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.024 29.160 ; + END + END dout_a[202] + PIN dout_a[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.024 29.304 ; + END + END dout_a[203] + PIN dout_a[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.024 29.448 ; + END + END dout_a[204] + PIN dout_a[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.024 29.592 ; + END + END dout_a[205] + PIN dout_a[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.024 29.736 ; + END + END dout_a[206] + PIN dout_a[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.024 29.880 ; + END + END dout_a[207] + PIN dout_a[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.024 30.024 ; + END + END dout_a[208] + PIN dout_a[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.024 30.168 ; + END + END dout_a[209] + PIN dout_a[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.024 30.312 ; + END + END dout_a[210] + PIN dout_a[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.024 30.456 ; + END + END dout_a[211] + PIN dout_a[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.024 30.600 ; + END + END dout_a[212] + PIN dout_a[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.024 30.744 ; + END + END dout_a[213] + PIN dout_a[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.024 30.888 ; + END + END dout_a[214] + PIN dout_a[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.024 31.032 ; + END + END dout_a[215] + PIN dout_a[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END dout_a[216] + PIN dout_a[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.024 31.320 ; + END + END dout_a[217] + PIN dout_a[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.024 31.464 ; + END + END dout_a[218] + PIN dout_a[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.024 31.608 ; + END + END dout_a[219] + PIN dout_a[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.024 31.752 ; + END + END dout_a[220] + PIN dout_a[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.872 0.024 31.896 ; + END + END dout_a[221] + PIN dout_a[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.016 0.024 32.040 ; + END + END dout_a[222] + PIN dout_a[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.160 0.024 32.184 ; + END + END dout_a[223] + PIN dout_a[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.304 0.024 32.328 ; + END + END dout_a[224] + PIN dout_a[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.448 0.024 32.472 ; + END + END dout_a[225] + PIN dout_a[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.592 0.024 32.616 ; + END + END dout_a[226] + PIN dout_a[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.736 0.024 32.760 ; + END + END dout_a[227] + PIN dout_a[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.880 0.024 32.904 ; + END + END dout_a[228] + PIN dout_a[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.024 0.024 33.048 ; + END + END dout_a[229] + PIN dout_a[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.168 0.024 33.192 ; + END + END dout_a[230] + PIN dout_a[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.312 0.024 33.336 ; + END + END dout_a[231] + PIN dout_a[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.456 0.024 33.480 ; + END + END dout_a[232] + PIN dout_a[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.600 0.024 33.624 ; + END + END dout_a[233] + PIN dout_a[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.744 0.024 33.768 ; + END + END dout_a[234] + PIN dout_a[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.888 0.024 33.912 ; + END + END dout_a[235] + PIN dout_a[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.032 0.024 34.056 ; + END + END dout_a[236] + PIN dout_a[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.176 0.024 34.200 ; + END + END dout_a[237] + PIN dout_a[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.320 0.024 34.344 ; + END + END dout_a[238] + PIN dout_a[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.464 0.024 34.488 ; + END + END dout_a[239] + PIN dout_a[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.608 0.024 34.632 ; + END + END dout_a[240] + PIN dout_a[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.752 0.024 34.776 ; + END + END dout_a[241] + PIN dout_a[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.896 0.024 34.920 ; + END + END dout_a[242] + PIN dout_a[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.040 0.024 35.064 ; + END + END dout_a[243] + PIN dout_a[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.184 0.024 35.208 ; + END + END dout_a[244] + PIN dout_a[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.328 0.024 35.352 ; + END + END dout_a[245] + PIN dout_a[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.472 0.024 35.496 ; + END + END dout_a[246] + PIN dout_a[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.616 0.024 35.640 ; + END + END dout_a[247] + PIN dout_a[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END dout_a[248] + PIN dout_a[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.904 0.024 35.928 ; + END + END dout_a[249] + PIN dout_a[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.048 0.024 36.072 ; + END + END dout_a[250] + PIN dout_a[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.192 0.024 36.216 ; + END + END dout_a[251] + PIN dout_a[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.336 0.024 36.360 ; + END + END dout_a[252] + PIN dout_a[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.480 0.024 36.504 ; + END + END dout_a[253] + PIN dout_a[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.624 0.024 36.648 ; + END + END dout_a[254] + PIN dout_a[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.768 0.024 36.792 ; + END + END dout_a[255] + PIN din_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.792 0.024 39.816 ; + END + END din_a[0] + PIN din_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.936 0.024 39.960 ; + END + END din_a[1] + PIN din_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.080 0.024 40.104 ; + END + END din_a[2] + PIN din_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.224 0.024 40.248 ; + END + END din_a[3] + PIN din_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.368 0.024 40.392 ; + END + END din_a[4] + PIN din_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.512 0.024 40.536 ; + END + END din_a[5] + PIN din_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.656 0.024 40.680 ; + END + END din_a[6] + PIN din_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.800 0.024 40.824 ; + END + END din_a[7] + PIN din_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.944 0.024 40.968 ; + END + END din_a[8] + PIN din_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.088 0.024 41.112 ; + END + END din_a[9] + PIN din_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.232 0.024 41.256 ; + END + END din_a[10] + PIN din_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.376 0.024 41.400 ; + END + END din_a[11] + PIN din_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.520 0.024 41.544 ; + END + END din_a[12] + PIN din_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.664 0.024 41.688 ; + END + END din_a[13] + PIN din_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.808 0.024 41.832 ; + END + END din_a[14] + PIN din_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.952 0.024 41.976 ; + END + END din_a[15] + PIN din_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.096 0.024 42.120 ; + END + END din_a[16] + PIN din_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.240 0.024 42.264 ; + END + END din_a[17] + PIN din_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.384 0.024 42.408 ; + END + END din_a[18] + PIN din_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.528 0.024 42.552 ; + END + END din_a[19] + PIN din_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.672 0.024 42.696 ; + END + END din_a[20] + PIN din_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.816 0.024 42.840 ; + END + END din_a[21] + PIN din_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.960 0.024 42.984 ; + END + END din_a[22] + PIN din_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.104 0.024 43.128 ; + END + END din_a[23] + PIN din_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.248 0.024 43.272 ; + END + END din_a[24] + PIN din_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.392 0.024 43.416 ; + END + END din_a[25] + PIN din_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.536 0.024 43.560 ; + END + END din_a[26] + PIN din_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.680 0.024 43.704 ; + END + END din_a[27] + PIN din_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.824 0.024 43.848 ; + END + END din_a[28] + PIN din_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.968 0.024 43.992 ; + END + END din_a[29] + PIN din_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.112 0.024 44.136 ; + END + END din_a[30] + PIN din_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.256 0.024 44.280 ; + END + END din_a[31] + PIN din_a[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.400 0.024 44.424 ; + END + END din_a[32] + PIN din_a[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.544 0.024 44.568 ; + END + END din_a[33] + PIN din_a[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.688 0.024 44.712 ; + END + END din_a[34] + PIN din_a[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.832 0.024 44.856 ; + END + END din_a[35] + PIN din_a[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.976 0.024 45.000 ; + END + END din_a[36] + PIN din_a[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.120 0.024 45.144 ; + END + END din_a[37] + PIN din_a[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.264 0.024 45.288 ; + END + END din_a[38] + PIN din_a[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.408 0.024 45.432 ; + END + END din_a[39] + PIN din_a[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.552 0.024 45.576 ; + END + END din_a[40] + PIN din_a[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.696 0.024 45.720 ; + END + END din_a[41] + PIN din_a[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.840 0.024 45.864 ; + END + END din_a[42] + PIN din_a[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.984 0.024 46.008 ; + END + END din_a[43] + PIN din_a[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.128 0.024 46.152 ; + END + END din_a[44] + PIN din_a[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.272 0.024 46.296 ; + END + END din_a[45] + PIN din_a[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.416 0.024 46.440 ; + END + END din_a[46] + PIN din_a[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.560 0.024 46.584 ; + END + END din_a[47] + PIN din_a[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.704 0.024 46.728 ; + END + END din_a[48] + PIN din_a[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.848 0.024 46.872 ; + END + END din_a[49] + PIN din_a[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.992 0.024 47.016 ; + END + END din_a[50] + PIN din_a[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.136 0.024 47.160 ; + END + END din_a[51] + PIN din_a[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.280 0.024 47.304 ; + END + END din_a[52] + PIN din_a[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.424 0.024 47.448 ; + END + END din_a[53] + PIN din_a[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.568 0.024 47.592 ; + END + END din_a[54] + PIN din_a[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.712 0.024 47.736 ; + END + END din_a[55] + PIN din_a[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.856 0.024 47.880 ; + END + END din_a[56] + PIN din_a[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.000 0.024 48.024 ; + END + END din_a[57] + PIN din_a[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.144 0.024 48.168 ; + END + END din_a[58] + PIN din_a[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.288 0.024 48.312 ; + END + END din_a[59] + PIN din_a[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.432 0.024 48.456 ; + END + END din_a[60] + PIN din_a[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.576 0.024 48.600 ; + END + END din_a[61] + PIN din_a[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.720 0.024 48.744 ; + END + END din_a[62] + PIN din_a[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.864 0.024 48.888 ; + END + END din_a[63] + PIN din_a[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.008 0.024 49.032 ; + END + END din_a[64] + PIN din_a[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.152 0.024 49.176 ; + END + END din_a[65] + PIN din_a[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.296 0.024 49.320 ; + END + END din_a[66] + PIN din_a[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.440 0.024 49.464 ; + END + END din_a[67] + PIN din_a[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.584 0.024 49.608 ; + END + END din_a[68] + PIN din_a[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.728 0.024 49.752 ; + END + END din_a[69] + PIN din_a[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.872 0.024 49.896 ; + END + END din_a[70] + PIN din_a[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.016 0.024 50.040 ; + END + END din_a[71] + PIN din_a[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.160 0.024 50.184 ; + END + END din_a[72] + PIN din_a[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.304 0.024 50.328 ; + END + END din_a[73] + PIN din_a[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.448 0.024 50.472 ; + END + END din_a[74] + PIN din_a[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.592 0.024 50.616 ; + END + END din_a[75] + PIN din_a[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.736 0.024 50.760 ; + END + END din_a[76] + PIN din_a[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.880 0.024 50.904 ; + END + END din_a[77] + PIN din_a[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.024 0.024 51.048 ; + END + END din_a[78] + PIN din_a[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.168 0.024 51.192 ; + END + END din_a[79] + PIN din_a[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.312 0.024 51.336 ; + END + END din_a[80] + PIN din_a[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.456 0.024 51.480 ; + END + END din_a[81] + PIN din_a[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.600 0.024 51.624 ; + END + END din_a[82] + PIN din_a[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.744 0.024 51.768 ; + END + END din_a[83] + PIN din_a[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.888 0.024 51.912 ; + END + END din_a[84] + PIN din_a[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.032 0.024 52.056 ; + END + END din_a[85] + PIN din_a[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.176 0.024 52.200 ; + END + END din_a[86] + PIN din_a[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.320 0.024 52.344 ; + END + END din_a[87] + PIN din_a[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.464 0.024 52.488 ; + END + END din_a[88] + PIN din_a[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.608 0.024 52.632 ; + END + END din_a[89] + PIN din_a[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.752 0.024 52.776 ; + END + END din_a[90] + PIN din_a[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.896 0.024 52.920 ; + END + END din_a[91] + PIN din_a[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.040 0.024 53.064 ; + END + END din_a[92] + PIN din_a[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.184 0.024 53.208 ; + END + END din_a[93] + PIN din_a[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.328 0.024 53.352 ; + END + END din_a[94] + PIN din_a[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.472 0.024 53.496 ; + END + END din_a[95] + PIN din_a[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.616 0.024 53.640 ; + END + END din_a[96] + PIN din_a[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.760 0.024 53.784 ; + END + END din_a[97] + PIN din_a[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.904 0.024 53.928 ; + END + END din_a[98] + PIN din_a[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.048 0.024 54.072 ; + END + END din_a[99] + PIN din_a[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.192 0.024 54.216 ; + END + END din_a[100] + PIN din_a[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.336 0.024 54.360 ; + END + END din_a[101] + PIN din_a[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.480 0.024 54.504 ; + END + END din_a[102] + PIN din_a[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.624 0.024 54.648 ; + END + END din_a[103] + PIN din_a[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.768 0.024 54.792 ; + END + END din_a[104] + PIN din_a[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.912 0.024 54.936 ; + END + END din_a[105] + PIN din_a[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.056 0.024 55.080 ; + END + END din_a[106] + PIN din_a[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.200 0.024 55.224 ; + END + END din_a[107] + PIN din_a[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.344 0.024 55.368 ; + END + END din_a[108] + PIN din_a[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.488 0.024 55.512 ; + END + END din_a[109] + PIN din_a[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.632 0.024 55.656 ; + END + END din_a[110] + PIN din_a[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.776 0.024 55.800 ; + END + END din_a[111] + PIN din_a[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.920 0.024 55.944 ; + END + END din_a[112] + PIN din_a[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.064 0.024 56.088 ; + END + END din_a[113] + PIN din_a[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.208 0.024 56.232 ; + END + END din_a[114] + PIN din_a[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.352 0.024 56.376 ; + END + END din_a[115] + PIN din_a[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.496 0.024 56.520 ; + END + END din_a[116] + PIN din_a[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.640 0.024 56.664 ; + END + END din_a[117] + PIN din_a[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.784 0.024 56.808 ; + END + END din_a[118] + PIN din_a[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.928 0.024 56.952 ; + END + END din_a[119] + PIN din_a[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.072 0.024 57.096 ; + END + END din_a[120] + PIN din_a[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.216 0.024 57.240 ; + END + END din_a[121] + PIN din_a[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.360 0.024 57.384 ; + END + END din_a[122] + PIN din_a[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.504 0.024 57.528 ; + END + END din_a[123] + PIN din_a[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.648 0.024 57.672 ; + END + END din_a[124] + PIN din_a[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.792 0.024 57.816 ; + END + END din_a[125] + PIN din_a[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.936 0.024 57.960 ; + END + END din_a[126] + PIN din_a[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.080 0.024 58.104 ; + END + END din_a[127] + PIN din_a[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.224 0.024 58.248 ; + END + END din_a[128] + PIN din_a[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.368 0.024 58.392 ; + END + END din_a[129] + PIN din_a[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.512 0.024 58.536 ; + END + END din_a[130] + PIN din_a[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.656 0.024 58.680 ; + END + END din_a[131] + PIN din_a[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.800 0.024 58.824 ; + END + END din_a[132] + PIN din_a[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.944 0.024 58.968 ; + END + END din_a[133] + PIN din_a[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.088 0.024 59.112 ; + END + END din_a[134] + PIN din_a[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.232 0.024 59.256 ; + END + END din_a[135] + PIN din_a[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.376 0.024 59.400 ; + END + END din_a[136] + PIN din_a[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.520 0.024 59.544 ; + END + END din_a[137] + PIN din_a[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.664 0.024 59.688 ; + END + END din_a[138] + PIN din_a[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.808 0.024 59.832 ; + END + END din_a[139] + PIN din_a[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.952 0.024 59.976 ; + END + END din_a[140] + PIN din_a[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.096 0.024 60.120 ; + END + END din_a[141] + PIN din_a[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.240 0.024 60.264 ; + END + END din_a[142] + PIN din_a[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.384 0.024 60.408 ; + END + END din_a[143] + PIN din_a[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.528 0.024 60.552 ; + END + END din_a[144] + PIN din_a[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.672 0.024 60.696 ; + END + END din_a[145] + PIN din_a[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.816 0.024 60.840 ; + END + END din_a[146] + PIN din_a[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.960 0.024 60.984 ; + END + END din_a[147] + PIN din_a[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.104 0.024 61.128 ; + END + END din_a[148] + PIN din_a[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.248 0.024 61.272 ; + END + END din_a[149] + PIN din_a[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.392 0.024 61.416 ; + END + END din_a[150] + PIN din_a[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.536 0.024 61.560 ; + END + END din_a[151] + PIN din_a[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.680 0.024 61.704 ; + END + END din_a[152] + PIN din_a[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.824 0.024 61.848 ; + END + END din_a[153] + PIN din_a[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.968 0.024 61.992 ; + END + END din_a[154] + PIN din_a[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.112 0.024 62.136 ; + END + END din_a[155] + PIN din_a[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.256 0.024 62.280 ; + END + END din_a[156] + PIN din_a[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.400 0.024 62.424 ; + END + END din_a[157] + PIN din_a[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.544 0.024 62.568 ; + END + END din_a[158] + PIN din_a[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.688 0.024 62.712 ; + END + END din_a[159] + PIN din_a[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.832 0.024 62.856 ; + END + END din_a[160] + PIN din_a[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.976 0.024 63.000 ; + END + END din_a[161] + PIN din_a[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.120 0.024 63.144 ; + END + END din_a[162] + PIN din_a[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.264 0.024 63.288 ; + END + END din_a[163] + PIN din_a[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.408 0.024 63.432 ; + END + END din_a[164] + PIN din_a[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.552 0.024 63.576 ; + END + END din_a[165] + PIN din_a[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.696 0.024 63.720 ; + END + END din_a[166] + PIN din_a[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.840 0.024 63.864 ; + END + END din_a[167] + PIN din_a[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.984 0.024 64.008 ; + END + END din_a[168] + PIN din_a[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.128 0.024 64.152 ; + END + END din_a[169] + PIN din_a[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.272 0.024 64.296 ; + END + END din_a[170] + PIN din_a[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.416 0.024 64.440 ; + END + END din_a[171] + PIN din_a[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.560 0.024 64.584 ; + END + END din_a[172] + PIN din_a[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.704 0.024 64.728 ; + END + END din_a[173] + PIN din_a[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.848 0.024 64.872 ; + END + END din_a[174] + PIN din_a[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.992 0.024 65.016 ; + END + END din_a[175] + PIN din_a[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.136 0.024 65.160 ; + END + END din_a[176] + PIN din_a[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.280 0.024 65.304 ; + END + END din_a[177] + PIN din_a[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.424 0.024 65.448 ; + END + END din_a[178] + PIN din_a[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.568 0.024 65.592 ; + END + END din_a[179] + PIN din_a[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.712 0.024 65.736 ; + END + END din_a[180] + PIN din_a[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.856 0.024 65.880 ; + END + END din_a[181] + PIN din_a[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.000 0.024 66.024 ; + END + END din_a[182] + PIN din_a[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.144 0.024 66.168 ; + END + END din_a[183] + PIN din_a[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.288 0.024 66.312 ; + END + END din_a[184] + PIN din_a[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.432 0.024 66.456 ; + END + END din_a[185] + PIN din_a[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.576 0.024 66.600 ; + END + END din_a[186] + PIN din_a[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.720 0.024 66.744 ; + END + END din_a[187] + PIN din_a[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.864 0.024 66.888 ; + END + END din_a[188] + PIN din_a[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.008 0.024 67.032 ; + END + END din_a[189] + PIN din_a[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.152 0.024 67.176 ; + END + END din_a[190] + PIN din_a[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.296 0.024 67.320 ; + END + END din_a[191] + PIN din_a[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.440 0.024 67.464 ; + END + END din_a[192] + PIN din_a[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.584 0.024 67.608 ; + END + END din_a[193] + PIN din_a[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.728 0.024 67.752 ; + END + END din_a[194] + PIN din_a[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.872 0.024 67.896 ; + END + END din_a[195] + PIN din_a[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.016 0.024 68.040 ; + END + END din_a[196] + PIN din_a[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.160 0.024 68.184 ; + END + END din_a[197] + PIN din_a[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.304 0.024 68.328 ; + END + END din_a[198] + PIN din_a[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.448 0.024 68.472 ; + END + END din_a[199] + PIN din_a[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.592 0.024 68.616 ; + END + END din_a[200] + PIN din_a[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.736 0.024 68.760 ; + END + END din_a[201] + PIN din_a[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.880 0.024 68.904 ; + END + END din_a[202] + PIN din_a[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.024 0.024 69.048 ; + END + END din_a[203] + PIN din_a[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.168 0.024 69.192 ; + END + END din_a[204] + PIN din_a[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.312 0.024 69.336 ; + END + END din_a[205] + PIN din_a[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.456 0.024 69.480 ; + END + END din_a[206] + PIN din_a[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.600 0.024 69.624 ; + END + END din_a[207] + PIN din_a[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.744 0.024 69.768 ; + END + END din_a[208] + PIN din_a[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.888 0.024 69.912 ; + END + END din_a[209] + PIN din_a[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.032 0.024 70.056 ; + END + END din_a[210] + PIN din_a[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.176 0.024 70.200 ; + END + END din_a[211] + PIN din_a[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.320 0.024 70.344 ; + END + END din_a[212] + PIN din_a[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.464 0.024 70.488 ; + END + END din_a[213] + PIN din_a[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.608 0.024 70.632 ; + END + END din_a[214] + PIN din_a[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.752 0.024 70.776 ; + END + END din_a[215] + PIN din_a[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.896 0.024 70.920 ; + END + END din_a[216] + PIN din_a[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.040 0.024 71.064 ; + END + END din_a[217] + PIN din_a[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.184 0.024 71.208 ; + END + END din_a[218] + PIN din_a[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.328 0.024 71.352 ; + END + END din_a[219] + PIN din_a[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.472 0.024 71.496 ; + END + END din_a[220] + PIN din_a[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.616 0.024 71.640 ; + END + END din_a[221] + PIN din_a[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.760 0.024 71.784 ; + END + END din_a[222] + PIN din_a[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.904 0.024 71.928 ; + END + END din_a[223] + PIN din_a[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.048 0.024 72.072 ; + END + END din_a[224] + PIN din_a[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.192 0.024 72.216 ; + END + END din_a[225] + PIN din_a[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.336 0.024 72.360 ; + END + END din_a[226] + PIN din_a[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.480 0.024 72.504 ; + END + END din_a[227] + PIN din_a[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.624 0.024 72.648 ; + END + END din_a[228] + PIN din_a[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.768 0.024 72.792 ; + END + END din_a[229] + PIN din_a[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.912 0.024 72.936 ; + END + END din_a[230] + PIN din_a[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.056 0.024 73.080 ; + END + END din_a[231] + PIN din_a[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.200 0.024 73.224 ; + END + END din_a[232] + PIN din_a[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.344 0.024 73.368 ; + END + END din_a[233] + PIN din_a[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.488 0.024 73.512 ; + END + END din_a[234] + PIN din_a[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.632 0.024 73.656 ; + END + END din_a[235] + PIN din_a[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.776 0.024 73.800 ; + END + END din_a[236] + PIN din_a[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.920 0.024 73.944 ; + END + END din_a[237] + PIN din_a[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.064 0.024 74.088 ; + END + END din_a[238] + PIN din_a[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.208 0.024 74.232 ; + END + END din_a[239] + PIN din_a[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.352 0.024 74.376 ; + END + END din_a[240] + PIN din_a[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.496 0.024 74.520 ; + END + END din_a[241] + PIN din_a[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.640 0.024 74.664 ; + END + END din_a[242] + PIN din_a[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.784 0.024 74.808 ; + END + END din_a[243] + PIN din_a[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.928 0.024 74.952 ; + END + END din_a[244] + PIN din_a[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.072 0.024 75.096 ; + END + END din_a[245] + PIN din_a[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.216 0.024 75.240 ; + END + END din_a[246] + PIN din_a[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.360 0.024 75.384 ; + END + END din_a[247] + PIN din_a[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.504 0.024 75.528 ; + END + END din_a[248] + PIN din_a[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.648 0.024 75.672 ; + END + END din_a[249] + PIN din_a[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.792 0.024 75.816 ; + END + END din_a[250] + PIN din_a[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.936 0.024 75.960 ; + END + END din_a[251] + PIN din_a[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.080 0.024 76.104 ; + END + END din_a[252] + PIN din_a[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.224 0.024 76.248 ; + END + END din_a[253] + PIN din_a[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.368 0.024 76.392 ; + END + END din_a[254] + PIN din_a[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.512 0.024 76.536 ; + END + END din_a[255] + PIN addr_a[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.536 0.024 79.560 ; + END + END addr_a[0] + PIN addr_a[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.680 0.024 79.704 ; + END + END addr_a[1] + PIN addr_a[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.824 0.024 79.848 ; + END + END addr_a[2] + PIN addr_a[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.968 0.024 79.992 ; + END + END addr_a[3] + PIN addr_a[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.112 0.024 80.136 ; + END + END addr_a[4] + PIN addr_a[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.256 0.024 80.280 ; + END + END addr_a[5] + PIN addr_a[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.400 0.024 80.424 ; + END + END addr_a[6] + PIN addr_a[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.544 0.024 80.568 ; + END + END addr_a[7] + PIN we_a + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.568 0.024 83.592 ; + END + END we_a + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.712 0.024 83.736 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 33.202 0.096 ; + RECT 0.048 0.768 33.202 0.864 ; + RECT 0.048 1.536 33.202 1.632 ; + RECT 0.048 2.304 33.202 2.400 ; + RECT 0.048 3.072 33.202 3.168 ; + RECT 0.048 3.840 33.202 3.936 ; + RECT 0.048 4.608 33.202 4.704 ; + RECT 0.048 5.376 33.202 5.472 ; + RECT 0.048 6.144 33.202 6.240 ; + RECT 0.048 6.912 33.202 7.008 ; + RECT 0.048 7.680 33.202 7.776 ; + RECT 0.048 8.448 33.202 8.544 ; + RECT 0.048 9.216 33.202 9.312 ; + RECT 0.048 9.984 33.202 10.080 ; + RECT 0.048 10.752 33.202 10.848 ; + RECT 0.048 11.520 33.202 11.616 ; + RECT 0.048 12.288 33.202 12.384 ; + RECT 0.048 13.056 33.202 13.152 ; + RECT 0.048 13.824 33.202 13.920 ; + RECT 0.048 14.592 33.202 14.688 ; + RECT 0.048 15.360 33.202 15.456 ; + RECT 0.048 16.128 33.202 16.224 ; + RECT 0.048 16.896 33.202 16.992 ; + RECT 0.048 17.664 33.202 17.760 ; + RECT 0.048 18.432 33.202 18.528 ; + RECT 0.048 19.200 33.202 19.296 ; + RECT 0.048 19.968 33.202 20.064 ; + RECT 0.048 20.736 33.202 20.832 ; + RECT 0.048 21.504 33.202 21.600 ; + RECT 0.048 22.272 33.202 22.368 ; + RECT 0.048 23.040 33.202 23.136 ; + RECT 0.048 23.808 33.202 23.904 ; + RECT 0.048 24.576 33.202 24.672 ; + RECT 0.048 25.344 33.202 25.440 ; + RECT 0.048 26.112 33.202 26.208 ; + RECT 0.048 26.880 33.202 26.976 ; + RECT 0.048 27.648 33.202 27.744 ; + RECT 0.048 28.416 33.202 28.512 ; + RECT 0.048 29.184 33.202 29.280 ; + RECT 0.048 29.952 33.202 30.048 ; + RECT 0.048 30.720 33.202 30.816 ; + RECT 0.048 31.488 33.202 31.584 ; + RECT 0.048 32.256 33.202 32.352 ; + RECT 0.048 33.024 33.202 33.120 ; + RECT 0.048 33.792 33.202 33.888 ; + RECT 0.048 34.560 33.202 34.656 ; + RECT 0.048 35.328 33.202 35.424 ; + RECT 0.048 36.096 33.202 36.192 ; + RECT 0.048 36.864 33.202 36.960 ; + RECT 0.048 37.632 33.202 37.728 ; + RECT 0.048 38.400 33.202 38.496 ; + RECT 0.048 39.168 33.202 39.264 ; + RECT 0.048 39.936 33.202 40.032 ; + RECT 0.048 40.704 33.202 40.800 ; + RECT 0.048 41.472 33.202 41.568 ; + RECT 0.048 42.240 33.202 42.336 ; + RECT 0.048 43.008 33.202 43.104 ; + RECT 0.048 43.776 33.202 43.872 ; + RECT 0.048 44.544 33.202 44.640 ; + RECT 0.048 45.312 33.202 45.408 ; + RECT 0.048 46.080 33.202 46.176 ; + RECT 0.048 46.848 33.202 46.944 ; + RECT 0.048 47.616 33.202 47.712 ; + RECT 0.048 48.384 33.202 48.480 ; + RECT 0.048 49.152 33.202 49.248 ; + RECT 0.048 49.920 33.202 50.016 ; + RECT 0.048 50.688 33.202 50.784 ; + RECT 0.048 51.456 33.202 51.552 ; + RECT 0.048 52.224 33.202 52.320 ; + RECT 0.048 52.992 33.202 53.088 ; + RECT 0.048 53.760 33.202 53.856 ; + RECT 0.048 54.528 33.202 54.624 ; + RECT 0.048 55.296 33.202 55.392 ; + RECT 0.048 56.064 33.202 56.160 ; + RECT 0.048 56.832 33.202 56.928 ; + RECT 0.048 57.600 33.202 57.696 ; + RECT 0.048 58.368 33.202 58.464 ; + RECT 0.048 59.136 33.202 59.232 ; + RECT 0.048 59.904 33.202 60.000 ; + RECT 0.048 60.672 33.202 60.768 ; + RECT 0.048 61.440 33.202 61.536 ; + RECT 0.048 62.208 33.202 62.304 ; + RECT 0.048 62.976 33.202 63.072 ; + RECT 0.048 63.744 33.202 63.840 ; + RECT 0.048 64.512 33.202 64.608 ; + RECT 0.048 65.280 33.202 65.376 ; + RECT 0.048 66.048 33.202 66.144 ; + RECT 0.048 66.816 33.202 66.912 ; + RECT 0.048 67.584 33.202 67.680 ; + RECT 0.048 68.352 33.202 68.448 ; + RECT 0.048 69.120 33.202 69.216 ; + RECT 0.048 69.888 33.202 69.984 ; + RECT 0.048 70.656 33.202 70.752 ; + RECT 0.048 71.424 33.202 71.520 ; + RECT 0.048 72.192 33.202 72.288 ; + RECT 0.048 72.960 33.202 73.056 ; + RECT 0.048 73.728 33.202 73.824 ; + RECT 0.048 74.496 33.202 74.592 ; + RECT 0.048 75.264 33.202 75.360 ; + RECT 0.048 76.032 33.202 76.128 ; + RECT 0.048 76.800 33.202 76.896 ; + RECT 0.048 77.568 33.202 77.664 ; + RECT 0.048 78.336 33.202 78.432 ; + RECT 0.048 79.104 33.202 79.200 ; + RECT 0.048 79.872 33.202 79.968 ; + RECT 0.048 80.640 33.202 80.736 ; + RECT 0.048 81.408 33.202 81.504 ; + RECT 0.048 82.176 33.202 82.272 ; + RECT 0.048 82.944 33.202 83.040 ; + RECT 0.048 83.712 33.202 83.808 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 33.202 0.480 ; + RECT 0.048 1.152 33.202 1.248 ; + RECT 0.048 1.920 33.202 2.016 ; + RECT 0.048 2.688 33.202 2.784 ; + RECT 0.048 3.456 33.202 3.552 ; + RECT 0.048 4.224 33.202 4.320 ; + RECT 0.048 4.992 33.202 5.088 ; + RECT 0.048 5.760 33.202 5.856 ; + RECT 0.048 6.528 33.202 6.624 ; + RECT 0.048 7.296 33.202 7.392 ; + RECT 0.048 8.064 33.202 8.160 ; + RECT 0.048 8.832 33.202 8.928 ; + RECT 0.048 9.600 33.202 9.696 ; + RECT 0.048 10.368 33.202 10.464 ; + RECT 0.048 11.136 33.202 11.232 ; + RECT 0.048 11.904 33.202 12.000 ; + RECT 0.048 12.672 33.202 12.768 ; + RECT 0.048 13.440 33.202 13.536 ; + RECT 0.048 14.208 33.202 14.304 ; + RECT 0.048 14.976 33.202 15.072 ; + RECT 0.048 15.744 33.202 15.840 ; + RECT 0.048 16.512 33.202 16.608 ; + RECT 0.048 17.280 33.202 17.376 ; + RECT 0.048 18.048 33.202 18.144 ; + RECT 0.048 18.816 33.202 18.912 ; + RECT 0.048 19.584 33.202 19.680 ; + RECT 0.048 20.352 33.202 20.448 ; + RECT 0.048 21.120 33.202 21.216 ; + RECT 0.048 21.888 33.202 21.984 ; + RECT 0.048 22.656 33.202 22.752 ; + RECT 0.048 23.424 33.202 23.520 ; + RECT 0.048 24.192 33.202 24.288 ; + RECT 0.048 24.960 33.202 25.056 ; + RECT 0.048 25.728 33.202 25.824 ; + RECT 0.048 26.496 33.202 26.592 ; + RECT 0.048 27.264 33.202 27.360 ; + RECT 0.048 28.032 33.202 28.128 ; + RECT 0.048 28.800 33.202 28.896 ; + RECT 0.048 29.568 33.202 29.664 ; + RECT 0.048 30.336 33.202 30.432 ; + RECT 0.048 31.104 33.202 31.200 ; + RECT 0.048 31.872 33.202 31.968 ; + RECT 0.048 32.640 33.202 32.736 ; + RECT 0.048 33.408 33.202 33.504 ; + RECT 0.048 34.176 33.202 34.272 ; + RECT 0.048 34.944 33.202 35.040 ; + RECT 0.048 35.712 33.202 35.808 ; + RECT 0.048 36.480 33.202 36.576 ; + RECT 0.048 37.248 33.202 37.344 ; + RECT 0.048 38.016 33.202 38.112 ; + RECT 0.048 38.784 33.202 38.880 ; + RECT 0.048 39.552 33.202 39.648 ; + RECT 0.048 40.320 33.202 40.416 ; + RECT 0.048 41.088 33.202 41.184 ; + RECT 0.048 41.856 33.202 41.952 ; + RECT 0.048 42.624 33.202 42.720 ; + RECT 0.048 43.392 33.202 43.488 ; + RECT 0.048 44.160 33.202 44.256 ; + RECT 0.048 44.928 33.202 45.024 ; + RECT 0.048 45.696 33.202 45.792 ; + RECT 0.048 46.464 33.202 46.560 ; + RECT 0.048 47.232 33.202 47.328 ; + RECT 0.048 48.000 33.202 48.096 ; + RECT 0.048 48.768 33.202 48.864 ; + RECT 0.048 49.536 33.202 49.632 ; + RECT 0.048 50.304 33.202 50.400 ; + RECT 0.048 51.072 33.202 51.168 ; + RECT 0.048 51.840 33.202 51.936 ; + RECT 0.048 52.608 33.202 52.704 ; + RECT 0.048 53.376 33.202 53.472 ; + RECT 0.048 54.144 33.202 54.240 ; + RECT 0.048 54.912 33.202 55.008 ; + RECT 0.048 55.680 33.202 55.776 ; + RECT 0.048 56.448 33.202 56.544 ; + RECT 0.048 57.216 33.202 57.312 ; + RECT 0.048 57.984 33.202 58.080 ; + RECT 0.048 58.752 33.202 58.848 ; + RECT 0.048 59.520 33.202 59.616 ; + RECT 0.048 60.288 33.202 60.384 ; + RECT 0.048 61.056 33.202 61.152 ; + RECT 0.048 61.824 33.202 61.920 ; + RECT 0.048 62.592 33.202 62.688 ; + RECT 0.048 63.360 33.202 63.456 ; + RECT 0.048 64.128 33.202 64.224 ; + RECT 0.048 64.896 33.202 64.992 ; + RECT 0.048 65.664 33.202 65.760 ; + RECT 0.048 66.432 33.202 66.528 ; + RECT 0.048 67.200 33.202 67.296 ; + RECT 0.048 67.968 33.202 68.064 ; + RECT 0.048 68.736 33.202 68.832 ; + RECT 0.048 69.504 33.202 69.600 ; + RECT 0.048 70.272 33.202 70.368 ; + RECT 0.048 71.040 33.202 71.136 ; + RECT 0.048 71.808 33.202 71.904 ; + RECT 0.048 72.576 33.202 72.672 ; + RECT 0.048 73.344 33.202 73.440 ; + RECT 0.048 74.112 33.202 74.208 ; + RECT 0.048 74.880 33.202 74.976 ; + RECT 0.048 75.648 33.202 75.744 ; + RECT 0.048 76.416 33.202 76.512 ; + RECT 0.048 77.184 33.202 77.280 ; + RECT 0.048 77.952 33.202 78.048 ; + RECT 0.048 78.720 33.202 78.816 ; + RECT 0.048 79.488 33.202 79.584 ; + RECT 0.048 80.256 33.202 80.352 ; + RECT 0.048 81.024 33.202 81.120 ; + RECT 0.048 81.792 33.202 81.888 ; + RECT 0.048 82.560 33.202 82.656 ; + RECT 0.048 83.328 33.202 83.424 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 84.000 ; + LAYER M2 ; + RECT 0 0 33.250 84.000 ; + LAYER M3 ; + RECT 0 0 33.250 84.000 ; + LAYER M4 ; + RECT 0 0 33.250 84.000 ; + END +END sprf_256x256 + +END LIBRARY +module sprf_256x256 +( + we_a, + addr_a, + din_a, + dout_a, + clk, +); + parameter DATA_WIDTH = 256; + parameter ADDR_WIDTH = 8; + + // Port A + input wire we_a, + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] din_a, + output reg [DATA_WIDTH-1:0] dout_a, + + input wire clk, + + // Memory array: 256 words of 256 bits + reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1]; + + // Synchronous Port A + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= din_a; + end + dout_a <= mem[addr_a]; // Read occurs after write (read-after-write OK) + end + +endmodule +(* blackbox *) +module sprf_256x256 ( + input we_a, + input [7:0] addr_a, + input [255:0] din_a, + output reg [255:0] dout_a, + clk, +); +endmodule +library(sprf_256x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(sprf_256x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(sprf_256x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(sprf_256x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(sprf_256x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(sprf_256x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (sprf_256x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (sprf_256x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(sprf_256x256) { + area : 2751.883; + interface_timing : true; + pin(we_a){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(sprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(sprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_a) { + bus_type : sprf_256x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(sprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(sprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_a) { + bus_type : sprf_256x256_DATA; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(sprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(sprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(sprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(sprf_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_a) { + bus_type : sprf_256x256_DATA; + direction : output; + max_capacitance : 0.500; + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(sprf_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(sprf_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(sprf_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(sprf_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(sprf_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(sprf_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + cell_leakage_power : 128.900; +} + +} diff --git a/test/au/sprf_256x32.au b/test/au/sprf_256x32.au new file mode 100644 index 0000000..a73d357 --- /dev/null +++ b/test/au/sprf_256x32.au @@ -0,0 +1,1181 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO sprf_256x32 + PROPERTY width 32 ; + PROPERTY depth 256 ; + PROPERTY banks 2 ; + FOREIGN sprf_256x32 0 0 ; + SYMMETRY X Y R90 ; + SIZE 8.360 BY 42.000 ; + CLASS BLOCK ; + PIN dout_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END dout_a[0] + PIN dout_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.024 0.600 ; + END + END dout_a[1] + PIN dout_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.024 1.128 ; + END + END dout_a[2] + PIN dout_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END dout_a[3] + PIN dout_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.024 2.184 ; + END + END dout_a[4] + PIN dout_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END dout_a[5] + PIN dout_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END dout_a[6] + PIN dout_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.024 3.768 ; + END + END dout_a[7] + PIN dout_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.272 0.024 4.296 ; + END + END dout_a[8] + PIN dout_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END dout_a[9] + PIN dout_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END dout_a[10] + PIN dout_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.024 5.880 ; + END + END dout_a[11] + PIN dout_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END dout_a[12] + PIN dout_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.912 0.024 6.936 ; + END + END dout_a[13] + PIN dout_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.440 0.024 7.464 ; + END + END dout_a[14] + PIN dout_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END dout_a[15] + PIN dout_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.496 0.024 8.520 ; + END + END dout_a[16] + PIN dout_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.024 0.024 9.048 ; + END + END dout_a[17] + PIN dout_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END dout_a[18] + PIN dout_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.024 10.104 ; + END + END dout_a[19] + PIN dout_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.608 0.024 10.632 ; + END + END dout_a[20] + PIN dout_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END dout_a[21] + PIN dout_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.024 11.688 ; + END + END dout_a[22] + PIN dout_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.192 0.024 12.216 ; + END + END dout_a[23] + PIN dout_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.720 0.024 12.744 ; + END + END dout_a[24] + PIN dout_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.248 0.024 13.272 ; + END + END dout_a[25] + PIN dout_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.776 0.024 13.800 ; + END + END dout_a[26] + PIN dout_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.304 0.024 14.328 ; + END + END dout_a[27] + PIN dout_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.832 0.024 14.856 ; + END + END dout_a[28] + PIN dout_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.360 0.024 15.384 ; + END + END dout_a[29] + PIN dout_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.888 0.024 15.912 ; + END + END dout_a[30] + PIN dout_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.416 0.024 16.440 ; + END + END dout_a[31] + PIN din_a[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.856 0.024 17.880 ; + END + END din_a[0] + PIN din_a[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.384 0.024 18.408 ; + END + END din_a[1] + PIN din_a[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.912 0.024 18.936 ; + END + END din_a[2] + PIN din_a[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.440 0.024 19.464 ; + END + END din_a[3] + PIN din_a[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.968 0.024 19.992 ; + END + END din_a[4] + PIN din_a[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.496 0.024 20.520 ; + END + END din_a[5] + PIN din_a[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.024 0.024 21.048 ; + END + END din_a[6] + PIN din_a[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.552 0.024 21.576 ; + END + END din_a[7] + PIN din_a[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.080 0.024 22.104 ; + END + END din_a[8] + PIN din_a[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.608 0.024 22.632 ; + END + END din_a[9] + PIN din_a[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.136 0.024 23.160 ; + END + END din_a[10] + PIN din_a[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.024 23.688 ; + END + END din_a[11] + PIN din_a[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.024 24.216 ; + END + END din_a[12] + PIN din_a[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.720 0.024 24.744 ; + END + END din_a[13] + PIN din_a[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.024 25.272 ; + END + END din_a[14] + PIN din_a[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.776 0.024 25.800 ; + END + END din_a[15] + PIN din_a[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.304 0.024 26.328 ; + END + END din_a[16] + PIN din_a[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END din_a[17] + PIN din_a[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.360 0.024 27.384 ; + END + END din_a[18] + PIN din_a[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.888 0.024 27.912 ; + END + END din_a[19] + PIN din_a[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.024 28.440 ; + END + END din_a[20] + PIN din_a[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.944 0.024 28.968 ; + END + END din_a[21] + PIN din_a[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.472 0.024 29.496 ; + END + END din_a[22] + PIN din_a[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.024 30.024 ; + END + END din_a[23] + PIN din_a[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.528 0.024 30.552 ; + END + END din_a[24] + PIN din_a[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.056 0.024 31.080 ; + END + END din_a[25] + PIN din_a[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.024 31.608 ; + END + END din_a[26] + PIN din_a[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.112 0.024 32.136 ; + END + END din_a[27] + PIN din_a[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.640 0.024 32.664 ; + END + END din_a[28] + PIN din_a[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.168 0.024 33.192 ; + END + END din_a[29] + PIN din_a[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.696 0.024 33.720 ; + END + END din_a[30] + PIN din_a[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.224 0.024 34.248 ; + END + END din_a[31] + PIN addr_a[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.664 0.024 35.688 ; + END + END addr_a[0] + PIN addr_a[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.192 0.024 36.216 ; + END + END addr_a[1] + PIN addr_a[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.720 0.024 36.744 ; + END + END addr_a[2] + PIN addr_a[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.248 0.024 37.272 ; + END + END addr_a[3] + PIN addr_a[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.776 0.024 37.800 ; + END + END addr_a[4] + PIN addr_a[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.304 0.024 38.328 ; + END + END addr_a[5] + PIN addr_a[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.832 0.024 38.856 ; + END + END addr_a[6] + PIN addr_a[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.360 0.024 39.384 ; + END + END addr_a[7] + PIN we_a + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.800 0.024 40.824 ; + END + END we_a + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.328 0.024 41.352 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 8.312 0.096 ; + RECT 0.048 0.768 8.312 0.864 ; + RECT 0.048 1.536 8.312 1.632 ; + RECT 0.048 2.304 8.312 2.400 ; + RECT 0.048 3.072 8.312 3.168 ; + RECT 0.048 3.840 8.312 3.936 ; + RECT 0.048 4.608 8.312 4.704 ; + RECT 0.048 5.376 8.312 5.472 ; + RECT 0.048 6.144 8.312 6.240 ; + RECT 0.048 6.912 8.312 7.008 ; + RECT 0.048 7.680 8.312 7.776 ; + RECT 0.048 8.448 8.312 8.544 ; + RECT 0.048 9.216 8.312 9.312 ; + RECT 0.048 9.984 8.312 10.080 ; + RECT 0.048 10.752 8.312 10.848 ; + RECT 0.048 11.520 8.312 11.616 ; + RECT 0.048 12.288 8.312 12.384 ; + RECT 0.048 13.056 8.312 13.152 ; + RECT 0.048 13.824 8.312 13.920 ; + RECT 0.048 14.592 8.312 14.688 ; + RECT 0.048 15.360 8.312 15.456 ; + RECT 0.048 16.128 8.312 16.224 ; + RECT 0.048 16.896 8.312 16.992 ; + RECT 0.048 17.664 8.312 17.760 ; + RECT 0.048 18.432 8.312 18.528 ; + RECT 0.048 19.200 8.312 19.296 ; + RECT 0.048 19.968 8.312 20.064 ; + RECT 0.048 20.736 8.312 20.832 ; + RECT 0.048 21.504 8.312 21.600 ; + RECT 0.048 22.272 8.312 22.368 ; + RECT 0.048 23.040 8.312 23.136 ; + RECT 0.048 23.808 8.312 23.904 ; + RECT 0.048 24.576 8.312 24.672 ; + RECT 0.048 25.344 8.312 25.440 ; + RECT 0.048 26.112 8.312 26.208 ; + RECT 0.048 26.880 8.312 26.976 ; + RECT 0.048 27.648 8.312 27.744 ; + RECT 0.048 28.416 8.312 28.512 ; + RECT 0.048 29.184 8.312 29.280 ; + RECT 0.048 29.952 8.312 30.048 ; + RECT 0.048 30.720 8.312 30.816 ; + RECT 0.048 31.488 8.312 31.584 ; + RECT 0.048 32.256 8.312 32.352 ; + RECT 0.048 33.024 8.312 33.120 ; + RECT 0.048 33.792 8.312 33.888 ; + RECT 0.048 34.560 8.312 34.656 ; + RECT 0.048 35.328 8.312 35.424 ; + RECT 0.048 36.096 8.312 36.192 ; + RECT 0.048 36.864 8.312 36.960 ; + RECT 0.048 37.632 8.312 37.728 ; + RECT 0.048 38.400 8.312 38.496 ; + RECT 0.048 39.168 8.312 39.264 ; + RECT 0.048 39.936 8.312 40.032 ; + RECT 0.048 40.704 8.312 40.800 ; + RECT 0.048 41.472 8.312 41.568 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 8.312 0.480 ; + RECT 0.048 1.152 8.312 1.248 ; + RECT 0.048 1.920 8.312 2.016 ; + RECT 0.048 2.688 8.312 2.784 ; + RECT 0.048 3.456 8.312 3.552 ; + RECT 0.048 4.224 8.312 4.320 ; + RECT 0.048 4.992 8.312 5.088 ; + RECT 0.048 5.760 8.312 5.856 ; + RECT 0.048 6.528 8.312 6.624 ; + RECT 0.048 7.296 8.312 7.392 ; + RECT 0.048 8.064 8.312 8.160 ; + RECT 0.048 8.832 8.312 8.928 ; + RECT 0.048 9.600 8.312 9.696 ; + RECT 0.048 10.368 8.312 10.464 ; + RECT 0.048 11.136 8.312 11.232 ; + RECT 0.048 11.904 8.312 12.000 ; + RECT 0.048 12.672 8.312 12.768 ; + RECT 0.048 13.440 8.312 13.536 ; + RECT 0.048 14.208 8.312 14.304 ; + RECT 0.048 14.976 8.312 15.072 ; + RECT 0.048 15.744 8.312 15.840 ; + RECT 0.048 16.512 8.312 16.608 ; + RECT 0.048 17.280 8.312 17.376 ; + RECT 0.048 18.048 8.312 18.144 ; + RECT 0.048 18.816 8.312 18.912 ; + RECT 0.048 19.584 8.312 19.680 ; + RECT 0.048 20.352 8.312 20.448 ; + RECT 0.048 21.120 8.312 21.216 ; + RECT 0.048 21.888 8.312 21.984 ; + RECT 0.048 22.656 8.312 22.752 ; + RECT 0.048 23.424 8.312 23.520 ; + RECT 0.048 24.192 8.312 24.288 ; + RECT 0.048 24.960 8.312 25.056 ; + RECT 0.048 25.728 8.312 25.824 ; + RECT 0.048 26.496 8.312 26.592 ; + RECT 0.048 27.264 8.312 27.360 ; + RECT 0.048 28.032 8.312 28.128 ; + RECT 0.048 28.800 8.312 28.896 ; + RECT 0.048 29.568 8.312 29.664 ; + RECT 0.048 30.336 8.312 30.432 ; + RECT 0.048 31.104 8.312 31.200 ; + RECT 0.048 31.872 8.312 31.968 ; + RECT 0.048 32.640 8.312 32.736 ; + RECT 0.048 33.408 8.312 33.504 ; + RECT 0.048 34.176 8.312 34.272 ; + RECT 0.048 34.944 8.312 35.040 ; + RECT 0.048 35.712 8.312 35.808 ; + RECT 0.048 36.480 8.312 36.576 ; + RECT 0.048 37.248 8.312 37.344 ; + RECT 0.048 38.016 8.312 38.112 ; + RECT 0.048 38.784 8.312 38.880 ; + RECT 0.048 39.552 8.312 39.648 ; + RECT 0.048 40.320 8.312 40.416 ; + RECT 0.048 41.088 8.312 41.184 ; + RECT 0.048 41.856 8.312 41.952 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 8.360 42.000 ; + LAYER M2 ; + RECT 0 0 8.360 42.000 ; + LAYER M3 ; + RECT 0 0 8.360 42.000 ; + LAYER M4 ; + RECT 0 0 8.360 42.000 ; + END +END sprf_256x32 + +END LIBRARY +module sprf_256x32 +( + we_a, + addr_a, + din_a, + dout_a, + clk, +); + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 8; + + // Port A + input wire we_a, + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] din_a, + output reg [DATA_WIDTH-1:0] dout_a, + + input wire clk, + + // Memory array: 256 words of 32 bits + reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1]; + + // Synchronous Port A + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= din_a; + end + dout_a <= mem[addr_a]; // Read occurs after write (read-after-write OK) + end + +endmodule +(* blackbox *) +module sprf_256x32 ( + input we_a, + input [7:0] addr_a, + input [31:0] din_a, + output reg [31:0] dout_a, + clk, +); +endmodule +library(sprf_256x32) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(sprf_256x32_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(sprf_256x32_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(sprf_256x32_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(sprf_256x32_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(sprf_256x32_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (sprf_256x32_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 32; + bit_from : 31; + bit_to : 0 ; + downto : true ; + } + type (sprf_256x32_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(sprf_256x32) { + area : 343.985; + interface_timing : true; + pin(we_a){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(sprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(sprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_a) { + bus_type : sprf_256x32_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(sprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(sprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(din_a) { + bus_type : sprf_256x32_DATA; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(sprf_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(sprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(sprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(sprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(sprf_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(dout_a) { + bus_type : sprf_256x32_DATA; + direction : output; + max_capacitance : 0.500; + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(sprf_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(sprf_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(sprf_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(sprf_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(sprf_256x32_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(sprf_256x32_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + cell_leakage_power : 128.900; +} + +} diff --git a/test/au/spsram_256x256.au b/test/au/spsram_256x256.au new file mode 100644 index 0000000..d85237d --- /dev/null +++ b/test/au/spsram_256x256.au @@ -0,0 +1,5437 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO spsram_256x256 + PROPERTY width 256 ; + PROPERTY depth 256 ; + PROPERTY banks 1 ; + FOREIGN spsram_256x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 84.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END rd_out[63] + PIN rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.024 9.288 ; + END + END rd_out[64] + PIN rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.024 9.432 ; + END + END rd_out[65] + PIN rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END rd_out[66] + PIN rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.024 9.720 ; + END + END rd_out[67] + PIN rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.024 9.864 ; + END + END rd_out[68] + PIN rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.024 10.008 ; + END + END rd_out[69] + PIN rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.024 10.152 ; + END + END rd_out[70] + PIN rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.024 10.296 ; + END + END rd_out[71] + PIN rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END rd_out[72] + PIN rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.024 10.584 ; + END + END rd_out[73] + PIN rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.024 10.728 ; + END + END rd_out[74] + PIN rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.024 10.872 ; + END + END rd_out[75] + PIN rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.024 11.016 ; + END + END rd_out[76] + PIN rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END rd_out[77] + PIN rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.024 11.304 ; + END + END rd_out[78] + PIN rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.024 11.448 ; + END + END rd_out[79] + PIN rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.024 11.592 ; + END + END rd_out[80] + PIN rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.024 11.736 ; + END + END rd_out[81] + PIN rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END rd_out[82] + PIN rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.024 12.024 ; + END + END rd_out[83] + PIN rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.024 12.168 ; + END + END rd_out[84] + PIN rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.024 12.312 ; + END + END rd_out[85] + PIN rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.432 0.024 12.456 ; + END + END rd_out[86] + PIN rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.576 0.024 12.600 ; + END + END rd_out[87] + PIN rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.720 0.024 12.744 ; + END + END rd_out[88] + PIN rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.864 0.024 12.888 ; + END + END rd_out[89] + PIN rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.008 0.024 13.032 ; + END + END rd_out[90] + PIN rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.152 0.024 13.176 ; + END + END rd_out[91] + PIN rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.296 0.024 13.320 ; + END + END rd_out[92] + PIN rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.440 0.024 13.464 ; + END + END rd_out[93] + PIN rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.584 0.024 13.608 ; + END + END rd_out[94] + PIN rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.728 0.024 13.752 ; + END + END rd_out[95] + PIN rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.872 0.024 13.896 ; + END + END rd_out[96] + PIN rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.016 0.024 14.040 ; + END + END rd_out[97] + PIN rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.160 0.024 14.184 ; + END + END rd_out[98] + PIN rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.304 0.024 14.328 ; + END + END rd_out[99] + PIN rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.448 0.024 14.472 ; + END + END rd_out[100] + PIN rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.592 0.024 14.616 ; + END + END rd_out[101] + PIN rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.736 0.024 14.760 ; + END + END rd_out[102] + PIN rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.880 0.024 14.904 ; + END + END rd_out[103] + PIN rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.024 0.024 15.048 ; + END + END rd_out[104] + PIN rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.168 0.024 15.192 ; + END + END rd_out[105] + PIN rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.312 0.024 15.336 ; + END + END rd_out[106] + PIN rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.456 0.024 15.480 ; + END + END rd_out[107] + PIN rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.600 0.024 15.624 ; + END + END rd_out[108] + PIN rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.744 0.024 15.768 ; + END + END rd_out[109] + PIN rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.888 0.024 15.912 ; + END + END rd_out[110] + PIN rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.032 0.024 16.056 ; + END + END rd_out[111] + PIN rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.176 0.024 16.200 ; + END + END rd_out[112] + PIN rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.320 0.024 16.344 ; + END + END rd_out[113] + PIN rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.464 0.024 16.488 ; + END + END rd_out[114] + PIN rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.608 0.024 16.632 ; + END + END rd_out[115] + PIN rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.752 0.024 16.776 ; + END + END rd_out[116] + PIN rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.896 0.024 16.920 ; + END + END rd_out[117] + PIN rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.040 0.024 17.064 ; + END + END rd_out[118] + PIN rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.184 0.024 17.208 ; + END + END rd_out[119] + PIN rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.328 0.024 17.352 ; + END + END rd_out[120] + PIN rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.472 0.024 17.496 ; + END + END rd_out[121] + PIN rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.616 0.024 17.640 ; + END + END rd_out[122] + PIN rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.760 0.024 17.784 ; + END + END rd_out[123] + PIN rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.904 0.024 17.928 ; + END + END rd_out[124] + PIN rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.048 0.024 18.072 ; + END + END rd_out[125] + PIN rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.192 0.024 18.216 ; + END + END rd_out[126] + PIN rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.336 0.024 18.360 ; + END + END rd_out[127] + PIN rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.480 0.024 18.504 ; + END + END rd_out[128] + PIN rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.624 0.024 18.648 ; + END + END rd_out[129] + PIN rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.768 0.024 18.792 ; + END + END rd_out[130] + PIN rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.912 0.024 18.936 ; + END + END rd_out[131] + PIN rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.056 0.024 19.080 ; + END + END rd_out[132] + PIN rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.200 0.024 19.224 ; + END + END rd_out[133] + PIN rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.344 0.024 19.368 ; + END + END rd_out[134] + PIN rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.488 0.024 19.512 ; + END + END rd_out[135] + PIN rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.632 0.024 19.656 ; + END + END rd_out[136] + PIN rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.776 0.024 19.800 ; + END + END rd_out[137] + PIN rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.920 0.024 19.944 ; + END + END rd_out[138] + PIN rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.024 20.088 ; + END + END rd_out[139] + PIN rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.208 0.024 20.232 ; + END + END rd_out[140] + PIN rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.352 0.024 20.376 ; + END + END rd_out[141] + PIN rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.496 0.024 20.520 ; + END + END rd_out[142] + PIN rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.640 0.024 20.664 ; + END + END rd_out[143] + PIN rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.024 20.808 ; + END + END rd_out[144] + PIN rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.928 0.024 20.952 ; + END + END rd_out[145] + PIN rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.024 21.096 ; + END + END rd_out[146] + PIN rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.024 21.240 ; + END + END rd_out[147] + PIN rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.024 21.384 ; + END + END rd_out[148] + PIN rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.024 21.528 ; + END + END rd_out[149] + PIN rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.648 0.024 21.672 ; + END + END rd_out[150] + PIN rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.792 0.024 21.816 ; + END + END rd_out[151] + PIN rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.024 21.960 ; + END + END rd_out[152] + PIN rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.080 0.024 22.104 ; + END + END rd_out[153] + PIN rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.224 0.024 22.248 ; + END + END rd_out[154] + PIN rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.368 0.024 22.392 ; + END + END rd_out[155] + PIN rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.512 0.024 22.536 ; + END + END rd_out[156] + PIN rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.656 0.024 22.680 ; + END + END rd_out[157] + PIN rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.800 0.024 22.824 ; + END + END rd_out[158] + PIN rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.944 0.024 22.968 ; + END + END rd_out[159] + PIN rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.088 0.024 23.112 ; + END + END rd_out[160] + PIN rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.232 0.024 23.256 ; + END + END rd_out[161] + PIN rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.376 0.024 23.400 ; + END + END rd_out[162] + PIN rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.520 0.024 23.544 ; + END + END rd_out[163] + PIN rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.024 23.688 ; + END + END rd_out[164] + PIN rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.024 23.832 ; + END + END rd_out[165] + PIN rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.024 23.976 ; + END + END rd_out[166] + PIN rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.024 24.120 ; + END + END rd_out[167] + PIN rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.024 24.264 ; + END + END rd_out[168] + PIN rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.024 24.408 ; + END + END rd_out[169] + PIN rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.024 24.552 ; + END + END rd_out[170] + PIN rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.024 24.696 ; + END + END rd_out[171] + PIN rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.024 24.840 ; + END + END rd_out[172] + PIN rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.024 24.984 ; + END + END rd_out[173] + PIN rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.024 25.128 ; + END + END rd_out[174] + PIN rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.024 25.272 ; + END + END rd_out[175] + PIN rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END rd_out[176] + PIN rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.024 25.560 ; + END + END rd_out[177] + PIN rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.024 25.704 ; + END + END rd_out[178] + PIN rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.024 25.848 ; + END + END rd_out[179] + PIN rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.024 25.992 ; + END + END rd_out[180] + PIN rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.024 26.136 ; + END + END rd_out[181] + PIN rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.024 26.280 ; + END + END rd_out[182] + PIN rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.024 26.424 ; + END + END rd_out[183] + PIN rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.024 26.568 ; + END + END rd_out[184] + PIN rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.024 26.712 ; + END + END rd_out[185] + PIN rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END rd_out[186] + PIN rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.024 27.000 ; + END + END rd_out[187] + PIN rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.024 27.144 ; + END + END rd_out[188] + PIN rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.024 27.288 ; + END + END rd_out[189] + PIN rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.024 27.432 ; + END + END rd_out[190] + PIN rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.024 27.576 ; + END + END rd_out[191] + PIN rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.024 27.720 ; + END + END rd_out[192] + PIN rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.024 27.864 ; + END + END rd_out[193] + PIN rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.024 28.008 ; + END + END rd_out[194] + PIN rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.024 28.152 ; + END + END rd_out[195] + PIN rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END rd_out[196] + PIN rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.024 28.440 ; + END + END rd_out[197] + PIN rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.024 28.584 ; + END + END rd_out[198] + PIN rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.024 28.728 ; + END + END rd_out[199] + PIN rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.024 28.872 ; + END + END rd_out[200] + PIN rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.024 29.016 ; + END + END rd_out[201] + PIN rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.024 29.160 ; + END + END rd_out[202] + PIN rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.024 29.304 ; + END + END rd_out[203] + PIN rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.024 29.448 ; + END + END rd_out[204] + PIN rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.024 29.592 ; + END + END rd_out[205] + PIN rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.024 29.736 ; + END + END rd_out[206] + PIN rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.024 29.880 ; + END + END rd_out[207] + PIN rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.024 30.024 ; + END + END rd_out[208] + PIN rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.024 30.168 ; + END + END rd_out[209] + PIN rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.024 30.312 ; + END + END rd_out[210] + PIN rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.024 30.456 ; + END + END rd_out[211] + PIN rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.024 30.600 ; + END + END rd_out[212] + PIN rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.024 30.744 ; + END + END rd_out[213] + PIN rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.024 30.888 ; + END + END rd_out[214] + PIN rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.024 31.032 ; + END + END rd_out[215] + PIN rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END rd_out[216] + PIN rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.024 31.320 ; + END + END rd_out[217] + PIN rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.024 31.464 ; + END + END rd_out[218] + PIN rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.024 31.608 ; + END + END rd_out[219] + PIN rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.024 31.752 ; + END + END rd_out[220] + PIN rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.872 0.024 31.896 ; + END + END rd_out[221] + PIN rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.016 0.024 32.040 ; + END + END rd_out[222] + PIN rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.160 0.024 32.184 ; + END + END rd_out[223] + PIN rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.304 0.024 32.328 ; + END + END rd_out[224] + PIN rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.448 0.024 32.472 ; + END + END rd_out[225] + PIN rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.592 0.024 32.616 ; + END + END rd_out[226] + PIN rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.736 0.024 32.760 ; + END + END rd_out[227] + PIN rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.880 0.024 32.904 ; + END + END rd_out[228] + PIN rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.024 0.024 33.048 ; + END + END rd_out[229] + PIN rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.168 0.024 33.192 ; + END + END rd_out[230] + PIN rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.312 0.024 33.336 ; + END + END rd_out[231] + PIN rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.456 0.024 33.480 ; + END + END rd_out[232] + PIN rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.600 0.024 33.624 ; + END + END rd_out[233] + PIN rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.744 0.024 33.768 ; + END + END rd_out[234] + PIN rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.888 0.024 33.912 ; + END + END rd_out[235] + PIN rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.032 0.024 34.056 ; + END + END rd_out[236] + PIN rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.176 0.024 34.200 ; + END + END rd_out[237] + PIN rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.320 0.024 34.344 ; + END + END rd_out[238] + PIN rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.464 0.024 34.488 ; + END + END rd_out[239] + PIN rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.608 0.024 34.632 ; + END + END rd_out[240] + PIN rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.752 0.024 34.776 ; + END + END rd_out[241] + PIN rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.896 0.024 34.920 ; + END + END rd_out[242] + PIN rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.040 0.024 35.064 ; + END + END rd_out[243] + PIN rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.184 0.024 35.208 ; + END + END rd_out[244] + PIN rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.328 0.024 35.352 ; + END + END rd_out[245] + PIN rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.472 0.024 35.496 ; + END + END rd_out[246] + PIN rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.616 0.024 35.640 ; + END + END rd_out[247] + PIN rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END rd_out[248] + PIN rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.904 0.024 35.928 ; + END + END rd_out[249] + PIN rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.048 0.024 36.072 ; + END + END rd_out[250] + PIN rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.192 0.024 36.216 ; + END + END rd_out[251] + PIN rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.336 0.024 36.360 ; + END + END rd_out[252] + PIN rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.480 0.024 36.504 ; + END + END rd_out[253] + PIN rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.624 0.024 36.648 ; + END + END rd_out[254] + PIN rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.768 0.024 36.792 ; + END + END rd_out[255] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.744 0.024 39.768 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.888 0.024 39.912 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.032 0.024 40.056 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.176 0.024 40.200 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.320 0.024 40.344 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.464 0.024 40.488 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.608 0.024 40.632 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.752 0.024 40.776 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.896 0.024 40.920 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.040 0.024 41.064 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.184 0.024 41.208 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.328 0.024 41.352 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.472 0.024 41.496 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.616 0.024 41.640 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.760 0.024 41.784 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.904 0.024 41.928 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.048 0.024 42.072 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.192 0.024 42.216 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.336 0.024 42.360 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.480 0.024 42.504 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.624 0.024 42.648 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.768 0.024 42.792 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.912 0.024 42.936 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.056 0.024 43.080 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.200 0.024 43.224 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.344 0.024 43.368 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.488 0.024 43.512 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.632 0.024 43.656 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.776 0.024 43.800 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.920 0.024 43.944 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.064 0.024 44.088 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.208 0.024 44.232 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.352 0.024 44.376 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.496 0.024 44.520 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.640 0.024 44.664 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.784 0.024 44.808 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.928 0.024 44.952 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.072 0.024 45.096 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.216 0.024 45.240 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.360 0.024 45.384 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.504 0.024 45.528 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.648 0.024 45.672 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.792 0.024 45.816 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.936 0.024 45.960 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.080 0.024 46.104 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.224 0.024 46.248 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.368 0.024 46.392 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.512 0.024 46.536 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.656 0.024 46.680 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.800 0.024 46.824 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.944 0.024 46.968 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.088 0.024 47.112 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.232 0.024 47.256 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.376 0.024 47.400 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.520 0.024 47.544 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.664 0.024 47.688 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.808 0.024 47.832 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.952 0.024 47.976 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.096 0.024 48.120 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.240 0.024 48.264 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.384 0.024 48.408 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.528 0.024 48.552 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.672 0.024 48.696 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.816 0.024 48.840 ; + END + END wd_in[63] + PIN wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.960 0.024 48.984 ; + END + END wd_in[64] + PIN wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.104 0.024 49.128 ; + END + END wd_in[65] + PIN wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.248 0.024 49.272 ; + END + END wd_in[66] + PIN wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.392 0.024 49.416 ; + END + END wd_in[67] + PIN wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.536 0.024 49.560 ; + END + END wd_in[68] + PIN wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.680 0.024 49.704 ; + END + END wd_in[69] + PIN wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.824 0.024 49.848 ; + END + END wd_in[70] + PIN wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.968 0.024 49.992 ; + END + END wd_in[71] + PIN wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.112 0.024 50.136 ; + END + END wd_in[72] + PIN wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.256 0.024 50.280 ; + END + END wd_in[73] + PIN wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.400 0.024 50.424 ; + END + END wd_in[74] + PIN wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.544 0.024 50.568 ; + END + END wd_in[75] + PIN wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.688 0.024 50.712 ; + END + END wd_in[76] + PIN wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.832 0.024 50.856 ; + END + END wd_in[77] + PIN wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.976 0.024 51.000 ; + END + END wd_in[78] + PIN wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.120 0.024 51.144 ; + END + END wd_in[79] + PIN wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.264 0.024 51.288 ; + END + END wd_in[80] + PIN wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.408 0.024 51.432 ; + END + END wd_in[81] + PIN wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.552 0.024 51.576 ; + END + END wd_in[82] + PIN wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.696 0.024 51.720 ; + END + END wd_in[83] + PIN wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.840 0.024 51.864 ; + END + END wd_in[84] + PIN wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.984 0.024 52.008 ; + END + END wd_in[85] + PIN wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.128 0.024 52.152 ; + END + END wd_in[86] + PIN wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.272 0.024 52.296 ; + END + END wd_in[87] + PIN wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.416 0.024 52.440 ; + END + END wd_in[88] + PIN wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.560 0.024 52.584 ; + END + END wd_in[89] + PIN wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.704 0.024 52.728 ; + END + END wd_in[90] + PIN wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.848 0.024 52.872 ; + END + END wd_in[91] + PIN wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.992 0.024 53.016 ; + END + END wd_in[92] + PIN wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.136 0.024 53.160 ; + END + END wd_in[93] + PIN wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.280 0.024 53.304 ; + END + END wd_in[94] + PIN wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.424 0.024 53.448 ; + END + END wd_in[95] + PIN wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.568 0.024 53.592 ; + END + END wd_in[96] + PIN wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.712 0.024 53.736 ; + END + END wd_in[97] + PIN wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.856 0.024 53.880 ; + END + END wd_in[98] + PIN wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.000 0.024 54.024 ; + END + END wd_in[99] + PIN wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.144 0.024 54.168 ; + END + END wd_in[100] + PIN wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.288 0.024 54.312 ; + END + END wd_in[101] + PIN wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.432 0.024 54.456 ; + END + END wd_in[102] + PIN wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.576 0.024 54.600 ; + END + END wd_in[103] + PIN wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.720 0.024 54.744 ; + END + END wd_in[104] + PIN wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.864 0.024 54.888 ; + END + END wd_in[105] + PIN wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.008 0.024 55.032 ; + END + END wd_in[106] + PIN wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.152 0.024 55.176 ; + END + END wd_in[107] + PIN wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.296 0.024 55.320 ; + END + END wd_in[108] + PIN wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.440 0.024 55.464 ; + END + END wd_in[109] + PIN wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.584 0.024 55.608 ; + END + END wd_in[110] + PIN wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.728 0.024 55.752 ; + END + END wd_in[111] + PIN wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.872 0.024 55.896 ; + END + END wd_in[112] + PIN wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.016 0.024 56.040 ; + END + END wd_in[113] + PIN wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.160 0.024 56.184 ; + END + END wd_in[114] + PIN wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.304 0.024 56.328 ; + END + END wd_in[115] + PIN wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.448 0.024 56.472 ; + END + END wd_in[116] + PIN wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.592 0.024 56.616 ; + END + END wd_in[117] + PIN wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.736 0.024 56.760 ; + END + END wd_in[118] + PIN wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.880 0.024 56.904 ; + END + END wd_in[119] + PIN wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.024 0.024 57.048 ; + END + END wd_in[120] + PIN wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.168 0.024 57.192 ; + END + END wd_in[121] + PIN wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.312 0.024 57.336 ; + END + END wd_in[122] + PIN wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.456 0.024 57.480 ; + END + END wd_in[123] + PIN wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.600 0.024 57.624 ; + END + END wd_in[124] + PIN wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.744 0.024 57.768 ; + END + END wd_in[125] + PIN wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.888 0.024 57.912 ; + END + END wd_in[126] + PIN wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.032 0.024 58.056 ; + END + END wd_in[127] + PIN wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.176 0.024 58.200 ; + END + END wd_in[128] + PIN wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.320 0.024 58.344 ; + END + END wd_in[129] + PIN wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.464 0.024 58.488 ; + END + END wd_in[130] + PIN wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.608 0.024 58.632 ; + END + END wd_in[131] + PIN wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.752 0.024 58.776 ; + END + END wd_in[132] + PIN wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.896 0.024 58.920 ; + END + END wd_in[133] + PIN wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.040 0.024 59.064 ; + END + END wd_in[134] + PIN wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.184 0.024 59.208 ; + END + END wd_in[135] + PIN wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.328 0.024 59.352 ; + END + END wd_in[136] + PIN wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.472 0.024 59.496 ; + END + END wd_in[137] + PIN wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.616 0.024 59.640 ; + END + END wd_in[138] + PIN wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.760 0.024 59.784 ; + END + END wd_in[139] + PIN wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.904 0.024 59.928 ; + END + END wd_in[140] + PIN wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.048 0.024 60.072 ; + END + END wd_in[141] + PIN wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.192 0.024 60.216 ; + END + END wd_in[142] + PIN wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.336 0.024 60.360 ; + END + END wd_in[143] + PIN wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.480 0.024 60.504 ; + END + END wd_in[144] + PIN wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.624 0.024 60.648 ; + END + END wd_in[145] + PIN wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.768 0.024 60.792 ; + END + END wd_in[146] + PIN wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.912 0.024 60.936 ; + END + END wd_in[147] + PIN wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.056 0.024 61.080 ; + END + END wd_in[148] + PIN wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.200 0.024 61.224 ; + END + END wd_in[149] + PIN wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.344 0.024 61.368 ; + END + END wd_in[150] + PIN wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.488 0.024 61.512 ; + END + END wd_in[151] + PIN wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.632 0.024 61.656 ; + END + END wd_in[152] + PIN wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.776 0.024 61.800 ; + END + END wd_in[153] + PIN wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.920 0.024 61.944 ; + END + END wd_in[154] + PIN wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.064 0.024 62.088 ; + END + END wd_in[155] + PIN wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.208 0.024 62.232 ; + END + END wd_in[156] + PIN wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.352 0.024 62.376 ; + END + END wd_in[157] + PIN wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.496 0.024 62.520 ; + END + END wd_in[158] + PIN wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.640 0.024 62.664 ; + END + END wd_in[159] + PIN wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.784 0.024 62.808 ; + END + END wd_in[160] + PIN wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.928 0.024 62.952 ; + END + END wd_in[161] + PIN wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.072 0.024 63.096 ; + END + END wd_in[162] + PIN wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.216 0.024 63.240 ; + END + END wd_in[163] + PIN wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.360 0.024 63.384 ; + END + END wd_in[164] + PIN wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.504 0.024 63.528 ; + END + END wd_in[165] + PIN wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.648 0.024 63.672 ; + END + END wd_in[166] + PIN wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.792 0.024 63.816 ; + END + END wd_in[167] + PIN wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.936 0.024 63.960 ; + END + END wd_in[168] + PIN wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.080 0.024 64.104 ; + END + END wd_in[169] + PIN wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.224 0.024 64.248 ; + END + END wd_in[170] + PIN wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.368 0.024 64.392 ; + END + END wd_in[171] + PIN wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.512 0.024 64.536 ; + END + END wd_in[172] + PIN wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.656 0.024 64.680 ; + END + END wd_in[173] + PIN wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.800 0.024 64.824 ; + END + END wd_in[174] + PIN wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.944 0.024 64.968 ; + END + END wd_in[175] + PIN wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.088 0.024 65.112 ; + END + END wd_in[176] + PIN wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.232 0.024 65.256 ; + END + END wd_in[177] + PIN wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.376 0.024 65.400 ; + END + END wd_in[178] + PIN wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.520 0.024 65.544 ; + END + END wd_in[179] + PIN wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.664 0.024 65.688 ; + END + END wd_in[180] + PIN wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.808 0.024 65.832 ; + END + END wd_in[181] + PIN wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.952 0.024 65.976 ; + END + END wd_in[182] + PIN wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.096 0.024 66.120 ; + END + END wd_in[183] + PIN wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.240 0.024 66.264 ; + END + END wd_in[184] + PIN wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.384 0.024 66.408 ; + END + END wd_in[185] + PIN wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.528 0.024 66.552 ; + END + END wd_in[186] + PIN wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.672 0.024 66.696 ; + END + END wd_in[187] + PIN wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.816 0.024 66.840 ; + END + END wd_in[188] + PIN wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.960 0.024 66.984 ; + END + END wd_in[189] + PIN wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.104 0.024 67.128 ; + END + END wd_in[190] + PIN wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.248 0.024 67.272 ; + END + END wd_in[191] + PIN wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.392 0.024 67.416 ; + END + END wd_in[192] + PIN wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.536 0.024 67.560 ; + END + END wd_in[193] + PIN wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.680 0.024 67.704 ; + END + END wd_in[194] + PIN wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.824 0.024 67.848 ; + END + END wd_in[195] + PIN wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.968 0.024 67.992 ; + END + END wd_in[196] + PIN wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.112 0.024 68.136 ; + END + END wd_in[197] + PIN wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.256 0.024 68.280 ; + END + END wd_in[198] + PIN wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.400 0.024 68.424 ; + END + END wd_in[199] + PIN wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.544 0.024 68.568 ; + END + END wd_in[200] + PIN wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.688 0.024 68.712 ; + END + END wd_in[201] + PIN wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.832 0.024 68.856 ; + END + END wd_in[202] + PIN wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.976 0.024 69.000 ; + END + END wd_in[203] + PIN wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.120 0.024 69.144 ; + END + END wd_in[204] + PIN wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.264 0.024 69.288 ; + END + END wd_in[205] + PIN wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.408 0.024 69.432 ; + END + END wd_in[206] + PIN wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.552 0.024 69.576 ; + END + END wd_in[207] + PIN wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.696 0.024 69.720 ; + END + END wd_in[208] + PIN wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.840 0.024 69.864 ; + END + END wd_in[209] + PIN wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.984 0.024 70.008 ; + END + END wd_in[210] + PIN wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.128 0.024 70.152 ; + END + END wd_in[211] + PIN wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.272 0.024 70.296 ; + END + END wd_in[212] + PIN wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.416 0.024 70.440 ; + END + END wd_in[213] + PIN wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.560 0.024 70.584 ; + END + END wd_in[214] + PIN wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.704 0.024 70.728 ; + END + END wd_in[215] + PIN wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.848 0.024 70.872 ; + END + END wd_in[216] + PIN wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.992 0.024 71.016 ; + END + END wd_in[217] + PIN wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.136 0.024 71.160 ; + END + END wd_in[218] + PIN wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.280 0.024 71.304 ; + END + END wd_in[219] + PIN wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.424 0.024 71.448 ; + END + END wd_in[220] + PIN wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.568 0.024 71.592 ; + END + END wd_in[221] + PIN wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.712 0.024 71.736 ; + END + END wd_in[222] + PIN wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.856 0.024 71.880 ; + END + END wd_in[223] + PIN wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.000 0.024 72.024 ; + END + END wd_in[224] + PIN wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.144 0.024 72.168 ; + END + END wd_in[225] + PIN wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.288 0.024 72.312 ; + END + END wd_in[226] + PIN wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.432 0.024 72.456 ; + END + END wd_in[227] + PIN wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.576 0.024 72.600 ; + END + END wd_in[228] + PIN wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.720 0.024 72.744 ; + END + END wd_in[229] + PIN wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.864 0.024 72.888 ; + END + END wd_in[230] + PIN wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.008 0.024 73.032 ; + END + END wd_in[231] + PIN wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.152 0.024 73.176 ; + END + END wd_in[232] + PIN wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.296 0.024 73.320 ; + END + END wd_in[233] + PIN wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.440 0.024 73.464 ; + END + END wd_in[234] + PIN wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.584 0.024 73.608 ; + END + END wd_in[235] + PIN wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.728 0.024 73.752 ; + END + END wd_in[236] + PIN wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.872 0.024 73.896 ; + END + END wd_in[237] + PIN wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.016 0.024 74.040 ; + END + END wd_in[238] + PIN wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.160 0.024 74.184 ; + END + END wd_in[239] + PIN wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.304 0.024 74.328 ; + END + END wd_in[240] + PIN wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.448 0.024 74.472 ; + END + END wd_in[241] + PIN wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.592 0.024 74.616 ; + END + END wd_in[242] + PIN wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.736 0.024 74.760 ; + END + END wd_in[243] + PIN wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.880 0.024 74.904 ; + END + END wd_in[244] + PIN wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.024 0.024 75.048 ; + END + END wd_in[245] + PIN wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.168 0.024 75.192 ; + END + END wd_in[246] + PIN wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.312 0.024 75.336 ; + END + END wd_in[247] + PIN wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.456 0.024 75.480 ; + END + END wd_in[248] + PIN wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.600 0.024 75.624 ; + END + END wd_in[249] + PIN wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.744 0.024 75.768 ; + END + END wd_in[250] + PIN wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.888 0.024 75.912 ; + END + END wd_in[251] + PIN wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.032 0.024 76.056 ; + END + END wd_in[252] + PIN wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.176 0.024 76.200 ; + END + END wd_in[253] + PIN wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.320 0.024 76.344 ; + END + END wd_in[254] + PIN wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.464 0.024 76.488 ; + END + END wd_in[255] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.440 0.024 79.464 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.584 0.024 79.608 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.728 0.024 79.752 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.872 0.024 79.896 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.016 0.024 80.040 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.160 0.024 80.184 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.304 0.024 80.328 ; + END + END addr_in[6] + PIN addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.448 0.024 80.472 ; + END + END addr_in[7] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.424 0.024 83.448 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.568 0.024 83.592 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.712 0.024 83.736 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 33.202 0.096 ; + RECT 0.048 0.768 33.202 0.864 ; + RECT 0.048 1.536 33.202 1.632 ; + RECT 0.048 2.304 33.202 2.400 ; + RECT 0.048 3.072 33.202 3.168 ; + RECT 0.048 3.840 33.202 3.936 ; + RECT 0.048 4.608 33.202 4.704 ; + RECT 0.048 5.376 33.202 5.472 ; + RECT 0.048 6.144 33.202 6.240 ; + RECT 0.048 6.912 33.202 7.008 ; + RECT 0.048 7.680 33.202 7.776 ; + RECT 0.048 8.448 33.202 8.544 ; + RECT 0.048 9.216 33.202 9.312 ; + RECT 0.048 9.984 33.202 10.080 ; + RECT 0.048 10.752 33.202 10.848 ; + RECT 0.048 11.520 33.202 11.616 ; + RECT 0.048 12.288 33.202 12.384 ; + RECT 0.048 13.056 33.202 13.152 ; + RECT 0.048 13.824 33.202 13.920 ; + RECT 0.048 14.592 33.202 14.688 ; + RECT 0.048 15.360 33.202 15.456 ; + RECT 0.048 16.128 33.202 16.224 ; + RECT 0.048 16.896 33.202 16.992 ; + RECT 0.048 17.664 33.202 17.760 ; + RECT 0.048 18.432 33.202 18.528 ; + RECT 0.048 19.200 33.202 19.296 ; + RECT 0.048 19.968 33.202 20.064 ; + RECT 0.048 20.736 33.202 20.832 ; + RECT 0.048 21.504 33.202 21.600 ; + RECT 0.048 22.272 33.202 22.368 ; + RECT 0.048 23.040 33.202 23.136 ; + RECT 0.048 23.808 33.202 23.904 ; + RECT 0.048 24.576 33.202 24.672 ; + RECT 0.048 25.344 33.202 25.440 ; + RECT 0.048 26.112 33.202 26.208 ; + RECT 0.048 26.880 33.202 26.976 ; + RECT 0.048 27.648 33.202 27.744 ; + RECT 0.048 28.416 33.202 28.512 ; + RECT 0.048 29.184 33.202 29.280 ; + RECT 0.048 29.952 33.202 30.048 ; + RECT 0.048 30.720 33.202 30.816 ; + RECT 0.048 31.488 33.202 31.584 ; + RECT 0.048 32.256 33.202 32.352 ; + RECT 0.048 33.024 33.202 33.120 ; + RECT 0.048 33.792 33.202 33.888 ; + RECT 0.048 34.560 33.202 34.656 ; + RECT 0.048 35.328 33.202 35.424 ; + RECT 0.048 36.096 33.202 36.192 ; + RECT 0.048 36.864 33.202 36.960 ; + RECT 0.048 37.632 33.202 37.728 ; + RECT 0.048 38.400 33.202 38.496 ; + RECT 0.048 39.168 33.202 39.264 ; + RECT 0.048 39.936 33.202 40.032 ; + RECT 0.048 40.704 33.202 40.800 ; + RECT 0.048 41.472 33.202 41.568 ; + RECT 0.048 42.240 33.202 42.336 ; + RECT 0.048 43.008 33.202 43.104 ; + RECT 0.048 43.776 33.202 43.872 ; + RECT 0.048 44.544 33.202 44.640 ; + RECT 0.048 45.312 33.202 45.408 ; + RECT 0.048 46.080 33.202 46.176 ; + RECT 0.048 46.848 33.202 46.944 ; + RECT 0.048 47.616 33.202 47.712 ; + RECT 0.048 48.384 33.202 48.480 ; + RECT 0.048 49.152 33.202 49.248 ; + RECT 0.048 49.920 33.202 50.016 ; + RECT 0.048 50.688 33.202 50.784 ; + RECT 0.048 51.456 33.202 51.552 ; + RECT 0.048 52.224 33.202 52.320 ; + RECT 0.048 52.992 33.202 53.088 ; + RECT 0.048 53.760 33.202 53.856 ; + RECT 0.048 54.528 33.202 54.624 ; + RECT 0.048 55.296 33.202 55.392 ; + RECT 0.048 56.064 33.202 56.160 ; + RECT 0.048 56.832 33.202 56.928 ; + RECT 0.048 57.600 33.202 57.696 ; + RECT 0.048 58.368 33.202 58.464 ; + RECT 0.048 59.136 33.202 59.232 ; + RECT 0.048 59.904 33.202 60.000 ; + RECT 0.048 60.672 33.202 60.768 ; + RECT 0.048 61.440 33.202 61.536 ; + RECT 0.048 62.208 33.202 62.304 ; + RECT 0.048 62.976 33.202 63.072 ; + RECT 0.048 63.744 33.202 63.840 ; + RECT 0.048 64.512 33.202 64.608 ; + RECT 0.048 65.280 33.202 65.376 ; + RECT 0.048 66.048 33.202 66.144 ; + RECT 0.048 66.816 33.202 66.912 ; + RECT 0.048 67.584 33.202 67.680 ; + RECT 0.048 68.352 33.202 68.448 ; + RECT 0.048 69.120 33.202 69.216 ; + RECT 0.048 69.888 33.202 69.984 ; + RECT 0.048 70.656 33.202 70.752 ; + RECT 0.048 71.424 33.202 71.520 ; + RECT 0.048 72.192 33.202 72.288 ; + RECT 0.048 72.960 33.202 73.056 ; + RECT 0.048 73.728 33.202 73.824 ; + RECT 0.048 74.496 33.202 74.592 ; + RECT 0.048 75.264 33.202 75.360 ; + RECT 0.048 76.032 33.202 76.128 ; + RECT 0.048 76.800 33.202 76.896 ; + RECT 0.048 77.568 33.202 77.664 ; + RECT 0.048 78.336 33.202 78.432 ; + RECT 0.048 79.104 33.202 79.200 ; + RECT 0.048 79.872 33.202 79.968 ; + RECT 0.048 80.640 33.202 80.736 ; + RECT 0.048 81.408 33.202 81.504 ; + RECT 0.048 82.176 33.202 82.272 ; + RECT 0.048 82.944 33.202 83.040 ; + RECT 0.048 83.712 33.202 83.808 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 33.202 0.480 ; + RECT 0.048 1.152 33.202 1.248 ; + RECT 0.048 1.920 33.202 2.016 ; + RECT 0.048 2.688 33.202 2.784 ; + RECT 0.048 3.456 33.202 3.552 ; + RECT 0.048 4.224 33.202 4.320 ; + RECT 0.048 4.992 33.202 5.088 ; + RECT 0.048 5.760 33.202 5.856 ; + RECT 0.048 6.528 33.202 6.624 ; + RECT 0.048 7.296 33.202 7.392 ; + RECT 0.048 8.064 33.202 8.160 ; + RECT 0.048 8.832 33.202 8.928 ; + RECT 0.048 9.600 33.202 9.696 ; + RECT 0.048 10.368 33.202 10.464 ; + RECT 0.048 11.136 33.202 11.232 ; + RECT 0.048 11.904 33.202 12.000 ; + RECT 0.048 12.672 33.202 12.768 ; + RECT 0.048 13.440 33.202 13.536 ; + RECT 0.048 14.208 33.202 14.304 ; + RECT 0.048 14.976 33.202 15.072 ; + RECT 0.048 15.744 33.202 15.840 ; + RECT 0.048 16.512 33.202 16.608 ; + RECT 0.048 17.280 33.202 17.376 ; + RECT 0.048 18.048 33.202 18.144 ; + RECT 0.048 18.816 33.202 18.912 ; + RECT 0.048 19.584 33.202 19.680 ; + RECT 0.048 20.352 33.202 20.448 ; + RECT 0.048 21.120 33.202 21.216 ; + RECT 0.048 21.888 33.202 21.984 ; + RECT 0.048 22.656 33.202 22.752 ; + RECT 0.048 23.424 33.202 23.520 ; + RECT 0.048 24.192 33.202 24.288 ; + RECT 0.048 24.960 33.202 25.056 ; + RECT 0.048 25.728 33.202 25.824 ; + RECT 0.048 26.496 33.202 26.592 ; + RECT 0.048 27.264 33.202 27.360 ; + RECT 0.048 28.032 33.202 28.128 ; + RECT 0.048 28.800 33.202 28.896 ; + RECT 0.048 29.568 33.202 29.664 ; + RECT 0.048 30.336 33.202 30.432 ; + RECT 0.048 31.104 33.202 31.200 ; + RECT 0.048 31.872 33.202 31.968 ; + RECT 0.048 32.640 33.202 32.736 ; + RECT 0.048 33.408 33.202 33.504 ; + RECT 0.048 34.176 33.202 34.272 ; + RECT 0.048 34.944 33.202 35.040 ; + RECT 0.048 35.712 33.202 35.808 ; + RECT 0.048 36.480 33.202 36.576 ; + RECT 0.048 37.248 33.202 37.344 ; + RECT 0.048 38.016 33.202 38.112 ; + RECT 0.048 38.784 33.202 38.880 ; + RECT 0.048 39.552 33.202 39.648 ; + RECT 0.048 40.320 33.202 40.416 ; + RECT 0.048 41.088 33.202 41.184 ; + RECT 0.048 41.856 33.202 41.952 ; + RECT 0.048 42.624 33.202 42.720 ; + RECT 0.048 43.392 33.202 43.488 ; + RECT 0.048 44.160 33.202 44.256 ; + RECT 0.048 44.928 33.202 45.024 ; + RECT 0.048 45.696 33.202 45.792 ; + RECT 0.048 46.464 33.202 46.560 ; + RECT 0.048 47.232 33.202 47.328 ; + RECT 0.048 48.000 33.202 48.096 ; + RECT 0.048 48.768 33.202 48.864 ; + RECT 0.048 49.536 33.202 49.632 ; + RECT 0.048 50.304 33.202 50.400 ; + RECT 0.048 51.072 33.202 51.168 ; + RECT 0.048 51.840 33.202 51.936 ; + RECT 0.048 52.608 33.202 52.704 ; + RECT 0.048 53.376 33.202 53.472 ; + RECT 0.048 54.144 33.202 54.240 ; + RECT 0.048 54.912 33.202 55.008 ; + RECT 0.048 55.680 33.202 55.776 ; + RECT 0.048 56.448 33.202 56.544 ; + RECT 0.048 57.216 33.202 57.312 ; + RECT 0.048 57.984 33.202 58.080 ; + RECT 0.048 58.752 33.202 58.848 ; + RECT 0.048 59.520 33.202 59.616 ; + RECT 0.048 60.288 33.202 60.384 ; + RECT 0.048 61.056 33.202 61.152 ; + RECT 0.048 61.824 33.202 61.920 ; + RECT 0.048 62.592 33.202 62.688 ; + RECT 0.048 63.360 33.202 63.456 ; + RECT 0.048 64.128 33.202 64.224 ; + RECT 0.048 64.896 33.202 64.992 ; + RECT 0.048 65.664 33.202 65.760 ; + RECT 0.048 66.432 33.202 66.528 ; + RECT 0.048 67.200 33.202 67.296 ; + RECT 0.048 67.968 33.202 68.064 ; + RECT 0.048 68.736 33.202 68.832 ; + RECT 0.048 69.504 33.202 69.600 ; + RECT 0.048 70.272 33.202 70.368 ; + RECT 0.048 71.040 33.202 71.136 ; + RECT 0.048 71.808 33.202 71.904 ; + RECT 0.048 72.576 33.202 72.672 ; + RECT 0.048 73.344 33.202 73.440 ; + RECT 0.048 74.112 33.202 74.208 ; + RECT 0.048 74.880 33.202 74.976 ; + RECT 0.048 75.648 33.202 75.744 ; + RECT 0.048 76.416 33.202 76.512 ; + RECT 0.048 77.184 33.202 77.280 ; + RECT 0.048 77.952 33.202 78.048 ; + RECT 0.048 78.720 33.202 78.816 ; + RECT 0.048 79.488 33.202 79.584 ; + RECT 0.048 80.256 33.202 80.352 ; + RECT 0.048 81.024 33.202 81.120 ; + RECT 0.048 81.792 33.202 81.888 ; + RECT 0.048 82.560 33.202 82.656 ; + RECT 0.048 83.328 33.202 83.424 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 84.000 ; + LAYER M2 ; + RECT 0 0 33.250 84.000 ; + LAYER M3 ; + RECT 0 0 33.250 84.000 ; + LAYER M4 ; + RECT 0 0 33.250 84.000 ; + END +END spsram_256x256 + +END LIBRARY +module spsram_256x256 +( + rd_out, + addr_in, + we_in, + wd_in, + clk, + ce_in +); + parameter BITS = 256; + parameter WORD_DEPTH = 256; + parameter ADDR_WIDTH = 8; + parameter corrupt_mem_on_X_p = 1; + + output reg [BITS-1:0] rd_out; + input [ADDR_WIDTH-1:0] addr_in; + input we_in; + input [BITS-1:0] wd_in; + input clk; + input ce_in; + + reg [BITS-1:0] mem [0:WORD_DEPTH-1]; + + integer j; + + always @(posedge clk) + begin + if (ce_in) + begin + //if ((we_in !== 1'b1 && we_in !== 1'b0) && corrupt_mem_on_X_p) + if (corrupt_mem_on_X_p && + ((^we_in === 1'bx) || (^addr_in === 1'bx)) + ) + begin + // WEN or ADDR is unknown, so corrupt entire array (using unsynthesizeable for loop) + for (j = 0; j < WORD_DEPTH; j = j + 1) + mem[j] <= 'x; + $display("warning: ce_in=1, we_in is %b, addr_in = %x in spsram_256x256", we_in, addr_in); + end + else if (we_in) + begin + mem[addr_in] <= (wd_in) | (mem[addr_in]); + end + // read + rd_out <= mem[addr_in]; + end + else + begin + // Make sure read fails if ce_in is low + rd_out <= 'x; + end + end + + // Timing check placeholders (will be replaced during SDF back-annotation) + reg notifier; + specify + // Delay from clk to rd_out + (posedge clk *> rd_out) = (0, 0); + + // Timing checks + $width (posedge clk, 0, 0, notifier); + $width (negedge clk, 0, 0, notifier); + $period (posedge clk, 0, notifier); + $setuphold (posedge clk, we_in, 0, 0, notifier); + $setuphold (posedge clk, ce_in, 0, 0, notifier); + $setuphold (posedge clk, addr_in, 0, 0, notifier); + $setuphold (posedge clk, wd_in, 0, 0, notifier); + endspecify + +endmodule +(* blackbox *) +module spsram_256x256 ( + output reg [31:0] rd_out, + input [7:0] addr_in, + input we_in, + input [255:0] wd_in, + input clk, + input ce_in +); +endmodule +library(spsram_256x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(spsram_256x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(spsram_256x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(spsram_256x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(spsram_256x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(spsram_256x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (spsram_256x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (spsram_256x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(spsram_256x256) { + area : 2751.883; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 256; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(spsram_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(spsram_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : spsram_256x256_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(spsram_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(spsram_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(spsram_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(spsram_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : spsram_256x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : spsram_256x256_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/test/au/spsram_256x32.au b/test/au/spsram_256x32.au new file mode 100644 index 0000000..c349dc4 --- /dev/null +++ b/test/au/spsram_256x32.au @@ -0,0 +1,1296 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO spsram_256x32 + PROPERTY width 32 ; + PROPERTY depth 256 ; + PROPERTY banks 2 ; + FOREIGN spsram_256x32 0 0 ; + SYMMETRY X Y R90 ; + SIZE 8.360 BY 42.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.024 0.600 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.024 1.128 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.024 2.184 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.024 3.768 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.272 0.024 4.296 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.024 5.880 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.912 0.024 6.936 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.440 0.024 7.464 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.496 0.024 8.520 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.024 0.024 9.048 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.024 10.104 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.608 0.024 10.632 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.024 11.688 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.192 0.024 12.216 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.720 0.024 12.744 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.248 0.024 13.272 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.776 0.024 13.800 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.304 0.024 14.328 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.832 0.024 14.856 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.360 0.024 15.384 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.888 0.024 15.912 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.416 0.024 16.440 ; + END + END rd_out[31] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.712 0.024 17.736 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.240 0.024 18.264 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.768 0.024 18.792 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.296 0.024 19.320 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.024 19.848 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.352 0.024 20.376 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.880 0.024 20.904 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.408 0.024 21.432 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.024 21.960 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.464 0.024 22.488 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.992 0.024 23.016 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.520 0.024 23.544 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.048 0.024 24.072 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.576 0.024 24.600 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.024 25.128 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.024 25.656 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.160 0.024 26.184 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.024 26.712 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.216 0.024 27.240 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.744 0.024 27.768 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.800 0.024 28.824 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.328 0.024 29.352 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.024 29.880 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.384 0.024 30.408 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.912 0.024 30.936 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.024 31.464 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.968 0.024 31.992 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.496 0.024 32.520 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.024 0.024 33.048 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.552 0.024 33.576 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.080 0.024 34.104 ; + END + END wd_in[31] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.376 0.024 35.400 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.904 0.024 35.928 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.432 0.024 36.456 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.960 0.024 36.984 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.488 0.024 37.512 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.016 0.024 38.040 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.544 0.024 38.568 ; + END + END addr_in[6] + PIN addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.072 0.024 39.096 ; + END + END addr_in[7] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.368 0.024 40.392 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.896 0.024 40.920 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.424 0.024 41.448 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 8.312 0.096 ; + RECT 0.048 0.768 8.312 0.864 ; + RECT 0.048 1.536 8.312 1.632 ; + RECT 0.048 2.304 8.312 2.400 ; + RECT 0.048 3.072 8.312 3.168 ; + RECT 0.048 3.840 8.312 3.936 ; + RECT 0.048 4.608 8.312 4.704 ; + RECT 0.048 5.376 8.312 5.472 ; + RECT 0.048 6.144 8.312 6.240 ; + RECT 0.048 6.912 8.312 7.008 ; + RECT 0.048 7.680 8.312 7.776 ; + RECT 0.048 8.448 8.312 8.544 ; + RECT 0.048 9.216 8.312 9.312 ; + RECT 0.048 9.984 8.312 10.080 ; + RECT 0.048 10.752 8.312 10.848 ; + RECT 0.048 11.520 8.312 11.616 ; + RECT 0.048 12.288 8.312 12.384 ; + RECT 0.048 13.056 8.312 13.152 ; + RECT 0.048 13.824 8.312 13.920 ; + RECT 0.048 14.592 8.312 14.688 ; + RECT 0.048 15.360 8.312 15.456 ; + RECT 0.048 16.128 8.312 16.224 ; + RECT 0.048 16.896 8.312 16.992 ; + RECT 0.048 17.664 8.312 17.760 ; + RECT 0.048 18.432 8.312 18.528 ; + RECT 0.048 19.200 8.312 19.296 ; + RECT 0.048 19.968 8.312 20.064 ; + RECT 0.048 20.736 8.312 20.832 ; + RECT 0.048 21.504 8.312 21.600 ; + RECT 0.048 22.272 8.312 22.368 ; + RECT 0.048 23.040 8.312 23.136 ; + RECT 0.048 23.808 8.312 23.904 ; + RECT 0.048 24.576 8.312 24.672 ; + RECT 0.048 25.344 8.312 25.440 ; + RECT 0.048 26.112 8.312 26.208 ; + RECT 0.048 26.880 8.312 26.976 ; + RECT 0.048 27.648 8.312 27.744 ; + RECT 0.048 28.416 8.312 28.512 ; + RECT 0.048 29.184 8.312 29.280 ; + RECT 0.048 29.952 8.312 30.048 ; + RECT 0.048 30.720 8.312 30.816 ; + RECT 0.048 31.488 8.312 31.584 ; + RECT 0.048 32.256 8.312 32.352 ; + RECT 0.048 33.024 8.312 33.120 ; + RECT 0.048 33.792 8.312 33.888 ; + RECT 0.048 34.560 8.312 34.656 ; + RECT 0.048 35.328 8.312 35.424 ; + RECT 0.048 36.096 8.312 36.192 ; + RECT 0.048 36.864 8.312 36.960 ; + RECT 0.048 37.632 8.312 37.728 ; + RECT 0.048 38.400 8.312 38.496 ; + RECT 0.048 39.168 8.312 39.264 ; + RECT 0.048 39.936 8.312 40.032 ; + RECT 0.048 40.704 8.312 40.800 ; + RECT 0.048 41.472 8.312 41.568 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 8.312 0.480 ; + RECT 0.048 1.152 8.312 1.248 ; + RECT 0.048 1.920 8.312 2.016 ; + RECT 0.048 2.688 8.312 2.784 ; + RECT 0.048 3.456 8.312 3.552 ; + RECT 0.048 4.224 8.312 4.320 ; + RECT 0.048 4.992 8.312 5.088 ; + RECT 0.048 5.760 8.312 5.856 ; + RECT 0.048 6.528 8.312 6.624 ; + RECT 0.048 7.296 8.312 7.392 ; + RECT 0.048 8.064 8.312 8.160 ; + RECT 0.048 8.832 8.312 8.928 ; + RECT 0.048 9.600 8.312 9.696 ; + RECT 0.048 10.368 8.312 10.464 ; + RECT 0.048 11.136 8.312 11.232 ; + RECT 0.048 11.904 8.312 12.000 ; + RECT 0.048 12.672 8.312 12.768 ; + RECT 0.048 13.440 8.312 13.536 ; + RECT 0.048 14.208 8.312 14.304 ; + RECT 0.048 14.976 8.312 15.072 ; + RECT 0.048 15.744 8.312 15.840 ; + RECT 0.048 16.512 8.312 16.608 ; + RECT 0.048 17.280 8.312 17.376 ; + RECT 0.048 18.048 8.312 18.144 ; + RECT 0.048 18.816 8.312 18.912 ; + RECT 0.048 19.584 8.312 19.680 ; + RECT 0.048 20.352 8.312 20.448 ; + RECT 0.048 21.120 8.312 21.216 ; + RECT 0.048 21.888 8.312 21.984 ; + RECT 0.048 22.656 8.312 22.752 ; + RECT 0.048 23.424 8.312 23.520 ; + RECT 0.048 24.192 8.312 24.288 ; + RECT 0.048 24.960 8.312 25.056 ; + RECT 0.048 25.728 8.312 25.824 ; + RECT 0.048 26.496 8.312 26.592 ; + RECT 0.048 27.264 8.312 27.360 ; + RECT 0.048 28.032 8.312 28.128 ; + RECT 0.048 28.800 8.312 28.896 ; + RECT 0.048 29.568 8.312 29.664 ; + RECT 0.048 30.336 8.312 30.432 ; + RECT 0.048 31.104 8.312 31.200 ; + RECT 0.048 31.872 8.312 31.968 ; + RECT 0.048 32.640 8.312 32.736 ; + RECT 0.048 33.408 8.312 33.504 ; + RECT 0.048 34.176 8.312 34.272 ; + RECT 0.048 34.944 8.312 35.040 ; + RECT 0.048 35.712 8.312 35.808 ; + RECT 0.048 36.480 8.312 36.576 ; + RECT 0.048 37.248 8.312 37.344 ; + RECT 0.048 38.016 8.312 38.112 ; + RECT 0.048 38.784 8.312 38.880 ; + RECT 0.048 39.552 8.312 39.648 ; + RECT 0.048 40.320 8.312 40.416 ; + RECT 0.048 41.088 8.312 41.184 ; + RECT 0.048 41.856 8.312 41.952 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 8.360 42.000 ; + LAYER M2 ; + RECT 0 0 8.360 42.000 ; + LAYER M3 ; + RECT 0 0 8.360 42.000 ; + LAYER M4 ; + RECT 0 0 8.360 42.000 ; + END +END spsram_256x32 + +END LIBRARY +module spsram_256x32 +( + rd_out, + addr_in, + we_in, + wd_in, + clk, + ce_in +); + parameter BITS = 32; + parameter WORD_DEPTH = 256; + parameter ADDR_WIDTH = 8; + parameter corrupt_mem_on_X_p = 1; + + output reg [BITS-1:0] rd_out; + input [ADDR_WIDTH-1:0] addr_in; + input we_in; + input [BITS-1:0] wd_in; + input clk; + input ce_in; + + reg [BITS-1:0] mem [0:WORD_DEPTH-1]; + + integer j; + + always @(posedge clk) + begin + if (ce_in) + begin + //if ((we_in !== 1'b1 && we_in !== 1'b0) && corrupt_mem_on_X_p) + if (corrupt_mem_on_X_p && + ((^we_in === 1'bx) || (^addr_in === 1'bx)) + ) + begin + // WEN or ADDR is unknown, so corrupt entire array (using unsynthesizeable for loop) + for (j = 0; j < WORD_DEPTH; j = j + 1) + mem[j] <= 'x; + $display("warning: ce_in=1, we_in is %b, addr_in = %x in spsram_256x32", we_in, addr_in); + end + else if (we_in) + begin + mem[addr_in] <= (wd_in) | (mem[addr_in]); + end + // read + rd_out <= mem[addr_in]; + end + else + begin + // Make sure read fails if ce_in is low + rd_out <= 'x; + end + end + + // Timing check placeholders (will be replaced during SDF back-annotation) + reg notifier; + specify + // Delay from clk to rd_out + (posedge clk *> rd_out) = (0, 0); + + // Timing checks + $width (posedge clk, 0, 0, notifier); + $width (negedge clk, 0, 0, notifier); + $period (posedge clk, 0, notifier); + $setuphold (posedge clk, we_in, 0, 0, notifier); + $setuphold (posedge clk, ce_in, 0, 0, notifier); + $setuphold (posedge clk, addr_in, 0, 0, notifier); + $setuphold (posedge clk, wd_in, 0, 0, notifier); + endspecify + +endmodule +(* blackbox *) +module spsram_256x32 ( + output reg [31:0] rd_out, + input [7:0] addr_in, + input we_in, + input [31:0] wd_in, + input clk, + input ce_in +); +endmodule +library(spsram_256x32) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(spsram_256x32_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(spsram_256x32_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(spsram_256x32_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(spsram_256x32_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(spsram_256x32_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (spsram_256x32_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 32; + bit_from : 31; + bit_to : 0 ; + downto : true ; + } + type (spsram_256x32_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(spsram_256x32) { + area : 343.985; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 32; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(spsram_256x32_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(spsram_256x32_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : spsram_256x32_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(spsram_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(spsram_256x32_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(spsram_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(spsram_256x32_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : spsram_256x32_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : spsram_256x32_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(spsram_256x32_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(spsram_256x32_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/test/cfg/dprf_example.cfg b/test/cfg/dprf_example.cfg new file mode 100644 index 0000000..098bcc5 --- /dev/null +++ b/test/cfg/dprf_example.cfg @@ -0,0 +1,48 @@ +#SAMPLE INPUT FILE; VALUES NOT REALISTIC +{ + # The process node. + "tech_nm": 7, + + # The operating voltage. + "voltage": 0.7, + + # String to add in front of every metal layer number for the layer name. + "metal_prefix": "M", + + # Horizontal Metal layer for macro pins + "metal_layer": "M4", + + # The pin width for signal pins. + "pin_width_nm": 24, + + # The minimum pin pitch for signal pins + "pin_pitch_nm": 48, + + # Metal track pitch + "metal_track_pitch_nm": 48, + + # Manufacturing Grid + "manufacturing_grid_nm": 1, + + # Contacted Poly Pitch + "contacted_poly_pitch_nm": 54, + + #column mux factor + "column_mux_factor": 1, + + # Fin pitch + "fin_pitch_nm" : 27, + + # Optional snap the width and height of the sram to a multiple value. + "snap_width_nm": 190, + "snap_height_nm": 1400, + + "memory_type": "RF", + "port_configuration": "DP", + + # List of SRAM configurations (name width depth and banks) + "srams": [ + {"name": "dprf_256x32", "width": 32, "depth": 256, "banks": 2}, + {"name": "dprf_256x256", "width": 256, "depth": 256, "banks": 1} + ] +} diff --git a/test/cfg/dpsram_example.cfg b/test/cfg/dpsram_example.cfg new file mode 100644 index 0000000..c83ab2d --- /dev/null +++ b/test/cfg/dpsram_example.cfg @@ -0,0 +1,48 @@ +#SAMPLE INPUT FILE; VALUES NOT REALISTIC +{ + # The process node. + "tech_nm": 7, + + # The operating voltage. + "voltage": 0.7, + + # String to add in front of every metal layer number for the layer name. + "metal_prefix": "M", + + # Horizontal Metal layer for macro pins + "metal_layer": "M4", + + # The pin width for signal pins. + "pin_width_nm": 24, + + # The minimum pin pitch for signal pins + "pin_pitch_nm": 48, + + # Metal track pitch + "metal_track_pitch_nm": 48, + + # Manufacturing Grid + "manufacturing_grid_nm": 1, + + # Contacted Poly Pitch + "contacted_poly_pitch_nm": 54, + + #column mux factor + "column_mux_factor": 1, + + # Fin pitch + "fin_pitch_nm" : 27, + + # Optional snap the width and height of the sram to a multiple value. + "snap_width_nm": 190, + "snap_height_nm": 1400, + + "memory_type": "RAM", + "port_configuration": "DP", + + # List of SRAM configurations (name width depth and banks) + "srams": [ + {"name": "dpsram_256x32", "width": 32, "depth": 256, "banks": 2}, + {"name": "dpsram_256x256", "width": 256, "depth": 256, "banks": 1} + ] +} diff --git a/test/cfg/sprf_example.cfg b/test/cfg/sprf_example.cfg new file mode 100644 index 0000000..5f20eff --- /dev/null +++ b/test/cfg/sprf_example.cfg @@ -0,0 +1,48 @@ +#SAMPLE INPUT FILE; VALUES NOT REALISTIC +{ + # The process node. + "tech_nm": 7, + + # The operating voltage. + "voltage": 0.7, + + # String to add in front of every metal layer number for the layer name. + "metal_prefix": "M", + + # Horizontal Metal layer for macro pins + "metal_layer": "M4", + + # The pin width for signal pins. + "pin_width_nm": 24, + + # The minimum pin pitch for signal pins + "pin_pitch_nm": 48, + + # Metal track pitch + "metal_track_pitch_nm": 48, + + # Manufacturing Grid + "manufacturing_grid_nm": 1, + + # Contacted Poly Pitch + "contacted_poly_pitch_nm": 54, + + #column mux factor + "column_mux_factor": 1, + + # Fin pitch + "fin_pitch_nm" : 27, + + # Optional snap the width and height of the sram to a multiple value. + "snap_width_nm": 190, + "snap_height_nm": 1400, + + "memory_type": "RF", + "port_configuration": "SP", + + # List of SRAM configurations (name width depth and banks) + "srams": [ + {"name": "sprf_256x32", "width": 32, "depth": 256, "banks": 2}, + {"name": "sprf_256x256", "width": 256, "depth": 256, "banks": 1} + ] +} diff --git a/test/cfg/spsram_example.cfg b/test/cfg/spsram_example.cfg new file mode 100644 index 0000000..995fbc9 --- /dev/null +++ b/test/cfg/spsram_example.cfg @@ -0,0 +1,48 @@ +#SAMPLE INPUT FILE; VALUES NOT REALISTIC +{ + # The process node. + "tech_nm": 7, + + # The operating voltage. + "voltage": 0.7, + + # String to add in front of every metal layer number for the layer name. + "metal_prefix": "M", + + # Horizontal Metal layer for macro pins + "metal_layer": "M4", + + # The pin width for signal pins. + "pin_width_nm": 24, + + # The minimum pin pitch for signal pins + "pin_pitch_nm": 48, + + # Metal track pitch + "metal_track_pitch_nm": 48, + + # Manufacturing Grid + "manufacturing_grid_nm": 1, + + # Contacted Poly Pitch + "contacted_poly_pitch_nm": 54, + + #column mux factor + "column_mux_factor": 1, + + # Fin pitch + "fin_pitch_nm" : 27, + + # Optional snap the width and height of the sram to a multiple value. + "snap_width_nm": 190, + "snap_height_nm": 1400, + + "memory_type": "RAM", + "port_configuration": "SP", + + # List of SRAM configurations (name width depth and banks) + "srams": [ + {"name": "spsram_256x32", "width": 32, "depth": 256, "banks": 2}, + {"name": "spsram_256x256", "width": 256, "depth": 256, "banks": 1} + ] +} diff --git a/test/dprf_flow_test.py b/test/dprf_flow_test.py new file mode 100755 index 0000000..f76e54b --- /dev/null +++ b/test/dprf_flow_test.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 + +import os +import shutil +import unittest +import subprocess + +from flow_test_base import FlowTestBase + + +class DPRFFlowTest(FlowTestBase): + """Flow test for dual port reg file""" + + def setUp(self): + """Sets up paths to validate results""" + self._tag = "dprf" + FlowTestBase.set_up(self, self._tag) + + def test_example_input(self): + """Tests the example input run""" + + expected_ram_list = [ + "dprf_256x256", + "dprf_256x32", + ] + self._execute_run(self._tag, expected_ram_list) + + +if __name__ == "__main__": + unittest.main() diff --git a/test/dpsram_flow_test.py b/test/dpsram_flow_test.py new file mode 100755 index 0000000..b557dc1 --- /dev/null +++ b/test/dpsram_flow_test.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 + +import os +import shutil +import unittest +import subprocess + +from flow_test_base import FlowTestBase + + +class DPSRAMFlowTest(FlowTestBase): + """Flow test for dual port RAM""" + + def setUp(self): + """Sets up paths to validate results""" + self._tag = "dpsram" + FlowTestBase.set_up(self, self._tag) + + def test_example_input(self): + """Tests the example input run""" + + expected_ram_list = [ + "dpsram_256x256", + "dpsram_256x32", + ] + self._execute_run(self._tag, expected_ram_list) + + +if __name__ == "__main__": + unittest.main() diff --git a/test/factory_base_test.py b/test/factory_base_test.py new file mode 100755 index 0000000..5f262a5 --- /dev/null +++ b/test/factory_base_test.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python3 + +import os +import sys +import unittest + +sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "utils"))) +from factory_base import FactoryBase + + +class DPRAM: + """Test class for DPRAM""" + + def __init__(self, name, width_in_bits, depth, num_banks, process, timing_data): + pass + + def get_type(self): + return "DPRAM" + + +class SPRAM: + """Test class for SPRAM""" + + def __init__(self, name, width_in_bits, depth, num_banks, process, timing_data): + pass + + def get_type(self): + return "SPRAM" + + +class FactoryBaseTest(unittest.TestCase): + """Unit test for FactoryBase class""" + + def setUp(self): + """Sets up factory by registering two types of SRAMs""" + FactoryBase.register("RAM", "DP", DPRAM) + FactoryBase.register("RAM", "SP", SPRAM) + + def test_basic(self): + """Tests calling factory with existent and non existent keys""" + width = 32 + depth = 256 + banks = 2 + dpram = FactoryBase.create( + "dpram", width, depth, banks, "RAM", "DP", None, None + ) + self.assertIsNotNone(dpram) + self.assertEqual(dpram.get_type(), "DPRAM") + spram = FactoryBase.create( + "spram", width, depth, banks, "RAM", "SP", None, None + ) + self.assertIsNotNone(spram) + self.assertEqual(spram.get_type(), "SPRAM") + # SP RF is not registered, so raise exception + with self.assertRaises(Exception): + sprf = FactoryBase.create( + "sprf", width, depth, banks, "RF", "SP", None, None + ) + + +if __name__ == "__main__": + unittest.main() diff --git a/test/flow_test.py b/test/flow_test.py index a9a1ab7..aa63ac9 100755 --- a/test/flow_test.py +++ b/test/flow_test.py @@ -6,6 +6,7 @@ import shutil import unittest import subprocess +from test_utils import TestUtils class FlowTest(unittest.TestCase): @@ -215,8 +216,9 @@ def _checkResultsDir(self): def test_example_input(self): """Tests the example input run""" + exec_cmd = TestUtils.get_exec_name(self._exec) cmd = ( - self._exec + exec_cmd + " " + os.path.join(self._script_dir, "example_input_file.cfg") + " --output_dir " diff --git a/test/flow_test_base.py b/test/flow_test_base.py new file mode 100644 index 0000000..01f1f6a --- /dev/null +++ b/test/flow_test_base.py @@ -0,0 +1,70 @@ +#!/usr/bin/env python3 + +import os +import shutil +import unittest +import subprocess +from test_utils import TestUtils + + +class FlowTestBase(unittest.TestCase): + """Flow test base class""" + + def set_up(self, tag): + result_dir = f"{tag}_results" + self._test_dir = os.path.abspath(os.path.dirname(__file__)) + self._script_dir = os.path.abspath(os.path.join(self._test_dir, "..")) + self._golden_dir = os.path.abspath(os.path.join(self._test_dir, "au")) + self._exec = os.path.join(self._script_dir, "run.py") + self._results_dir = os.path.join(self._test_dir, result_dir) + if os.path.isdir(self._results_dir): + shutil.rmtree(self._results_dir) + + def _compare_golden( + self, ram_name, lef_file, verilog_file, sv_blackbox_file, liberty_file + ): + temp_file = os.path.join(self._results_dir, ram_name + ".out") + golden_file = os.path.join(self._golden_dir, ram_name + ".au") + cmd = f"cat {lef_file} {verilog_file} {sv_blackbox_file} {liberty_file} | grep -v date > {temp_file}" + out = subprocess.run(cmd, check=True, shell=True) + self.assertEqual(out.returncode, 0) + cmd = f"cmp {temp_file} {golden_file}" + out = subprocess.run(cmd, check=True, shell=True) + self.assertEqual(out.returncode, 0) + + def _check_memory(self, ram_name): + lef_file = os.path.join(self._results_dir, ram_name, ram_name + ".lef") + verilog_file = os.path.join(self._results_dir, ram_name, ram_name + ".v") + sv_blackbox_file = os.path.join(self._results_dir, ram_name, ram_name + ".sv") + liberty_file = os.path.join(self._results_dir, ram_name, ram_name + ".lib") + self.assertTrue(os.path.exists(lef_file), f"{lef_file} doesn't exist") + self.assertTrue(os.path.exists(verilog_file), f"{verilog_file} doesn't exist") + self.assertTrue( + os.path.exists(sv_blackbox_file), f"{sv_blackbox_file} doesn't exist" + ) + self.assertTrue(os.path.exists(liberty_file), f"{liberty_file} doesn't exist") + self._compare_golden( + ram_name, lef_file, verilog_file, sv_blackbox_file, liberty_file + ) + + def _check_results_dir(self, expected_ram_list): + """Checks that the expected RAMs were generated""" + self.assertTrue(os.path.isdir(self._results_dir)) + self.assertListEqual(sorted(os.listdir(self._results_dir)), expected_ram_list) + for ram_name in expected_ram_list: + self._check_memory(ram_name) + + def _execute_run(self, tag, expected_ram_list): + cfg_file_name = f"{tag}_example.cfg" + + exec_cmd = TestUtils.get_exec_name(self._exec) + cmd = ( + exec_cmd + + " " + + os.path.join(self._test_dir, "cfg", cfg_file_name) + + " --output_dir " + + self._results_dir + ) + out = subprocess.run(cmd, check=True, shell=True) + self.assertEqual(out.returncode, 0) + self._check_results_dir(expected_ram_list) diff --git a/test/macro_dim_test.py b/test/macro_dim_test.py index cb50e43..f3c04bb 100755 --- a/test/macro_dim_test.py +++ b/test/macro_dim_test.py @@ -7,7 +7,6 @@ sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "utils"))) from class_process import Process from test_utils import TestUtils -import area class MacroDimTest(unittest.TestCase): @@ -35,9 +34,12 @@ def test_macro_dim(self): "depth": 2048, "banks": num_banks, } - (height, width) = area.get_macro_dimensions(self._process, sram_data) + (width, height) = self._process.get_macro_dimensions( + sram_data["width"], sram_data["depth"], sram_data["banks"] + ) exp_height = base_height / num_banks exp_width = base_width * num_banks + self.assertFalse(self._process.has_defined_bitcell_size()) self.assertAlmostEqual(height, exp_height, delta=self._delta) self.assertAlmostEqual(width, exp_width, delta=self._delta) @@ -50,7 +52,34 @@ def test_macro_dim_invalid_banks(self): "banks": 8, } with self.assertRaises(Exception): - (height, width) = area.get_macro_dimensions(self._process, sram_data) + (width, height) = self._process.get_macro_dimensions( + sram_data["width"], sram_data["depth"], sram_data["banks"] + ) + + def test_macro_dim_bitcell_override(self): + """Tests when bitcell dimensions are provided""" + + process_data = TestUtils.get_base_process_data().copy() + process_data["bitcell_width_um"] = 123.0 + process_data["bitcell_height_um"] = 456.0 + process = Process(process_data) + + sram_data = { + "width": 32, + "depth": 256, + "banks": 1, + } + exp_width = 4723.2 + exp_height = 140083.2 + (width, height) = process.get_macro_dimensions( + sram_data["width"], sram_data["depth"], sram_data["banks"] + ) + self.assertTrue(process.has_defined_bitcell_size()) + (bitcell_width, bitcell_height) = process.get_bitcell_dimensions() + self.assertEqual(bitcell_width, process_data["bitcell_width_um"]) + self.assertEqual(bitcell_height, process_data["bitcell_height_um"]) + self.assertAlmostEqual(width, exp_width, delta=self._delta) + self.assertAlmostEqual(height, exp_height, delta=self._delta) if __name__ == "__main__": diff --git a/test/memory_factory_test.py b/test/memory_factory_test.py new file mode 100755 index 0000000..8dfc59c --- /dev/null +++ b/test/memory_factory_test.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 + +import os +import sys +import unittest + +sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "utils"))) +from class_process import Process +from memory_factory import MemoryFactory +from timing_data import TimingData +from test_utils import TestUtils + + +class MemoryFactoryTest(unittest.TestCase): + """Unit test for MemoryFactory object""" + + def setUp(self): + """Sets up process object used by test methods""" + + self._process = Process(TestUtils.get_base_process_data()) + self._timing_data = TimingData() + + def test_basic(self): + """ + Tests basic operations + """ + + timing_data = TimingData() + for memory_type in ["RAM", "RF"]: + for port_config in ["SP", "DP"]: + name = (f"{port_config}{memory_type}",) + memory = MemoryFactory.create( + name, + 32, + 256, + 1, + memory_type, + port_config, + self._process, + timing_data, + ) + self.assertIsNotNone(memory) + self.assertEqual(memory.get_name(), name) + with self.assertRaises(Exception): + memory = MemoryFactory.create( + bogus, 32, 256, 1, "unknown", "unknown", self._process, timing_data + ) + + +if __name__ == "__main__": + unittest.main() diff --git a/test/memory_test.py b/test/memory_test.py index 8d1e821..1821c04 100755 --- a/test/memory_test.py +++ b/test/memory_test.py @@ -8,6 +8,8 @@ sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "utils"))) from class_memory import Memory from class_process import Process +from memory_factory import MemoryFactory +from timing_data import TimingData from test_utils import TestUtils @@ -32,31 +34,48 @@ def test_memory(self): Tests basic memory object """ - memory = Memory(self._process, self._sram_data) - self.assertEqual(memory.name, self._sram_data["name"]) - self.assertEqual(memory.width_in_bits, self._sram_data["width"]) - self.assertEqual(memory.depth, self._sram_data["depth"]) - self.assertEqual(memory.num_banks, self._sram_data["banks"]) - self.assertEqual(memory.cache_type, "cache") - self.assertEqual(memory.width_in_bytes, math.ceil(memory.width_in_bits / 8.0)) - self.assertEqual(memory.total_size, memory.width_in_bytes * memory.depth) - # the area is calculated prior to snapping, so check that the area is - # within some area determined by the snap area + timing_data = TimingData() + memory = MemoryFactory.create( + self._sram_data["name"], + self._sram_data["width"], + self._sram_data["depth"], + self._sram_data["banks"], + "RAM", + "SP", + self._process, + timing_data, + ) + self.assertEqual(memory.get_name(), self._sram_data["name"]) + self.assertEqual(memory.get_width(), self._sram_data["width"]) + self.assertEqual(memory.get_depth(), self._sram_data["depth"]) + self.assertEqual(memory.get_num_banks(), self._sram_data["banks"]) + self.assertEqual( + memory.get_width_in_bytes(), math.ceil(memory.get_width() / 8.0) + ) + self.assertEqual( + memory.get_total_size(), memory.get_width_in_bytes() * memory.get_depth() + ) + # the area used by Liberty is calculated prior to snapping, so check + # that the area is within some delta determined by the snap area area_delta = self._process.snap_width_nm * self._process.snap_height_nm * 1e-3 + physical = memory.get_physical_data() self.assertAlmostEqual( - memory.area_um2, memory.width_um * memory.height_um, delta=area_delta + physical.get_area(False), + physical.get_width() * physical.get_height(), + delta=area_delta, ) # These values are all hard-coded in the Memory object - self.assertEqual(memory.rw_ports, 1) - self.assertEqual(memory.t_setup_ns, 0.05) - self.assertEqual(memory.t_hold_ns, 0.05) - self.assertEqual(memory.standby_leakage_per_bank_mW, 0.1289) - self.assertEqual(memory.access_time_ns, 0.2183) - self.assertEqual(memory.pin_dynamic_power_mW, 0.0013449) - self.assertEqual(memory.cap_input_pf, 0.005) - self.assertEqual(memory.cycle_time_ns, 0.1566) - self.assertEqual(memory.fo4_ps, 9.0632) + timing_data = memory.get_timing_data() + self.assertEqual(memory.get_num_rw_ports(), 1) + self.assertEqual(timing_data.t_setup_ns, 0.05) + self.assertEqual(timing_data.t_hold_ns, 0.05) + self.assertEqual(timing_data.standby_leakage_per_bank_mW, 0.1289) + self.assertEqual(timing_data.access_time_ns, 0.2183) + self.assertEqual(timing_data.pin_dynamic_power_mW, 0.0013449) + self.assertEqual(timing_data.cap_input_pf, 0.005) + self.assertEqual(timing_data.cycle_time_ns, 0.1566) + self.assertEqual(timing_data.fo4_ps, 9.0632) if __name__ == "__main__": diff --git a/test/physical_test.py b/test/physical_test.py new file mode 100755 index 0000000..ccff5a4 --- /dev/null +++ b/test/physical_test.py @@ -0,0 +1,85 @@ +#!/usr/bin/env python3 + +import os +import sys +import math +import unittest + +sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "utils"))) +from physical_data import PhysicalData + + +class PhysicalDataTest(unittest.TestCase): + """Unit test for PhysicalData class""" + + def setUp(self): + """Sets up base_data with example config data""" + + + def test_empty_physical(self): + """Tests physical field defaults""" + + physical = PhysicalData() + self.assertIsNone(physical.get_width()) + self.assertIsNone(physical.get_height()) + self.assertIsNone(physical.get_width(True)) + self.assertIsNone(physical.get_height(True)) + self.assertIsNone(physical.get_pin_pitch()) + self.assertIsNone(physical.get_group_pitch()) + + def test_set_extents_and_snapping(self): + """Tests physical field defaults""" + + physical = PhysicalData() + width = 123.4 + height = 456.5 + snapped_width = math.ceil(width) + snapped_height = math.ceil(height) + + # Can't snap before setting extents + with self.assertRaises(Exception): + physical.snap_to_grid(1000, 1000) + + # Set extents and verify values + physical.set_extents(width, height) + self.assertEqual(physical.get_width(False), width) + self.assertEqual(physical.get_height(False), height) + self.assertEqual(physical.get_area(False), width * height) + # Not snapped yet, so should return non-snapped value + self.assertEqual(physical.get_width(True), width) + self.assertEqual(physical.get_height(True), height) + self.assertEqual(physical.get_area(True), width * height) + + # Snap to 1um + physical.snap_to_grid(1000, 1000) + + # Non-snapped should return original + self.assertEqual(physical.get_width(False), width) + self.assertEqual(physical.get_height(False), height) + self.assertEqual(physical.get_area(False), width * height) + self.assertEqual(physical.get_width(True), snapped_width) + self.assertEqual(physical.get_height(True), snapped_height) + self.assertEqual(physical.get_area(True), snapped_width * snapped_height) + + def test_pin_pitches_exception(self): + """Tests get_pin_pitches when there's no enough room for the pins""" + + num_pins = 523 + min_pin_pitch = 0.048 + y_offset = 0.048 + height = 21.0 + physical = PhysicalData() + + # Can't set pin pitches before setting height + with self.assertRaises(Exception): + physical.set_pin_pitches("bogus", num_pins, min_pin_pitch, y_offset) + + # Try again after setting height + physical.set_extents(height, height) + physical.snap_to_grid(1, 1) + with self.assertRaises(Exception): + physical.set_pin_pitches("bogus", num_pins, min_pin_pitch, y_offset) + + +if __name__ == "__main__": + unittest.main() diff --git a/test/process_test.py b/test/process_test.py index 8c6b9f5..15b2f8b 100755 --- a/test/process_test.py +++ b/test/process_test.py @@ -35,34 +35,47 @@ def test_process(self): process = Process(self._base_data) self.assertIsNotNone(process) - self.assertEqual(process.tech_nm, self._base_data["tech_nm"]) - self.assertTrue(isinstance(process.voltage, str)) - self.assertEqual(process.voltage, str(self._base_data["voltage"])) - self.assertEqual(process.metal_prefix, self._base_data["metal_prefix"]) - self.assertEqual(process.metal_layer, self._base_data["metal_layer"]) - self.assertEqual(process.pin_width_nm, self._base_data["pin_width_nm"]) - self.assertEqual(process.pin_pitch_nm, self._base_data["pin_pitch_nm"]) + self.assertEqual(process.get_tech_nm(), self._base_data["tech_nm"]) + self.assertTrue(isinstance(process.get_voltage(), float)) + self.assertEqual(process.get_voltage(), self._base_data["voltage"]) + self.assertEqual(process.get_metal_prefix(), self._base_data["metal_prefix"]) + self.assertEqual(process.get_metal_layer(), self._base_data["metal_layer"]) + self.assertEqual(process.get_pin_width_nm(), self._base_data["pin_width_nm"]) + self.assertEqual(process.get_pin_pitch_nm(), self._base_data["pin_pitch_nm"]) self.assertEqual( - process.metal_track_pitch_nm, self._base_data["metal_track_pitch_nm"] + process.get_metal_track_pitch_nm(), self._base_data["metal_track_pitch_nm"] ) self.assertEqual( - process.contacted_poly_pitch_nm, self._base_data["contacted_poly_pitch_nm"] + process.get_contacted_poly_pitch(), + self._base_data["contacted_poly_pitch_nm"], ) - self.assertEqual(process.fin_pitch_nm, self._base_data["fin_pitch_nm"]) + self.assertEqual(process.get_fin_pitch(), self._base_data["fin_pitch_nm"]) self.assertEqual( - process.manufacturing_grid_nm, self._base_data["manufacturing_grid_nm"] + process.get_manufacturing_grid_nm(), + self._base_data["manufacturing_grid_nm"], + ) + self.assertEqual(process.get_snap_width_nm(), self._base_data["snap_width_nm"]) + self.assertEqual( + process.get_snap_height_nm(), self._base_data["snap_height_nm"] ) - self.assertEqual(process.snap_width_nm, self._base_data["snap_width_nm"]) - self.assertEqual(process.snap_height_nm, self._base_data["snap_height_nm"]) # check nm -> um - self.assertEqual(process.tech_um, process.tech_nm / 1000.0) - self.assertEqual(process.pin_width_um, process.pin_width_nm / 1000.0) - self.assertEqual(process.pin_pitch_um, process.pin_pitch_nm / 1000.0) + self.assertEqual(process.get_tech_um(), process.get_tech_nm() / 1000.0) + self.assertEqual( + process.get_pin_width_um(), process.get_pin_width_nm() / 1000.0 + ) + self.assertEqual( + process.get_pin_pitch_um(), process.get_pin_pitch_nm() / 1000.0 + ) + self.assertEqual( + process.get_metal_track_pitch_um(), + process.get_metal_track_pitch_nm() / 1000.0, + ) self.assertEqual( - process.metal_track_pitch_um, process.metal_track_pitch_nm / 1000.0 + process.get_manufacturing_grid_um(), + process.get_manufacturing_grid_nm() / 1000.0, ) self.assertEqual( - process.manufacturing_grid_um, process.manufacturing_grid_nm / 1000.0 + process.get_column_mux_factor(), self._base_data["column_mux_factor"] ) def test_process_optional_snap(self): @@ -72,24 +85,34 @@ def test_process_optional_snap(self): del process_data["snap_width_nm"] del process_data["snap_height_nm"] process = Process(process_data) - self.assertEqual(process.tech_nm, self._base_data["tech_nm"]) - self.assertEqual(process.voltage, str(self._base_data["voltage"])) - self.assertEqual(process.metal_prefix, self._base_data["metal_prefix"]) - self.assertEqual(process.metal_layer, self._base_data["metal_layer"]) - self.assertEqual(process.pin_width_nm, self._base_data["pin_width_nm"]) - self.assertEqual(process.pin_pitch_nm, self._base_data["pin_pitch_nm"]) + self.assertEqual(process.get_tech_nm(), self._base_data["tech_nm"]) + self.assertEqual(process.get_voltage(), float(self._base_data["voltage"])) + self.assertEqual(process.get_metal_prefix(), self._base_data["metal_prefix"]) + self.assertEqual(process.get_metal_layer(), self._base_data["metal_layer"]) + self.assertEqual(process.get_pin_width_nm(), self._base_data["pin_width_nm"]) + self.assertEqual(process.get_pin_pitch_nm(), self._base_data["pin_pitch_nm"]) self.assertEqual( - process.metal_track_pitch_nm, self._base_data["metal_track_pitch_nm"] + process.get_metal_track_pitch_nm(), self._base_data["metal_track_pitch_nm"] ) self.assertEqual( - process.contacted_poly_pitch_nm, self._base_data["contacted_poly_pitch_nm"] + process.get_contacted_poly_pitch(), + self._base_data["contacted_poly_pitch_nm"], ) - self.assertEqual(process.fin_pitch_nm, self._base_data["fin_pitch_nm"]) + self.assertEqual(process.get_fin_pitch(), self._base_data["fin_pitch_nm"]) self.assertEqual( - process.manufacturing_grid_nm, self._base_data["manufacturing_grid_nm"] + process.get_manufacturing_grid_nm(), + self._base_data["manufacturing_grid_nm"], + ) + self.assertEqual(process.get_snap_width_nm(), 1) + self.assertEqual(process.get_snap_height_nm(), 1) + self.assertEqual(process.get_x_offset(), process.get_pin_pitch_um()) + self.assertEqual(process.get_y_offset(), process.get_pin_pitch_um()) + self.assertEqual( + process.get_y_step(), + process.get_y_offset() + - (process.get_y_offset() % process.get_manufacturing_grid_um()) + + (process.get_pin_width_um() / 2.0), ) - self.assertEqual(process.snap_width_nm, 1) - self.assertEqual(process.snap_height_nm, 1) def test_process_misaligned_pin_mfg_grid_pitch(self): """ @@ -117,6 +140,19 @@ def test_process_misaligned_pin_track_pitch(self): with self.assertRaises(Exception): process = Process(process_data) + def test_bitcell_override(self): + """Tests when bitcell size overrides computation""" + + process_data = self._base_data.copy() + process_data["bitcell_width_um"] = 123.0 + process_data["bitcell_height_um"] = 456.0 + process = Process(process_data) + + self.assertTrue(process.has_defined_bitcell_size()) + (bitcell_width, bitcell_height) = process.get_bitcell_dimensions() + self.assertEqual(bitcell_width, process_data["bitcell_width_um"]) + self.assertEqual(bitcell_height, process_data["bitcell_height_um"]) + if __name__ == "__main__": unittest.main() diff --git a/test/sprf_flow_test.py b/test/sprf_flow_test.py new file mode 100755 index 0000000..3e6357e --- /dev/null +++ b/test/sprf_flow_test.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 + +import os +import shutil +import unittest +import subprocess + +from flow_test_base import FlowTestBase + + +class SPRFFlowTest(FlowTestBase): + """Flow test for single port reg file""" + + def setUp(self): + """Sets up paths to validate results""" + self._tag = "sprf" + FlowTestBase.set_up(self, self._tag) + + def test_example_input(self): + """Tests the example input run""" + + expected_ram_list = [ + "sprf_256x256", + "sprf_256x32", + ] + self._execute_run(self._tag, expected_ram_list) + + +if __name__ == "__main__": + unittest.main() diff --git a/test/spsram_flow_test.py b/test/spsram_flow_test.py new file mode 100755 index 0000000..09f581d --- /dev/null +++ b/test/spsram_flow_test.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 + +import os +import shutil +import unittest +import subprocess + +from flow_test_base import FlowTestBase + + +class SPSRAMFlowTest(FlowTestBase): + """Flow test for single port RAM""" + + def setUp(self): + """Sets up paths to validate results""" + self._tag = "spsram" + FlowTestBase.set_up(self, self._tag) + + def test_example_input(self): + """Tests the example input run""" + + expected_ram_list = [ + "spsram_256x256", + "spsram_256x32", + ] + self._execute_run(self._tag, expected_ram_list) + + +if __name__ == "__main__": + unittest.main() diff --git a/test/test_all.sh b/test/test_all.sh index 427fd1c..290600b 100755 --- a/test/test_all.sh +++ b/test/test_all.sh @@ -2,8 +2,20 @@ set -eoux pipefail +if [[ -v COVERAGE_RUN ]]; then + rm -rf .coverage* + cmd_preamble="coverage run --parallel-mode" +else + cmd_preamble="" +fi + SCRIPT_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) for test_file in $SCRIPT_DIR/*_test.py; do - $test_file + $cmd_preamble $test_file done + +if [[ -v COVERAGE_RUN ]]; then + coverage combine +fi + diff --git a/test/test_utils.py b/test/test_utils.py index e1a9ced..2a97b8f 100755 --- a/test/test_utils.py +++ b/test/test_utils.py @@ -1,5 +1,6 @@ #!/usr/bin/env python3 +import os class TestUtils: @staticmethod @@ -20,3 +21,17 @@ def get_base_process_data(): "snap_width_nm": 190, "snap_height_nm": 1400, } + + @staticmethod + def get_exec_name(exec_name): + """ + Returns the exec name, which includes the coverage command, if + coverage is enabled + """ + + if "COVERAGE_RUN" in os.environ: + exec_cmd = "coverage run --parallel-mode " + exec_name + else: #pragma: nocover + exec_cmd = exec_name + return exec_cmd + diff --git a/test/timing_data_test.py b/test/timing_data_test.py new file mode 100755 index 0000000..7979cf3 --- /dev/null +++ b/test/timing_data_test.py @@ -0,0 +1,126 @@ +#!/usr/bin/env python3 + +import os +import sys +import unittest + +sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "utils"))) +from timing_data import TimingData + + +class TimingDataTest(unittest.TestCase): + """Unit test for TimingData class""" + + def setUp(self): + pass + + def check_caps_loads(self, timing_data, input_cap): + self.assertEqual(timing_data.get_input_cap(), input_cap) + self.assertEqual(timing_data.get_min_driver_input_cap(), input_cap) + min_load = timing_data.get_min_load() + max_load = timing_data.get_max_load() + self.assertEqual(min_load, input_cap) + self.assertEqual(max_load, input_cap * 100) + self.assertEqual( + timing_data.get_load_indices_str(), f"{min_load:.3f}, {max_load:.3f}" + ) + + def check_fo4_vals(self, timing_data, fo4_ps): + self.assertEqual(timing_data.get_fo4_ps(), fo4_ps) + self.assertEqual(timing_data.get_fo4(), fo4_ps * 1e-3) + min_slew = timing_data.get_min_slew() + max_slew = timing_data.get_max_slew() + self.assertEqual(min_slew, fo4_ps * 1e-3) + self.assertEqual(max_slew, fo4_ps * 1e-3 * 25) + self.assertEqual( + timing_data.get_slew_indices_str(), f"{min_slew:.3f}, {max_slew:.3f}" + ) + + def check_leakage_vals(self, timing_data, mw_val): + self.assertEqual(timing_data.get_leakage_power_per_bank(), mw_val) + self.assertEqual(timing_data.get_leakage_power(), mw_val * 1e3) + + def check_pin_dynamic_power_vals(self, timing_data, mw_val): + self.assertEqual(timing_data.get_clkpin_dynamic_power(), mw_val * 1e3) + self.assertEqual(timing_data.get_pin_dynamic_power(), mw_val * 1e1) + self.assertEqual(timing_data.get_pin_dynamic_power_mw(), mw_val) + + def test_asap7(self): + """Tests process fields based on asap7 defaults""" + + timing_data = TimingData(None) + self.assertIsNotNone(timing_data) + self.assertEqual( + timing_data.get_setup_time(), timing_data._asap7_defaults["t_setup_ns"] + ) + self.assertEqual( + timing_data.get_hold_time(), timing_data._asap7_defaults["t_hold_ns"] + ) + self.assertEqual( + timing_data.get_access_time(), timing_data._asap7_defaults["access_time_ns"] + ) + self.assertEqual( + timing_data.get_cycle_time(), timing_data._asap7_defaults["cycle_time_ns"] + ) + self.check_leakage_vals( + timing_data, timing_data._asap7_defaults["standby_leakage_per_bank_mW"] + ) + self.check_pin_dynamic_power_vals( + timing_data, timing_data._asap7_defaults["pin_dynamic_power_mW"] + ) + self.check_caps_loads(timing_data, timing_data._asap7_defaults["cap_input_pf"]) + self.check_fo4_vals(timing_data, timing_data._asap7_defaults["fo4_ps"]) + + def test_full_override(self): + """Tests when all input values are overridden""" + + new_data = { + "t_setup_ns": 0.99, + "t_hold_ns": 0.123, + "standby_leakage_per_bank_mW": 0.456, + "access_time_ns": 0.9745, + "pin_dynamic_power_mW": 3.1415, + "cap_input_pf": 0.009, + "cycle_time_ns": 0.664, + "fo4_ps": 10.0, + } + timing_data = TimingData(new_data) + self.assertIsNotNone(timing_data) + self.assertEqual(timing_data.get_setup_time(), new_data["t_setup_ns"]) + self.assertEqual(timing_data.get_hold_time(), new_data["t_hold_ns"]) + self.assertEqual(timing_data.get_access_time(), new_data["access_time_ns"]) + self.assertEqual(timing_data.get_cycle_time(), new_data["cycle_time_ns"]) + self.check_leakage_vals(timing_data, new_data["standby_leakage_per_bank_mW"]) + self.check_pin_dynamic_power_vals(timing_data, new_data["pin_dynamic_power_mW"]) + self.check_caps_loads(timing_data, new_data["cap_input_pf"]) + self.check_fo4_vals(timing_data, new_data["fo4_ps"]) + + def test_partial_override(self): + """Tests when only some of the values are overridden""" + + new_data = { + "t_setup_ns": 0.99, + "t_hold_ns": 0.123, + } + timing_data = TimingData(new_data) + self.assertIsNotNone(timing_data) + self.assertEqual(timing_data.get_setup_time(), new_data["t_setup_ns"]) + self.assertEqual(timing_data.get_hold_time(), new_data["t_hold_ns"]) + self.assertEqual( + timing_data.get_access_time(), timing_data._asap7_defaults["access_time_ns"] + ) + self.assertEqual( + timing_data.get_cycle_time(), timing_data._asap7_defaults["cycle_time_ns"] + ) + self.check_leakage_vals( + timing_data, timing_data._asap7_defaults["standby_leakage_per_bank_mW"] + ) + self.check_pin_dynamic_power_vals( + timing_data, timing_data._asap7_defaults["pin_dynamic_power_mW"] + ) + self.check_caps_loads(timing_data, timing_data._asap7_defaults["cap_input_pf"]) + self.check_fo4_vals(timing_data, timing_data._asap7_defaults["fo4_ps"]) + + +if __name__ == "__main__": + unittest.main() diff --git a/utils/area.py b/utils/area.py deleted file mode 100644 index 7dfafda..0000000 --- a/utils/area.py +++ /dev/null @@ -1,33 +0,0 @@ -import os -import sys -import math - - -def get_macro_dimensions(process, sram_data): - contacted_poly_pitch_um = process.contacted_poly_pitch_nm / 1000 - column_mux_factor = process.column_mux_factor - fin_pitch_um = process.fin_pitch_nm / 1000 - width_in_bits = int(sram_data["width"]) - depth = int(sram_data["depth"]) - num_banks = int(sram_data["banks"]) - - # Corresponds to the recommended 122 cell in asap7 - bitcell_height = 10 * fin_pitch_um - bitcell_width = 2 * contacted_poly_pitch_um - - all_bitcell_height = bitcell_height * depth - all_bitcell_width = bitcell_width * width_in_bits - - if num_banks == 2 or num_banks == 4: - all_bitcell_height = all_bitcell_height / num_banks - all_bitcell_width = all_bitcell_width * num_banks - elif num_banks != 1: - raise Exception("Unsupported number of banks: {}".format(num_banks)) - - all_bitcell_height = all_bitcell_height / column_mux_factor - all_bitcell_width = all_bitcell_width * column_mux_factor - - total_height = all_bitcell_height * 1.2 - total_width = all_bitcell_width * 1.2 - - return total_height, total_width diff --git a/utils/class_memory.py b/utils/class_memory.py index 1609f25..09683eb 100644 --- a/utils/class_memory.py +++ b/utils/class_memory.py @@ -1,8 +1,10 @@ -import os -import sys +#!/usr/bin/env python3 + import math +import argparse -from area import get_macro_dimensions +from physical_data import PhysicalData +from lef_exporter import LefExporter ################################################################################ # MEMORY CLASS @@ -14,43 +16,144 @@ class Memory: + def __init__(self, name, width_in_bits, depth, num_banks, process, timing_data): + """ + Initializer - def __init__(self, process, sram_data): + Stores the process and timing_data objects directly on the memory, so + that they can be accessed by the appropriate exporters. The physical + data stores anything related to LEF. + """ self.process = process - self.name = str(sram_data["name"]) - self.width_in_bits = int(sram_data["width"]) - self.depth = int(sram_data["depth"]) - self.num_banks = int(sram_data["banks"]) - self.cache_type = str(sram_data["type"]) if "type" in sram_data else "cache" - self.rw_ports = 1 + self.name = name + self.width_in_bits = width_in_bits + self.depth = depth + self.addr_width = math.ceil(math.log2(self.depth)) + self.num_banks = num_banks self.width_in_bytes = math.ceil(self.width_in_bits / 8.0) self.total_size = self.width_in_bytes * self.depth - - self.height_um, self.width_um = get_macro_dimensions(process, sram_data) - self.area_um2 = self.width_um * self.height_um - - # Adjust to snap - self.width_um = ( - math.ceil((self.width_um * 1000.0) / self.process.snap_width_nm) - * self.process.snap_width_nm - ) / 1000.0 - self.height_um = ( - math.ceil((self.height_um * 1000.0) / self.process.snap_height_nm) - * self.process.snap_height_nm - ) / 1000.0 + self.timing_data = timing_data + self.physical = PhysicalData() + (width_um, height_um) = self.process.get_macro_dimensions( + self.width_in_bits, self.depth, self.num_banks + ) + self.physical.set_extents(width_um, height_um) + self.physical.snap_to_grid( + self.process.snap_width_nm, self.process.snap_height_nm + ) if False: # pragma: no cover print("Total Bitcell Height is", self.height_um) print("Total Bitcell Width is", self.width_um) + num_pins = self.get_num_pins() + self.physical.set_pin_pitches( + self.name, num_pins, self.process.pin_pitch_um, self.process.y_offset + ) + + def get_name(self): + """Returns the name of the memory""" + return self.name + + def get_depth(self): + """Returns the depth""" + return self.depth + + def get_width(self): + """Returns the width in bits""" + return self.width_in_bits + + def get_num_banks(self): + """Returns the number of banks""" + return self.num_banks + + def get_width_in_bytes(self): + """Returns the width in bytes""" + return self.width_in_bytes + + def get_total_size(self): + """Returns the total size in bytes""" + return self.total_size + + def get_data_bus_msb(self): + """ + Returns the data bus MSB, which is one less than the data bus width + """ + return self.get_width() - 1 + + def get_addr_width(self): + """Returns the address width""" + return self.addr_width + + def get_addr_bus_msb(self): + """ + Returns the address bus MSB, which is one less than the address bus + width + """ + + return self.get_addr_width() - 1 + + def get_process_data(self): + """Returns the process data""" + return self.process + + def get_timing_data(self): + """Returns the timing data""" + return self.timing_data + + def get_physical_data(self): + """Returns the physical data""" + return self.physical + + def get_num_rw_ports(self): + """Returns the number of rw ports""" + return self.num_rw_ports + + def write_lef_file(self, out_file_name): + """Writes the LEF content to a file""" + + exporter = LefExporter(self) + exporter.export_file(out_file_name) + + @staticmethod + def main(memory_type, port_config): # pragma: nocover + from run_utils import RunUtils + from class_process import Process + from timing_data import TimingData + from memory_factory import MemoryFactory + + parser = argparse.ArgumentParser() + parser.add_argument( + "-c", "--config_file", help="FakeRAM config file", required=True + ) + parser.add_argument( + "-w", "--width", help="memory width in bits", type=int, required=True + ) + parser.add_argument( + "-d", "--depth", help="memory depth", type=int, required=True + ) + parser.add_argument( + "-b", + "--banks", + choices=[1, 2, 4], + type=int, + required=True, + help="number of banks", + ) + parser.add_argument("-n", "--name", help="memory name", required=True) + parser.add_argument("-o", "--output_dir", default=".", help="Output directory") + args = parser.parse_args() - ## DUMMY (FOR NOW) VALUES FOR LIB CREATION - self.t_setup_ns = 0.050 - # arbitrary 50ps setup - self.t_hold_ns = 0.050 - # arbitrary 50ps hold - self.standby_leakage_per_bank_mW = 0.1289 - self.access_time_ns = 0.2183 - self.pin_dynamic_power_mW = 0.0013449 - self.cap_input_pf = 0.005 - self.cycle_time_ns = 0.1566 - self.fo4_ps = 9.0632 + json_data = RunUtils.get_config(args.config_file) + timing_data = TimingData(json_data) + process_data = Process(json_data) + memory = MemoryFactory.create( + args.name, + int(args.width), + int(args.depth), + int(args.banks), + memory_type, + port_config, + process_data, + timing_data, + ) + RunUtils.write_memory(memory, args.output_dir) diff --git a/utils/class_process.py b/utils/class_process.py index 9ffcd57..bceedfc 100644 --- a/utils/class_process.py +++ b/utils/class_process.py @@ -6,18 +6,15 @@ # for the process comes from the json configuration file (typically before the # "sram" list section). ################################################################################ -import os -import sys -import math class Process: - def __init__(self, json_data): + """Initialize from json_data imported from config file""" # From JSON configuration file self.tech_nm = int(json_data["tech_nm"]) - self.voltage = str(json_data["voltage"]) + self.voltage = float(json_data["voltage"]) self.metal_prefix = str(json_data["metal_prefix"]) self.metal_layer = str(json_data["metal_layer"]) self.pin_width_nm = int(json_data["pin_width_nm"]) @@ -53,3 +50,147 @@ def __init__(self, json_data): "Pin Pitch %d not a multiple of Manufacturing Grid %d" % (self.pin_pitch_nm, self.manufacturing_grid_nm) ) + + # Offset from bottom edge to first pin + self.x_offset = 1 * self.pin_pitch_um + # as told by MSK + self.y_offset = 1 * self.pin_pitch_um + # as told by MSK + + self.y_step = ( + self.y_offset + - (self.y_offset % self.manufacturing_grid_um) + + (self.pin_width_um / 2.0) + ) + + if "bitcell_width_um" in json_data and "bitcell_height_um" in json_data: + self.bitcell_width_um = float(json_data["bitcell_width_um"]) + self.bitcell_height_um = float(json_data["bitcell_height_um"]) + else: + self.bitcell_width_um = self.bitcell_height_um = None + + def has_defined_bitcell_size(self): + return self.bitcell_width_um and self.bitcell_height_um + + def get_bitcell_dimensions(self): + if self.has_defined_bitcell_size(): + bitcell_width = self.bitcell_width_um + bitcell_height = self.bitcell_height_um + else: + contacted_poly_pitch_um = self.contacted_poly_pitch_nm / 1000 + fin_pitch_um = self.fin_pitch_nm / 1000 + + # Corresponds to the recommended 122 cell in asap7 + bitcell_height = 10 * fin_pitch_um + bitcell_width = 2 * contacted_poly_pitch_um + return (bitcell_width, bitcell_height) + + def get_macro_dimensions(self, width_in_bits, depth, num_banks): + """ + Returns the computed macro height & width based on the width/depth/banks + and process parameters + """ + + column_mux_factor = self.column_mux_factor + (bitcell_width, bitcell_height) = self.get_bitcell_dimensions() + + all_bitcell_height = bitcell_height * depth + all_bitcell_width = bitcell_width * width_in_bits + + if num_banks == 2 or num_banks == 4: + all_bitcell_height = all_bitcell_height / num_banks + all_bitcell_width = all_bitcell_width * num_banks + elif num_banks != 1: + raise Exception("Unsupported number of banks: {}".format(num_banks)) + + all_bitcell_height = all_bitcell_height / column_mux_factor + all_bitcell_width = all_bitcell_width * column_mux_factor + + total_height = all_bitcell_height * 1.2 + total_width = all_bitcell_width * 1.2 + + return (total_width, total_height) + + def get_tech_nm(self): + """Returns the process technology size in nm""" + return self.tech_nm + + def get_tech_um(self): + """Returns the process technology size in um""" + return self.tech_um + + def get_voltage(self): + """Returns the voltage in V""" + return self.voltage + + def get_metal_prefix(self): + """Returns the metal layer prefix string""" + return self.metal_prefix + + def get_metal_layer(self): + """Returns the metal layer string""" + return self.metal_layer + + def get_pin_width_nm(self): + """Returns the pin width in nm""" + return self.pin_width_nm + + def get_pin_width_um(self): + """Returns the pin width in um""" + return self.pin_width_um + + def get_pin_pitch_nm(self): + """Returns the pin pitch in nm""" + return self.pin_pitch_nm + + def get_pin_pitch_um(self): + """Returns the pin pitch in um""" + return self.pin_pitch_um + + def get_snap_width_nm(self): + """Returns the snap width in nm""" + return self.snap_width_nm + + def get_snap_height_nm(self): + """Returns the snap height in nm""" + return self.snap_height_nm + + def get_metal_track_pitch_nm(self): + """Returns the metal track pitch in nm""" + return self.metal_track_pitch_nm + + def get_metal_track_pitch_um(self): + """Returns the metal track pitch in um""" + return self.metal_track_pitch_um + + def get_manufacturing_grid_nm(self): + """Returns the manufacturing grid in nm""" + return self.manufacturing_grid_nm + + def get_manufacturing_grid_um(self): + """Returns the manufacturing grid in um""" + return self.manufacturing_grid_um + + def get_contacted_poly_pitch(self): + """Returns the poly pitch in nm""" + return self.contacted_poly_pitch_nm + + def get_fin_pitch(self): + """Returns the fin pitch in nm""" + return self.fin_pitch_nm + + def get_x_offset(self): + """Returns the x offset in um""" + return self.x_offset + + def get_y_offset(self): + """Returns the y offset in um""" + return self.y_offset + + def get_y_step(self): + """Returns the y step in um""" + return self.y_step + + def get_column_mux_factor(self): + """Returns the column mux factor""" + return self.column_mux_factor diff --git a/utils/create_lef.py b/utils/create_lef.py deleted file mode 100644 index 0cc7bec..0000000 --- a/utils/create_lef.py +++ /dev/null @@ -1,245 +0,0 @@ -import os -import sys -import math - -################################################################################ -# CREATE LEF view for the given SRAM -################################################################################ - - -def create_header(fid, name, w, h, bits, depth, banks): - """LEF header""" - - fid.write("# Generated by FakeRAM 2.0\n") - fid.write("VERSION 5.7 ;\n") - fid.write('BUSBITCHARS "[]" ;\n') - fid.write("PROPERTYDEFINITIONS\n") - fid.write(" MACRO width INTEGER ;\n") - fid.write(" MACRO depth INTEGER ;\n") - fid.write(" MACRO banks INTEGER ;\n") - fid.write("END PROPERTYDEFINITIONS\n") - fid.write("MACRO %s\n" % (name)) - fid.write(f" PROPERTY width {bits} ;\n") - fid.write(f" PROPERTY depth {depth} ;\n") - fid.write(f" PROPERTY banks {banks} ;\n") - fid.write(" FOREIGN %s 0 0 ;\n" % (name)) - fid.write(" SYMMETRY X Y R90 ;\n") - fid.write(" SIZE %.3f BY %.3f ;\n" % (w, h)) - fid.write(" CLASS BLOCK ;\n") - - -def create_pg_shapes( - fid, w, h, y_step, x_offset, y_offset, supply_pin_half_width, supply_pin_pitch -): - """Creates power/ground shapes""" - - while y_step <= h - y_offset: - fid.write( - " RECT %.3f %.3f %.3f %.3f ;\n" - % ( - x_offset, - y_step - supply_pin_half_width, - w - x_offset, - y_step + supply_pin_half_width, - ) - ) - y_step += ( - supply_pin_pitch * 2 - ) # this *2 is important because we want alternate VDD and VSS pins - - -def create_pg_pin( - fid, - pin_name, - pin_use, - metal_layer, - w, - h, - y_step, - x_offset, - y_offset, - supply_pin_half_width, - supply_pin_pitch, -): - fid.write(" PIN %s\n" % pin_name) - fid.write(" DIRECTION INOUT ;\n") - fid.write(" USE %s ;\n" % pin_use) - fid.write(" PORT\n") - fid.write(" LAYER %s ;\n" % metal_layer) - create_pg_shapes( - fid, w, h, y_step, x_offset, y_offset, supply_pin_half_width, supply_pin_pitch - ) - fid.write(" END\n") - fid.write(" END %s\n" % pin_name) - - -def create_pg_straps( - fid, min_pin_width, min_pin_pitch, x_offset, y_offset, w, h, metal_layer -): - """Create power/ground straps""" - - supply_pin_width = min_pin_width * 4 - supply_pin_half_width = supply_pin_width / 2 - supply_pin_pitch = min_pin_pitch * 8 - # supply_pin_layer = '%s' % metal_layer - - ## Create supply pins : How are we ensuring that supply pins don't overlap - ## with the signal pins? Is it by giving x_offset as the base x coordinate ? - y_step = y_offset - create_pg_pin( - fid, - "VSS", - "GROUND", - metal_layer, - w, - h, - y_step, - x_offset, - y_offset, - supply_pin_half_width, - supply_pin_pitch, - ) - - y_step = y_offset + supply_pin_pitch - create_pg_pin( - fid, - "VDD", - "POWER", - metal_layer, - w, - h, - y_step, - x_offset, - y_offset, - supply_pin_half_width, - supply_pin_pitch, - ) - - -def create_obs(fid, metal_layer, metal_prefix, w, h): - """Create obstructions""" - - fid.write(" OBS\n") - # full rect - pin_layer_number = metal_layer.replace(metal_prefix, "", 1) - for x in range(int(pin_layer_number)): - dummy = x + 1 - fid.write(" LAYER %s%d ;\n" % (metal_prefix, dummy)) - fid.write(" RECT 0 0 %.3f %.3f ;\n" % (w, h)) - fid.write(" END\n") - - -def create_signal_pins(fid, mem, bits, addr_width, y_offset, pin_pitch, group_pitch): - """LEF SIGNAL PINS""" - - manufacturing_grid_um = mem.process.manufacturing_grid_um - - y_step = ( - y_offset - (y_offset % manufacturing_grid_um) + (mem.process.pin_width_um / 2.0) - ) - for i in range(int(bits)): - y_step = lef_add_pin(fid, mem, "rd_out[%d]" % i, False, y_step, pin_pitch) - - y_step += group_pitch - for i in range(int(bits)): - y_step = lef_add_pin(fid, mem, "wd_in[%d]" % i, True, y_step, pin_pitch) - - y_step += group_pitch - for i in range(int(addr_width)): - y_step = lef_add_pin(fid, mem, "addr_in[%d]" % i, True, y_step, pin_pitch) - - y_step += group_pitch - y_step = lef_add_pin(fid, mem, "we_in", True, y_step, pin_pitch) - y_step = lef_add_pin(fid, mem, "ce_in", True, y_step, pin_pitch) - y_step = lef_add_pin(fid, mem, "clk", True, y_step, pin_pitch) - - -def create_lef(mem, results_dir): - - # File pointer - fid = open(os.sep.join([results_dir, mem.name + ".lef"]), "w") - - # Memory parameters - name = mem.name - depth = mem.depth - bits = mem.width_in_bits - banks = mem.num_banks - w = mem.width_um - h = mem.height_um - num_rwport = mem.rw_ports - addr_width = math.ceil(math.log2(mem.depth)) - - # Process parameters - min_pin_width = mem.process.pin_width_um - min_pin_pitch = mem.process.pin_pitch_um - metal_prefix = mem.process.metal_prefix - metal_layer = mem.process.metal_layer - column_mux_factor = mem.process.column_mux_factor - - # Offset from bottom edge to first pin - x_offset = 1 * min_pin_pitch - # as told by MSK - y_offset = 1 * min_pin_pitch - # as told by MSK - ######################################### - # Calculate the pin spacing (pitch) - ######################################### - # rd_out (#bits) + wd_in (#bits) + addr_in (#addr_width) + we_in/ce_in/clk - number_of_pins = 2 * bits + addr_width + 3 - number_of_tracks_available = math.floor((h - 2 * y_offset) / min_pin_pitch) - number_of_spare_tracks = number_of_tracks_available - number_of_pins - - if number_of_spare_tracks < 0: - raise Exception( - "Error: not enough tracks for %s (num pins: %d, available tracks: %d)." - % (name, number_of_pins, number_of_tracks_available) - ) - - ## The next few lines of code till "pin_pitch = min.." spreads the pins in higher multiples of pin pitch if there are available tracks - track_count = 1 - while number_of_spare_tracks > 0: - track_count += 1 - number_of_spare_tracks = ( - number_of_tracks_available - number_of_pins * track_count - ) - track_count -= 1 - - pin_pitch = min_pin_pitch * track_count - # Divide by the remaining 'spare' tracks into the inter-group spaces - # [4 groups -> 3 spaces] - extra = math.floor((number_of_tracks_available - number_of_pins * track_count) / 3) - group_pitch = extra * mem.process.pin_pitch_um - - create_header(fid, name, w, h, bits, depth, banks) - create_signal_pins(fid, mem, bits, addr_width, y_offset, pin_pitch, group_pitch) - create_pg_straps( - fid, min_pin_width, min_pin_pitch, x_offset, y_offset, w, h, metal_layer - ) - create_obs(fid, metal_layer, metal_prefix, w, h) - fid.write("END %s\n" % name) - fid.write("\n") - fid.write("END LIBRARY\n") - fid.close() - - -# -# Helper function that adds a signal pin -# y_step = lef_add_pin( fid, mem, 'w_mask_in[%d]'%i, True, y_step, pin_pitch ) -def lef_add_pin(fid, mem, pin_name, is_input, y, pitch): - - layer = mem.process.metal_layer - pw = mem.process.pin_width_um - hpw = mem.process.pin_width_um / 2.0 - # half pin width - - fid.write(" PIN %s\n" % pin_name) - fid.write(" DIRECTION %s ;\n" % ("INPUT" if is_input else "OUTPUT")) - fid.write(" USE SIGNAL ;\n") - fid.write(" SHAPE ABUTMENT ;\n") - fid.write(" PORT\n") - fid.write(" LAYER %s ;\n" % layer) - fid.write(" RECT %.3f %.3f %.3f %.3f ;\n" % (0, y - hpw, pw, y + hpw)) - fid.write(" END\n") - fid.write(" END %s\n" % pin_name) - - return y + pitch diff --git a/utils/create_lib.py b/utils/create_lib.py deleted file mode 100644 index 0759c09..0000000 --- a/utils/create_lib.py +++ /dev/null @@ -1,505 +0,0 @@ -import os -import math -import time -import datetime - -################################################################################ -# GENERATE LIBERTY VIEW -# -# Generate a .lib file based on the given SRAM. -################################################################################ - - -def write_header(LIB_file, voltage): - """Writes the Liberty header""" - - # Get the date - d = datetime.date.today() - date = d.isoformat() - current_time = time.strftime("%H:%M:%SZ", time.gmtime()) - - LIB_file.write(" technology (cmos);\n") - LIB_file.write(" delay_model : table_lookup;\n") - LIB_file.write(" revision : 1.0;\n") - LIB_file.write(' date : "%s %s";\n' % (date, current_time)) - LIB_file.write(' comment : "SRAM";\n') - LIB_file.write(' time_unit : "1ns";\n') - LIB_file.write(' voltage_unit : "1V";\n') - LIB_file.write(' current_unit : "1uA";\n') - LIB_file.write(' leakage_power_unit : "1uW";\n') - LIB_file.write(" nom_process : 1;\n") - LIB_file.write(" nom_temperature : 25.000;\n") - LIB_file.write(" nom_voltage : %s;\n" % voltage) - LIB_file.write(" capacitive_load_unit (1,pf);\n\n") - LIB_file.write(' pulling_resistance_unit : "1kohm";\n\n') - LIB_file.write(" operating_conditions(tt_1.0_25.0) {\n") - LIB_file.write(" process : 1;\n") - LIB_file.write(" temperature : 25.000;\n") - LIB_file.write(" voltage : %s;\n" % voltage) - LIB_file.write(" tree_type : balanced_tree;\n") - LIB_file.write(" }\n") - LIB_file.write("\n") - - -def write_defaults(LIB_file, max_slew): - """Writes the library defaults""" - - LIB_file.write(" /* default attributes */\n") - LIB_file.write(" default_cell_leakage_power : 0;\n") - LIB_file.write(" default_fanout_load : 1;\n") - LIB_file.write(" default_inout_pin_cap : 0.0;\n") - LIB_file.write(" default_input_pin_cap : 0.0;\n") - LIB_file.write(" default_output_pin_cap : 0.0;\n") - LIB_file.write(" default_input_pin_cap : 0.0;\n") - LIB_file.write(" default_max_transition : %.3f;\n\n" % max_slew) - LIB_file.write(" default_operating_conditions : tt_1.0_25.0;\n") - LIB_file.write(" default_leakage_power_density : 0.0;\n") - LIB_file.write("\n") - - LIB_file.write(" /* additional header data */\n") - LIB_file.write(" slew_derate_from_library : 1.000;\n") - LIB_file.write(" slew_lower_threshold_pct_fall : 20.000;\n") - LIB_file.write(" slew_upper_threshold_pct_fall : 80.000;\n") - LIB_file.write(" slew_lower_threshold_pct_rise : 20.000;\n") - LIB_file.write(" slew_upper_threshold_pct_rise : 80.000;\n") - LIB_file.write(" input_threshold_pct_fall : 50.000;\n") - LIB_file.write(" input_threshold_pct_rise : 50.000;\n") - LIB_file.write(" output_threshold_pct_fall : 50.000;\n") - LIB_file.write(" output_threshold_pct_rise : 50.000;\n\n") - LIB_file.write("\n") - - -def write_table_templates(LIB_file, name): - """Writes the default table templates""" - - LIB_file.write(" lu_table_template(%s_mem_out_delay_template) {\n" % name) - LIB_file.write(" variable_1 : input_net_transition;\n") - LIB_file.write(" variable_2 : total_output_net_capacitance;\n") - LIB_file.write(' index_1 ("1000, 1001");\n') - LIB_file.write(' index_2 ("1000, 1001");\n') - LIB_file.write(" }\n") - LIB_file.write(" lu_table_template(%s_mem_out_slew_template) {\n" % name) - LIB_file.write(" variable_1 : total_output_net_capacitance;\n") - LIB_file.write(' index_1 ("1000, 1001");\n') - LIB_file.write(" }\n") - LIB_file.write(" lu_table_template(%s_constraint_template) {\n" % name) - LIB_file.write(" variable_1 : related_pin_transition;\n") - LIB_file.write(" variable_2 : constrained_pin_transition;\n") - LIB_file.write(' index_1 ("1000, 1001");\n') - LIB_file.write(' index_2 ("1000, 1001");\n') - LIB_file.write(" }\n") - LIB_file.write(" power_lut_template(%s_energy_template_clkslew) {\n" % name) - LIB_file.write(" variable_1 : input_transition_time;\n") - LIB_file.write(' index_1 ("1000, 1001");\n') - LIB_file.write(" }\n") - LIB_file.write(" power_lut_template(%s_energy_template_sigslew) {\n" % name) - LIB_file.write(" variable_1 : input_transition_time;\n") - LIB_file.write(' index_1 ("1000, 1001");\n') - LIB_file.write(" }\n") - - -def write_bus_defs(LIB_file, name, bits, addr_width): - """Writes the bus type definitions""" - - addr_width_m1 = addr_width - 1 - LIB_file.write(" type (%s_DATA) {\n" % name) - LIB_file.write(" base_type : array ;\n") - LIB_file.write(" data_type : bit ;\n") - LIB_file.write(" bit_width : %d;\n" % bits) - LIB_file.write(" bit_from : %d;\n" % (int(bits) - 1)) - LIB_file.write(" bit_to : 0 ;\n") - LIB_file.write(" downto : true ;\n") - LIB_file.write(" }\n") - LIB_file.write(" type (%s_ADDRESS) {\n" % name) - LIB_file.write(" base_type : array ;\n") - LIB_file.write(" data_type : bit ;\n") - LIB_file.write(" bit_width : %d;\n" % addr_width) - LIB_file.write(" bit_from : %d;\n" % addr_width_m1) - LIB_file.write(" bit_to : 0 ;\n") - LIB_file.write(" downto : true ;\n") - LIB_file.write(" }\n") - - -def write_int_power_table(LIB_file, rise_fall, template_name, slew_indices, dynamic): - """Writes the internal power table""" - - LIB_file.write(" %s_power(%s) {\n" % (rise_fall, template_name)) - LIB_file.write(' index_1 ("%s");\n' % slew_indices) - LIB_file.write(' values ("%.3f, %.3f")\n' % (dynamic, dynamic)) - LIB_file.write(" }\n") - - -def write_internal_power(LIB_file, template_name, slew_indices, dynamic, when=None): - """Writes the internal power section""" - - LIB_file.write(" internal_power(){\n") - if when: - LIB_file.write(' when : "%s";\n' % when) - write_int_power_table(LIB_file, "rise", template_name, slew_indices, dynamic) - write_int_power_table(LIB_file, "fall", template_name, slew_indices, dynamic) - LIB_file.write(" }\n") - - -def write_clk_pin( - LIB_file, name, min_driver_in_cap, min_period, slew_indices, clkpindynamic -): - """Writes the clock pin section""" - - int_power_template = name + "_energy_template_clkslew" - LIB_file.write(" pin(clk) {\n") - LIB_file.write(" direction : input;\n") - LIB_file.write(" capacitance : %.3f;\n" % (min_driver_in_cap * 5)) - # Clk pin is usually higher cap for fanout control, assuming an x5 driver. - LIB_file.write(" clock : true;\n") - LIB_file.write(" min_period : %.3f ;\n" % (min_period)) - write_internal_power(LIB_file, int_power_template, slew_indices, clkpindynamic) - LIB_file.write(" }\n") - LIB_file.write("\n") - - -def write_cell_delay( - LIB_file, rise_fall, template_name, slew_indices, load_indices, delay -): - """Writes the cell delay section""" - - LIB_file.write(" cell_%s(%s) {\n" % (rise_fall, template_name)) - LIB_file.write(' index_1 ("%s");\n' % slew_indices) - LIB_file.write(' index_2 ("%s");\n' % load_indices) - LIB_file.write(" values ( \\\n") - LIB_file.write(' "%.3f, %.3f", \\\n' % (delay, delay)) - LIB_file.write(' "%.3f, %.3f" \\\n' % (delay, delay)) - LIB_file.write(" )\n") - LIB_file.write(" }\n") - - -def write_cell_transition( - LIB_file, rise_fall, template_name, load_indices, min_slew, max_slew -): - """Writes the cell transition section""" - - LIB_file.write(" %s_transition(%s) {\n" % (rise_fall, template_name)) - LIB_file.write(' index_1 ("%s");\n' % load_indices) - LIB_file.write(' values ("%.3f, %.3f")\n' % (min_slew, max_slew)) - LIB_file.write(" }\n") - - -def write_cell_constraint(LIB_file, rise_fall, template_name, slew_indices, val): - """Writes the cell constraint section""" - - LIB_file.write(" %s_constraint(%s) {\n" % (rise_fall, template_name)) - LIB_file.write(' index_1 ("%s");\n' % slew_indices) - LIB_file.write(' index_2 ("%s");\n' % slew_indices) - LIB_file.write(" values ( \\\n") - LIB_file.write(' "%.3f, %.3f", \\\n' % (val, val)) - LIB_file.write(' "%.3f, %.3f" \\\n' % (val, val)) - LIB_file.write(" )\n") - LIB_file.write(" }\n") - - -def write_output_bus( - LIB_file, - mem, - name, - pin_name, - max_load, - slew_indices, - load_indices, - min_slew, - max_slew, -): - """Writes the output bus definition""" - - tcq = float(mem.access_time_ns) - delay_template_name = name + "_mem_out_delay_template" - transition_template_name = name + "_mem_out_slew_template" - - LIB_file.write(" bus(%s) {\n" % pin_name) - LIB_file.write(" bus_type : %s_DATA;\n" % name) - LIB_file.write(" direction : output;\n") - LIB_file.write(" max_capacitance : %.3f;\n" % max_load) - # Based on 32x inverter being a common max (or near max) inverter - LIB_file.write(" memory_read() {\n") - LIB_file.write(" address : addr_in;\n") - LIB_file.write(" }\n") - LIB_file.write(" timing() {\n") - LIB_file.write(' related_pin : "clk" ;\n') - LIB_file.write(" timing_type : rising_edge;\n") - LIB_file.write(" timing_sense : non_unate;\n") - write_cell_delay( - LIB_file, "rise", delay_template_name, slew_indices, load_indices, tcq - ) - write_cell_delay( - LIB_file, "fall", delay_template_name, slew_indices, load_indices, tcq - ) - write_cell_transition( - LIB_file, "rise", transition_template_name, load_indices, min_slew, max_slew - ) - write_cell_transition( - LIB_file, "fall", transition_template_name, load_indices, min_slew, max_slew - ) - LIB_file.write(" }\n") - LIB_file.write(" }\n") - - -def write_pin( - LIB_file, - name, - pin_name, - min_driver_in_cap, - slew_indices, - tsetup, - thold, - pindynamic, -): - """Writes the enable pin definition""" - - template_name = name + "_constraint_template" - LIB_file.write(" pin(%s){\n" % pin_name) - LIB_file.write(" direction : input;\n") - LIB_file.write(" capacitance : %.3f;\n" % (min_driver_in_cap)) - write_timing(LIB_file, name, slew_indices, tsetup, thold) - write_internal_power( - LIB_file, name + "_energy_template_sigslew", slew_indices, pindynamic - ) - LIB_file.write(" }\n") - - -def write_timing(LIB_file, name, slew_indices, tsetup, thold): - """Writes the pin/bus timing section""" - - template_name = name + "_constraint_template" - LIB_file.write(" timing() {\n") - LIB_file.write(" related_pin : clk;\n") - LIB_file.write(" timing_type : setup_rising ;\n") - write_cell_constraint(LIB_file, "rise", template_name, slew_indices, tsetup) - write_cell_constraint(LIB_file, "fall", template_name, slew_indices, tsetup) - LIB_file.write(" } \n") - LIB_file.write(" timing() {\n") - LIB_file.write(" related_pin : clk;\n") - LIB_file.write(" timing_type : hold_rising ;\n") - write_cell_constraint(LIB_file, "rise", template_name, slew_indices, thold) - write_cell_constraint(LIB_file, "fall", template_name, slew_indices, thold) - LIB_file.write(" }\n") - - -def write_address_bus( - LIB_file, - name, - bus_name, - min_driver_in_cap, - slew_indices, - tsetup, - thold, - pindynamic, -): - """Writes the address bus""" - - LIB_file.write(" bus(%s) {\n" % bus_name) - LIB_file.write(" bus_type : %s_ADDRESS;\n" % name) - LIB_file.write(" direction : input;\n") - LIB_file.write(" capacitance : %.3f;\n" % (min_driver_in_cap)) - write_timing(LIB_file, name, slew_indices, tsetup, thold) - write_internal_power( - LIB_file, name + "_energy_template_sigslew", slew_indices, pindynamic - ) - LIB_file.write(" }\n") - - -def write_data_bus( - LIB_file, - name, - bus_name, - min_driver_in_cap, - slew_indices, - tsetup, - thold, - pindynamic, -): - """Writes the data bus""" - - LIB_file.write(" bus(%s) {\n" % bus_name) - LIB_file.write(" bus_type : %s_DATA;\n" % name) - LIB_file.write(" memory_write() {\n") - LIB_file.write(" address : addr_in;\n") - LIB_file.write(' clocked_on : "clk";\n') - LIB_file.write(" }\n") - LIB_file.write(" direction : input;\n") - LIB_file.write(" capacitance : %.3f;\n" % (min_driver_in_cap)) - write_timing(LIB_file, name, slew_indices, tsetup, thold) - write_internal_power( - LIB_file, - name + "_energy_template_sigslew", - slew_indices, - pindynamic, - "(! (we_in) )", - ) - write_internal_power( - LIB_file, - name + "_energy_template_sigslew", - slew_indices, - pindynamic, - "(we_in)", - ) - LIB_file.write(" }\n") - - -def write_cell( - LIB_file, - mem, - name, - bits, - addr_width, - min_driver_in_cap, - min_load, - max_load, - num_rwport, - min_slew, - max_slew, -): - """Writes the Liberty cell""" - - area = float(mem.area_um2) - tsetup = float(mem.t_setup_ns) - thold = float(mem.t_hold_ns) - min_period = float(mem.cycle_time_ns) - clkpindynamic = float(mem.pin_dynamic_power_mW) * 1e3 - pindynamic = float(mem.pin_dynamic_power_mW) * 1e1 - leakage = float(mem.standby_leakage_per_bank_mW) * 1e3 - - slew_indices = "%.3f, %.3f" % (min_slew, max_slew) - # input pin transition with between 1xfo4 and 100xfo4 - load_indices = "%.3f, %.3f" % (min_load, max_load) - # output capacitance table between a 1x and 32x inverter - - LIB_file.write("cell(%s) {\n" % name) - LIB_file.write(" area : %.3f;\n" % area) - LIB_file.write(" interface_timing : true;\n") - LIB_file.write(" memory() {\n") - LIB_file.write(" type : ram;\n") - LIB_file.write(" address_width : %d;\n" % addr_width) - LIB_file.write(" word_width : %d;\n" % bits) - LIB_file.write(" }\n") - write_clk_pin( - LIB_file, name, min_driver_in_cap, min_period, slew_indices, clkpindynamic - ) - if num_rwport == 1: - write_output_bus( - LIB_file, - mem, - name, - "rd_out", - max_load, - slew_indices, - load_indices, - min_slew, - max_slew, - ) - write_pin( - LIB_file, - name, - "we_in", - min_driver_in_cap, - slew_indices, - tsetup, - thold, - pindynamic, - ) - write_pin( - LIB_file, - name, - "ce_in", - min_driver_in_cap, - slew_indices, - tsetup, - thold, - pindynamic, - ) - if num_rwport == 1: - write_address_bus( - LIB_file, - name, - "addr_in", - min_driver_in_cap, - slew_indices, - tsetup, - thold, - pindynamic, - ) - write_data_bus( - LIB_file, - name, - "wd_in", - min_driver_in_cap, - slew_indices, - tsetup, - thold, - pindynamic, - ) - LIB_file.write(" cell_leakage_power : %.3f;\n" % (leakage)) - LIB_file.write("}\n") - - -def create_lib(mem, results_dir): - """Writes the Liberty lib""" - - # Make sure the data types are correct - name = str(mem.name) - bits = int(mem.width_in_bits) - min_driver_in_cap = float(mem.cap_input_pf) - fo4 = float(mem.fo4_ps) / 1e3 - - # Only support 1RW srams. At some point, expose these as well! - num_rwport = mem.rw_ports - - # Number of bits for address - addr_width = math.ceil(math.log2(mem.depth)) - - # TODO: Arbitrary indices for the NLDM table. This is used for Clk->Q arcs - # as well as setup/hold times. We only have a single value for these, there - # are two options. 1. adding some sort of static variation of the single - # value for each table entry, 2. use the same value so all interpolated - # values are the same. The 1st is more realistic but depend on good variation - # values which is process sepcific and I don't have a strategy for - # determining decent variation values without breaking NDA so right now we - # have no variations. - # - # The table indices are main min/max values for interpolation. The tools - # typically don't like extrapolation so a large range is nice, but makes the - # single value strategy described above even more unrealistic. - # - min_slew = 1 * fo4 - # arbitrary (1x fo4, fear that 0 would cause issues) - max_slew = 25 * fo4 - # arbitrary (25x fo4 as ~100x fanout ... i know that is not really how it works) - min_load = 1 * min_driver_in_cap - # arbitrary (1x driver, fear that 0 would cause issues) - max_load = 100 * min_driver_in_cap - # arbitrary (100x driver) - - # Start generating the LIB file - - LIB_file = open(os.sep.join([results_dir, name + ".lib"]), "w") - - LIB_file.write("library(%s) {\n" % name) - write_header(LIB_file, float(mem.process.voltage)) - write_defaults(LIB_file, max_slew) - write_table_templates(LIB_file, name) - LIB_file.write(" library_features(report_delay_calculation);\n") - write_bus_defs(LIB_file, name, bits, addr_width) - write_cell( - LIB_file, - mem, - name, - bits, - addr_width, - min_driver_in_cap, - min_load, - max_load, - num_rwport, - min_slew, - max_slew, - ) - LIB_file.write("\n") - LIB_file.write("}\n") - - LIB_file.close() diff --git a/utils/create_verilog.py b/utils/create_verilog.py deleted file mode 100644 index 931955b..0000000 --- a/utils/create_verilog.py +++ /dev/null @@ -1,119 +0,0 @@ -import os -import math - -################################################################################ -# GENERATE VERILOG VIEW -# -# Generate a .v file based on the given SRAM. -################################################################################ - - -def write_module_ports(V_file, bits, depth, addr_width, num_rwport): - V_file.write("(\n") - if num_rwport == 1: - V_file.write(" rd_out,\n") - V_file.write(" addr_in,\n") - V_file.write(" we_in,\n") - V_file.write(" wd_in,\n") - V_file.write(" clk,\n") - V_file.write(" ce_in\n") - V_file.write(");\n") - V_file.write(" parameter BITS = %s;\n" % str(bits)) - V_file.write(" parameter WORD_DEPTH = %s;\n" % str(depth)) - V_file.write(" parameter ADDR_WIDTH = %s;\n" % str(addr_width)) - V_file.write(" parameter corrupt_mem_on_X_p = 1;\n") - V_file.write("\n") - if num_rwport == 1: - V_file.write(" output reg [BITS-1:0] rd_out;\n") - V_file.write(" input [ADDR_WIDTH-1:0] addr_in;\n") - V_file.write(" input we_in;\n") - V_file.write(" input [BITS-1:0] wd_in;\n") - V_file.write(" input clk;\n") - V_file.write(" input ce_in;\n") - V_file.write("\n") - - -def write_timing_check(V_file): - """Writes timing check placeholder data""" - - V_file.write( - " // Timing check placeholders (will be replaced during SDF back-annotation)\n" - ) - V_file.write(" reg notifier;\n") - V_file.write(" specify\n") - V_file.write(" // Delay from clk to rd_out\n") - V_file.write(" (posedge clk *> rd_out) = (0, 0);\n") - V_file.write("\n") - V_file.write(" // Timing checks\n") - V_file.write(" $width (posedge clk, 0, 0, notifier);\n") - V_file.write(" $width (negedge clk, 0, 0, notifier);\n") - V_file.write(" $period (posedge clk, 0, notifier);\n") - V_file.write(" $setuphold (posedge clk, we_in, 0, 0, notifier);\n") - V_file.write(" $setuphold (posedge clk, ce_in, 0, 0, notifier);\n") - V_file.write(" $setuphold (posedge clk, addr_in, 0, 0, notifier);\n") - V_file.write(" $setuphold (posedge clk, wd_in, 0, 0, notifier);\n") - V_file.write(" endspecify\n") - V_file.write("\n") - - -def create_verilog(mem, results_dir): - - name = str(mem.name) - depth = int(mem.depth) - num_rwport = int(mem.rw_ports) - addr_width = math.ceil(math.log2(depth)) - - V_file = open(os.sep.join([results_dir, name + ".v"]), "w") - - V_file.write("module %s\n" % name) - write_module_ports( - V_file, int(mem.width_in_bits), mem.depth, addr_width, num_rwport - ) - V_file.write(" reg [BITS-1:0] mem [0:WORD_DEPTH-1];\n") - V_file.write("\n") - V_file.write(" integer j;\n") - V_file.write("\n") - V_file.write(" always @(posedge clk)\n") - V_file.write(" begin\n") - V_file.write(" if (ce_in)\n") - V_file.write(" begin\n") - for i in range(int(num_rwport)): - V_file.write( - " //if ((we_in !== 1'b1 && we_in !== 1'b0) && corrupt_mem_on_X_p)\n" - ) - V_file.write(" if (corrupt_mem_on_X_p &&\n") - V_file.write(" ((^we_in === 1'bx) || (^addr_in === 1'bx))\n") - V_file.write(" )\n") - V_file.write(" begin\n") - V_file.write( - " // WEN or ADDR is unknown, so corrupt entire array (using unsynthesizeable for loop)\n" - ) - V_file.write(" for (j = 0; j < WORD_DEPTH; j = j + 1)\n") - V_file.write(" mem[j] <= 'x;\n") - V_file.write( - ' $display("warning: ce_in=1, we_in is %b, addr_in = %x in ' - + name - + '", we_in, addr_in);\n' - ) - V_file.write(" end\n") - V_file.write(" else if (we_in)\n") - V_file.write(" begin\n") - V_file.write(" mem[addr_in] <= (wd_in) | (mem[addr_in]);\n") - # V_file.write(' mem[addr_in] <= (wd_in & w_mask_in) | (mem[addr_in] & ~w_mask_in);\n') - V_file.write(" end\n") - V_file.write(" // read\n") - for i in range(int(num_rwport)): - V_file.write(" rd_out <= mem[addr_in];\n") - V_file.write(" end\n") - V_file.write(" else\n") - V_file.write(" begin\n") - V_file.write(" // Make sure read fails if ce_in is low\n") - V_file.write(" rd_out <= 'x;\n") - V_file.write(" end\n") - V_file.write(" end\n") - V_file.write("\n") - write_timing_check(V_file) - - V_file.write("endmodule\n") - - V_file.close() diff --git a/utils/dual_port_ram.py b/utils/dual_port_ram.py new file mode 100755 index 0000000..ac2a20a --- /dev/null +++ b/utils/dual_port_ram.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 + +from class_memory import Memory +from ram import RAM + + +class DualPortRAM(RAM): + """ + Class for dual port RAM + + RAM has the following pins/busses + + input we_a, + input [ADDR_WIDTH-1:0] addr_a, + input [DATA_WIDTH-1:0] din_a, + output [DATA_WIDTH-1:0] dout_a, + input we_b, + input [ADDR_WIDTH-1:0] addr_b, + input [DATA_WIDTH-1:0] din_b, + output [DATA_WIDTH-1:0] dout_b, + input clk, + """ + + def __init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ): + """Initializer""" + RAM.__init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ) + self.num_rw_ports = 2 + + def get_num_pins(self): + """Returns the total number of logical pins""" + + # din (#bits) + dout (#bits) + addr (#addr_width) + we + rw_port_group_size = (2 * self.get_width()) + self.get_addr_width() + 1 + # 2 rw groups + clk + return (2 * rw_port_group_size) + 1 + + +if __name__ == "__main__": # pragma: nocover + Memory.main("RAM", "DP") diff --git a/utils/dual_port_regfile.py b/utils/dual_port_regfile.py new file mode 100755 index 0000000..1f27401 --- /dev/null +++ b/utils/dual_port_regfile.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 + +from class_memory import Memory +from reg_file import RegFile + + +class DualPortRegFile(RegFile): + """ + Class for dual port register file + + Reg file has the following pins/busses + + input we_a, + input [ADDR_WIDTH-1:0] addr_a, + input [DATA_WIDTH-1:0] din_a, + output [DATA_WIDTH-1:0] dout_a, + input we_b, + input [ADDR_WIDTH-1:0] addr_b, + input [DATA_WIDTH-1:0] din_b, + output [DATA_WIDTH-1:0] dout_b, + input clk, + """ + + def __init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ): + """Initializer""" + RegFile.__init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ) + self.num_rw_ports = 2 + + def get_num_pins(self): + """Returns the total number of logical pins""" + + # din (#bits) + dout (#bits) + addr (#addr_width) + we + rw_port_group_size = (2 * self.get_width()) + self.get_addr_width() + 1 + # 2 rw groups + clk + return (2 * rw_port_group_size) + 1 + + +if __name__ == "__main__": # pragma: nocover + Memory.main("RF", "DP") diff --git a/utils/exporter.py b/utils/exporter.py new file mode 100644 index 0000000..f9c5b3e --- /dev/null +++ b/utils/exporter.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 + + +class Exporter: + """Base class for all exporters. Contains common code""" + + def __init__(self, memory): + """Initializer""" + self._memory = memory + + def get_memory(self): + """Returns the memory for this exporter""" + return self._memory + + def export_file(self, file_name): + """Exports the contents to the specified file""" + with open(file_name, "w") as out_fh: + self.export(out_fh) diff --git a/utils/factory_base.py b/utils/factory_base.py new file mode 100644 index 0000000..69b6500 --- /dev/null +++ b/utils/factory_base.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 + + +class FactoryBase: + """Base class for factory registration and creation""" + + _registry = {} + + @classmethod + def get_key(self, memory_type, port_config): + """Returns the key from the memory_type and port_config""" + return f"{port_config}_{memory_type}" + + @classmethod + def register(self, memory_type, port_config, klass): + """Registers a class for the given memory_type and port_config""" + self._registry[self.get_key(memory_type, port_config)] = klass + + @classmethod + def create( + self, + name, + width_in_bits, + depth, + num_banks, + memory_type, + port_config, + process, + timing_data, + ): + """ + Creates and returns the requested object based on the factory registry + """ + key = self.get_key(memory_type, port_config) + klass = self._registry.get(key) + if klass is None: + raise ValueError( + f"No class registered under key: {memory_type} {port_config}" + ) + return klass(name, width_in_bits, depth, num_banks, process, timing_data) diff --git a/utils/lef_exporter.py b/utils/lef_exporter.py new file mode 100644 index 0000000..15f06b3 --- /dev/null +++ b/utils/lef_exporter.py @@ -0,0 +1,263 @@ +#!/usr/bin/env python3 + +import math +from exporter import Exporter + + +class LefExporter(Exporter): + """ + Base class for LEF exporter + + Note that memory-type-specific methods are defined in their respective + classes (e.g. look at single_port_sram_lef_exporter) + """ + + def __init__(self, memory): + """Initializer""" + Exporter.__init__(self, memory) + + def export(self, out_fh): + """Exports LEF file to output stream""" + + # Memory parameters + mem = self.get_memory() + name = mem.get_name() + physical = mem.get_physical_data() + w = physical.get_width() + h = physical.get_height() + pin_pitch = physical.get_pin_pitch() + group_pitch = physical.get_group_pitch() + + # Process parameters + process = mem.get_process_data() + min_pin_width = process.get_pin_width_um() + min_pin_pitch = process.get_pin_pitch_um() + metal_prefix = process.get_metal_prefix() + metal_layer = process.get_metal_layer() + x_offset = process.get_x_offset() + y_offset = process.get_y_offset() + + self.create_header( + out_fh, + name, + w, + h, + self._memory.get_width(), + self._memory.get_depth(), + mem.num_banks, + ) + self.create_signal_pins(out_fh, pin_pitch, group_pitch) + self.create_pg_straps( + out_fh, min_pin_width, min_pin_pitch, x_offset, y_offset, w, h, metal_layer + ) + self.create_obs(out_fh, metal_layer, metal_prefix, w, h) + self.write_footer(out_fh, name) + + def create_header(self, fid, name, w, h, bits, depth, banks): + """LEF header""" + + fid.write("# Generated by FakeRAM 2.0\n") + fid.write("VERSION 5.7 ;\n") + fid.write('BUSBITCHARS "[]" ;\n') + fid.write("PROPERTYDEFINITIONS\n") + fid.write(" MACRO width INTEGER ;\n") + fid.write(" MACRO depth INTEGER ;\n") + fid.write(" MACRO banks INTEGER ;\n") + fid.write("END PROPERTYDEFINITIONS\n") + fid.write("MACRO %s\n" % (name)) + fid.write(f" PROPERTY width {bits} ;\n") + fid.write(f" PROPERTY depth {depth} ;\n") + fid.write(f" PROPERTY banks {banks} ;\n") + fid.write(" FOREIGN %s 0 0 ;\n" % (name)) + fid.write(" SYMMETRY X Y R90 ;\n") + fid.write(" SIZE %.3f BY %.3f ;\n" % (w, h)) + fid.write(" CLASS BLOCK ;\n") + + def add_pin(self, fid, pin_name, is_input, y, pitch): + """ + Helper function that adds a signal pin + y_step = add_pin( fid, mem, 'w_mask_in[%d]'%i, True, y_step, pin_pitch ) + """ + mem = self.get_memory() + process = mem.get_process_data() + layer = process.get_metal_layer() + pw = process.get_pin_width_um() + hpw = process.get_pin_width_um() / 2.0 + # half pin width + + fid.write(" PIN %s\n" % pin_name) + fid.write(" DIRECTION %s ;\n" % ("INPUT" if is_input else "OUTPUT")) + fid.write(" USE SIGNAL ;\n") + fid.write(" SHAPE ABUTMENT ;\n") + fid.write(" PORT\n") + fid.write(" LAYER %s ;\n" % layer) + fid.write(" RECT %.3f %.3f %.3f %.3f ;\n" % (0, y - hpw, pw, y + hpw)) + fid.write(" END\n") + fid.write(" END %s\n" % pin_name) + + return y + pitch + + def create_obs(self, fid, metal_layer, metal_prefix, w, h): + """Create obstructions""" + + fid.write(" OBS\n") + # full rect + pin_layer_number = metal_layer.replace(metal_prefix, "", 1) + for x in range(int(pin_layer_number)): + dummy = x + 1 + fid.write(" LAYER %s%d ;\n" % (metal_prefix, dummy)) + fid.write(" RECT 0 0 %.3f %.3f ;\n" % (w, h)) + fid.write(" END\n") + + def create_pg_pin( + self, + fid, + pin_name, + pin_use, + metal_layer, + w, + h, + y_step, + x_offset, + y_offset, + supply_pin_half_width, + supply_pin_pitch, + ): + """Writes a power/ground pin""" + + fid.write(" PIN %s\n" % pin_name) + fid.write(" DIRECTION INOUT ;\n") + fid.write(" USE %s ;\n" % pin_use) + fid.write(" PORT\n") + fid.write(" LAYER %s ;\n" % metal_layer) + self.create_pg_shapes( + fid, + w, + h, + y_step, + x_offset, + y_offset, + supply_pin_half_width, + supply_pin_pitch, + ) + fid.write(" END\n") + fid.write(" END %s\n" % pin_name) + + def create_pg_shapes( + self, + fid, + w, + h, + y_step, + x_offset, + y_offset, + supply_pin_half_width, + supply_pin_pitch, + ): + """Creates power/ground shapes""" + + while y_step <= h - y_offset: + fid.write( + " RECT %.3f %.3f %.3f %.3f ;\n" + % ( + x_offset, + y_step - supply_pin_half_width, + w - x_offset, + y_step + supply_pin_half_width, + ) + ) + y_step += ( + supply_pin_pitch * 2 + ) # this *2 is important because we want alternate VDD and VSS pins + + def create_pg_straps( + self, fid, min_pin_width, min_pin_pitch, x_offset, y_offset, w, h, metal_layer + ): + """Create power/ground straps""" + + supply_pin_width = min_pin_width * 4 + supply_pin_half_width = supply_pin_width / 2 + supply_pin_pitch = min_pin_pitch * 8 + # supply_pin_layer = '%s' % metal_layer + + ## Create supply pins : How are we ensuring that supply pins don't overlap + ## with the signal pins? Is it by giving x_offset as the base x coordinate ? + y_step = y_offset + self.create_pg_pin( + fid, + "VSS", + "GROUND", + metal_layer, + w, + h, + y_step, + x_offset, + y_offset, + supply_pin_half_width, + supply_pin_pitch, + ) + + y_step = y_offset + supply_pin_pitch + self.create_pg_pin( + fid, + "VDD", + "POWER", + metal_layer, + w, + h, + y_step, + x_offset, + y_offset, + supply_pin_half_width, + supply_pin_pitch, + ) + + def write_signal_bus(self, fid, name, num_pins, is_input, y_step, pin_pitch): + """Writes the individual pins for a signal bus""" + + name_format = f"{name}[%d]" + for i in range(int(num_pins)): + y_step = self.add_pin(fid, name_format % i, is_input, y_step, pin_pitch) + return y_step + + def write_footer(self, fid, name): + """LEF footer""" + fid.write("END %s\n" % name) + fid.write("\n") + fid.write("END LIBRARY\n") + + def create_signals(self, fid, suffix, y_step, pin_pitch, group_pitch): + """Writes rw signal bundle, comprised of dout, din, addr busses""" + + bits = self.get_memory().get_width() + y_step = self.write_signal_bus( + fid, f"dout_{suffix}", bits, False, y_step, pin_pitch + ) + y_step += group_pitch + y_step = self.write_signal_bus( + fid, f"din_{suffix}", bits, False, y_step, pin_pitch + ) + y_step += group_pitch + y_step = self.write_signal_bus( + fid, + f"addr_{suffix}", + self._memory.get_addr_width(), + True, + y_step, + pin_pitch, + ) + y_step += group_pitch + return y_step + + def create_signal_pins(self, fid, pin_pitch, group_pitch): + """LEF SIGNAL PINS""" + + mem = self.get_memory() + y_step = mem.get_process_data().y_step + for i in range(0, mem.get_num_rw_ports()): + suffix = chr(ord("a") + i) + y_step = self.create_signals(fid, suffix, y_step, pin_pitch, group_pitch) + for i in range(0, mem.get_num_rw_ports()): + suffix = chr(ord("a") + i) + y_step = self.add_pin(fid, f"we_{suffix}", True, y_step, pin_pitch) + y_step = self.add_pin(fid, "clk", True, y_step, pin_pitch) diff --git a/utils/liberty_exporter.py b/utils/liberty_exporter.py new file mode 100644 index 0000000..2d489b8 --- /dev/null +++ b/utils/liberty_exporter.py @@ -0,0 +1,386 @@ +#!/usr/bin/env python3 + +import time +import datetime +from exporter import Exporter + + +class LibertyExporter(Exporter): + """Liberty exporter base class""" + + def __init__(self, memory): + """Initializer""" + Exporter.__init__(self, memory) + + def export(self, out_fh): + """Exports the Liberty content to the output stream""" + + name = self.get_memory().get_name() + out_fh.write("library(%s) {\n" % name) + self.write_header(out_fh) + self.write_defaults(out_fh) + self.write_table_templates(out_fh) + out_fh.write(" library_features(report_delay_calculation);\n") + self.write_bus_defs(out_fh) + self.write_cell_header(out_fh) + self.write_cell(out_fh) + self.write_cell_footer(out_fh) + out_fh.write("\n") + out_fh.write("}\n") + + def write_cell_header(self, out_fh): + """Writes the cell header to the output stream""" + + name = self.get_memory().get_name() + area = self.get_memory().physical.get_area(False) + out_fh.write("cell(%s) {\n" % name) + out_fh.write(" area : %.3f;\n" % area) + out_fh.write(" interface_timing : true;\n") + + def write_cell_footer(self, out_fh): + """Writes the cell footer to the output stream""" + + out_fh.write( + " cell_leakage_power : %.3f;\n" + % (self.get_memory().get_timing_data().leakage) + ) + out_fh.write("}\n") + + def write_header(self, out_fh): + """Writes the Liberty header""" + + # Get the date + d = datetime.date.today() + date = d.isoformat() + current_time = time.strftime("%H:%M:%SZ", time.gmtime()) + + voltage = self.get_memory().get_process_data().voltage + out_fh.write(" technology (cmos);\n") + out_fh.write(" delay_model : table_lookup;\n") + out_fh.write(" revision : 1.0;\n") + out_fh.write(' date : "%s %s";\n' % (date, current_time)) + out_fh.write(' comment : "SRAM";\n') + out_fh.write(' time_unit : "1ns";\n') + out_fh.write(' voltage_unit : "1V";\n') + out_fh.write(' current_unit : "1uA";\n') + out_fh.write(' leakage_power_unit : "1uW";\n') + out_fh.write(" nom_process : 1;\n") + out_fh.write(" nom_temperature : 25.000;\n") + out_fh.write(" nom_voltage : %.1f;\n" % voltage) + out_fh.write(" capacitive_load_unit (1,pf);\n\n") + out_fh.write(' pulling_resistance_unit : "1kohm";\n\n') + out_fh.write(" operating_conditions(tt_1.0_25.0) {\n") + out_fh.write(" process : 1;\n") + out_fh.write(" temperature : 25.000;\n") + out_fh.write(" voltage : %.1f;\n" % voltage) + out_fh.write(" tree_type : balanced_tree;\n") + out_fh.write(" }\n") + out_fh.write("\n") + + def write_defaults(self, out_fh): + """Writes the library defaults""" + + out_fh.write(" /* default attributes */\n") + out_fh.write(" default_cell_leakage_power : 0;\n") + out_fh.write(" default_fanout_load : 1;\n") + out_fh.write(" default_inout_pin_cap : 0.0;\n") + out_fh.write(" default_input_pin_cap : 0.0;\n") + out_fh.write(" default_output_pin_cap : 0.0;\n") + out_fh.write(" default_input_pin_cap : 0.0;\n") + out_fh.write( + " default_max_transition : %.3f;\n\n" + % self.get_memory().get_timing_data().max_slew + ) + out_fh.write(" default_operating_conditions : tt_1.0_25.0;\n") + out_fh.write(" default_leakage_power_density : 0.0;\n") + out_fh.write("\n") + + out_fh.write(" /* additional header data */\n") + out_fh.write(" slew_derate_from_library : 1.000;\n") + out_fh.write(" slew_lower_threshold_pct_fall : 20.000;\n") + out_fh.write(" slew_upper_threshold_pct_fall : 80.000;\n") + out_fh.write(" slew_lower_threshold_pct_rise : 20.000;\n") + out_fh.write(" slew_upper_threshold_pct_rise : 80.000;\n") + out_fh.write(" input_threshold_pct_fall : 50.000;\n") + out_fh.write(" input_threshold_pct_rise : 50.000;\n") + out_fh.write(" output_threshold_pct_fall : 50.000;\n") + out_fh.write(" output_threshold_pct_rise : 50.000;\n\n") + out_fh.write("\n") + + def write_table_templates(self, out_fh): + """Writes the default table templates""" + + name = self.get_memory().get_name() + out_fh.write(" lu_table_template(%s_mem_out_delay_template) {\n" % name) + out_fh.write(" variable_1 : input_net_transition;\n") + out_fh.write(" variable_2 : total_output_net_capacitance;\n") + out_fh.write(' index_1 ("1000, 1001");\n') + out_fh.write(' index_2 ("1000, 1001");\n') + out_fh.write(" }\n") + out_fh.write(" lu_table_template(%s_mem_out_slew_template) {\n" % name) + out_fh.write(" variable_1 : total_output_net_capacitance;\n") + out_fh.write(' index_1 ("1000, 1001");\n') + out_fh.write(" }\n") + out_fh.write(" lu_table_template(%s_constraint_template) {\n" % name) + out_fh.write(" variable_1 : related_pin_transition;\n") + out_fh.write(" variable_2 : constrained_pin_transition;\n") + out_fh.write(' index_1 ("1000, 1001");\n') + out_fh.write(' index_2 ("1000, 1001");\n') + out_fh.write(" }\n") + out_fh.write(" power_lut_template(%s_energy_template_clkslew) {\n" % name) + out_fh.write(" variable_1 : input_transition_time;\n") + out_fh.write(' index_1 ("1000, 1001");\n') + out_fh.write(" }\n") + out_fh.write(" power_lut_template(%s_energy_template_sigslew) {\n" % name) + out_fh.write(" variable_1 : input_transition_time;\n") + out_fh.write(' index_1 ("1000, 1001");\n') + out_fh.write(" }\n") + + def write_bus_defs(self, out_fh): + """Writes the bus type definitions""" + + mem = self.get_memory() + name = mem.get_name() + bits = mem.get_width() + data_bus_msb = mem.get_data_bus_msb() + addr_width = mem.get_addr_width() + addr_bus_msb = mem.get_addr_bus_msb() + out_fh.write(" type (%s_DATA) {\n" % name) + out_fh.write(" base_type : array ;\n") + out_fh.write(" data_type : bit ;\n") + out_fh.write(" bit_width : %d;\n" % bits) + out_fh.write(" bit_from : %d;\n" % data_bus_msb) + out_fh.write(" bit_to : 0 ;\n") + out_fh.write(" downto : true ;\n") + out_fh.write(" }\n") + out_fh.write(" type (%s_ADDRESS) {\n" % name) + out_fh.write(" base_type : array ;\n") + out_fh.write(" data_type : bit ;\n") + out_fh.write(" bit_width : %d;\n" % addr_width) + out_fh.write(" bit_from : %d;\n" % addr_bus_msb) + out_fh.write(" bit_to : 0 ;\n") + out_fh.write(" downto : true ;\n") + out_fh.write(" }\n") + + def write_int_power_table( + self, out_fh, rise_fall, template_name, slew_indices, dynamic + ): + """Writes the internal power table""" + + out_fh.write(" %s_power(%s) {\n" % (rise_fall, template_name)) + out_fh.write(' index_1 ("%s");\n' % slew_indices) + out_fh.write(' values ("%.3f, %.3f")\n' % (dynamic, dynamic)) + out_fh.write(" }\n") + + def write_internal_power( + self, out_fh, template_name, slew_indices, dynamic, when=None + ): + """Writes the internal power section""" + + out_fh.write(" internal_power(){\n") + if when: + out_fh.write(' when : "%s";\n' % when) + self.write_int_power_table(out_fh, "rise", template_name, slew_indices, dynamic) + self.write_int_power_table(out_fh, "fall", template_name, slew_indices, dynamic) + out_fh.write(" }\n") + + def write_clk_pin(self, out_fh): + """Writes the clock pin section""" + + int_power_template = self.get_memory().get_name() + "_energy_template_clkslew" + timing_data = self.get_memory().get_timing_data() + out_fh.write(" pin(clk) {\n") + out_fh.write(" direction : input;\n") + out_fh.write( + " capacitance : %.3f;\n" % (timing_data.min_driver_in_cap * 5) + ) + # Clk pin is usually higher cap for fanout control, assuming an x5 driver. + out_fh.write(" clock : true;\n") + out_fh.write( + " min_period : %.3f ;\n" % (timing_data.cycle_time_ns) + ) + self.write_internal_power( + out_fh, + int_power_template, + timing_data.slew_indices, + timing_data.clkpin_dynamic_power, + ) + out_fh.write(" }\n") + out_fh.write("\n") + + def write_cell_delay( + self, out_fh, rise_fall, template_name, slew_indices, load_indices, delay + ): + """Writes the cell delay section""" + + out_fh.write(" cell_%s(%s) {\n" % (rise_fall, template_name)) + out_fh.write(' index_1 ("%s");\n' % slew_indices) + out_fh.write(' index_2 ("%s");\n' % load_indices) + out_fh.write(" values ( \\\n") + out_fh.write(' "%.3f, %.3f", \\\n' % (delay, delay)) + out_fh.write(' "%.3f, %.3f" \\\n' % (delay, delay)) + out_fh.write(" )\n") + out_fh.write(" }\n") + + def write_cell_transition( + self, out_fh, rise_fall, template_name, load_indices, min_slew, max_slew + ): + """Writes the cell transition section""" + + out_fh.write(" %s_transition(%s) {\n" % (rise_fall, template_name)) + out_fh.write(' index_1 ("%s");\n' % load_indices) + out_fh.write(' values ("%.3f, %.3f")\n' % (min_slew, max_slew)) + out_fh.write(" }\n") + + def write_cell_constraint( + self, out_fh, rise_fall, template_name, slew_indices, val + ): + """Writes the cell constraint section""" + + out_fh.write(" %s_constraint(%s) {\n" % (rise_fall, template_name)) + out_fh.write(' index_1 ("%s");\n' % slew_indices) + out_fh.write(' index_2 ("%s");\n' % slew_indices) + out_fh.write(" values ( \\\n") + out_fh.write(' "%.3f, %.3f", \\\n' % (val, val)) + out_fh.write(' "%.3f, %.3f" \\\n' % (val, val)) + out_fh.write(" )\n") + out_fh.write(" }\n") + + def write_output_bus(self, out_fh, name, pin_name, include_memory_read): + """Writes the output bus definition""" + + delay_template_name = name + "_mem_out_delay_template" + transition_template_name = name + "_mem_out_slew_template" + timing_data = self.get_memory().get_timing_data() + max_load = timing_data.max_load + slew_indices = timing_data.slew_indices + load_indices = timing_data.load_indices + min_slew = timing_data.min_slew + max_slew = timing_data.max_slew + tcq = timing_data.access_time_ns + + out_fh.write(" bus(%s) {\n" % pin_name) + out_fh.write(" bus_type : %s_DATA;\n" % name) + out_fh.write(" direction : output;\n") + out_fh.write(" max_capacitance : %.3f;\n" % max_load) + # Based on 32x inverter being a common max (or near max) inverter + if include_memory_read: + out_fh.write(" memory_read() {\n") + out_fh.write(" address : addr_in;\n") + out_fh.write(" }\n") + out_fh.write(" timing() {\n") + out_fh.write(' related_pin : "clk" ;\n') + out_fh.write(" timing_type : rising_edge;\n") + out_fh.write(" timing_sense : non_unate;\n") + self.write_cell_delay( + out_fh, "rise", delay_template_name, slew_indices, load_indices, tcq + ) + self.write_cell_delay( + out_fh, "fall", delay_template_name, slew_indices, load_indices, tcq + ) + self.write_cell_transition( + out_fh, "rise", transition_template_name, load_indices, min_slew, max_slew + ) + self.write_cell_transition( + out_fh, "fall", transition_template_name, load_indices, min_slew, max_slew + ) + out_fh.write(" }\n") + out_fh.write(" }\n") + + def write_pin(self, out_fh, name, pin_name): + """Writes the enable pin definition""" + + template_name = name + "_constraint_template" + timing_data = self.get_memory().get_timing_data() + min_driver_in_cap = timing_data.min_driver_in_cap + slew_indices = timing_data.slew_indices + tsetup = timing_data.t_setup_ns + thold = timing_data.t_hold_ns + pindynamic = timing_data.pin_dynamic + out_fh.write(" pin(%s){\n" % pin_name) + out_fh.write(" direction : input;\n") + out_fh.write(" capacitance : %.3f;\n" % (min_driver_in_cap)) + self.write_timing(out_fh, name, slew_indices, tsetup, thold) + self.write_internal_power( + out_fh, name + "_energy_template_sigslew", slew_indices, pindynamic + ) + out_fh.write(" }\n") + + def write_timing(self, out_fh, name, slew_indices, tsetup, thold): + """Writes the pin/bus timing section""" + + template_name = name + "_constraint_template" + out_fh.write(" timing() {\n") + out_fh.write(" related_pin : clk;\n") + out_fh.write(" timing_type : setup_rising ;\n") + self.write_cell_constraint(out_fh, "rise", template_name, slew_indices, tsetup) + self.write_cell_constraint(out_fh, "fall", template_name, slew_indices, tsetup) + out_fh.write(" } \n") + out_fh.write(" timing() {\n") + out_fh.write(" related_pin : clk;\n") + out_fh.write(" timing_type : hold_rising ;\n") + self.write_cell_constraint(out_fh, "rise", template_name, slew_indices, thold) + self.write_cell_constraint(out_fh, "fall", template_name, slew_indices, thold) + out_fh.write(" }\n") + + def write_address_bus(self, out_fh, name, bus_name): + """Writes the address bus""" + + timing_data = self.get_memory().get_timing_data() + min_driver_in_cap = timing_data.min_driver_in_cap + slew_indices = timing_data.slew_indices + tsetup = timing_data.t_setup_ns + thold = timing_data.t_hold_ns + pindynamic = timing_data.pin_dynamic + out_fh.write(" bus(%s) {\n" % bus_name) + out_fh.write(" bus_type : %s_ADDRESS;\n" % name) + out_fh.write(" direction : input;\n") + out_fh.write(" capacitance : %.3f;\n" % (min_driver_in_cap)) + self.write_timing(out_fh, name, slew_indices, tsetup, thold) + self.write_internal_power( + out_fh, name + "_energy_template_sigslew", slew_indices, pindynamic + ) + out_fh.write(" }\n") + + def write_data_bus(self, out_fh, name, bus_name, include_memory_write): + """Writes the data bus""" + + timing_data = self.get_memory().get_timing_data() + min_driver_in_cap = timing_data.min_driver_in_cap + slew_indices = timing_data.slew_indices + tsetup = timing_data.t_setup_ns + thold = timing_data.t_hold_ns + pindynamic = timing_data.pin_dynamic + out_fh.write(" bus(%s) {\n" % bus_name) + out_fh.write(" bus_type : %s_DATA;\n" % name) + if include_memory_write: + out_fh.write(" memory_write() {\n") + out_fh.write(" address : addr_in;\n") + out_fh.write(' clocked_on : "clk";\n') + out_fh.write(" }\n") + out_fh.write(" direction : input;\n") + out_fh.write(" capacitance : %.3f;\n" % (min_driver_in_cap)) + self.write_timing(out_fh, name, slew_indices, tsetup, thold) + self.write_internal_power( + out_fh, + name + "_energy_template_sigslew", + slew_indices, + pindynamic, + "(! (we_in) )", + ) + self.write_internal_power( + out_fh, + name + "_energy_template_sigslew", + slew_indices, + pindynamic, + "(we_in)", + ) + out_fh.write(" }\n") + + def write_rw_pin_set(self, out_fh, name, suffix, is_ram): + """Writes the rw pin group to the output stream""" + + self.write_pin(out_fh, name, f"we_{suffix}") + self.write_address_bus(out_fh, name, f"addr_{suffix}") + self.write_data_bus(out_fh, name, f"din_{suffix}", is_ram) + self.write_output_bus(out_fh, name, f"dout_{suffix}", is_ram) diff --git a/utils/memory_factory.py b/utils/memory_factory.py new file mode 100644 index 0000000..69faa38 --- /dev/null +++ b/utils/memory_factory.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 + +from factory_base import FactoryBase +from single_port_ram import SinglePortRAM +from dual_port_ram import DualPortRAM +from single_port_regfile import SinglePortRegFile +from dual_port_regfile import DualPortRegFile + + +class MemoryFactory(FactoryBase): + """MemoryFactory "implementation" - done to avoid circular imports""" + + pass + + +# Register known memory types +MemoryFactory.register("RAM", "SP", SinglePortRAM) +MemoryFactory.register("RAM", "DP", DualPortRAM) +MemoryFactory.register("RF", "SP", SinglePortRegFile) +MemoryFactory.register("RF", "DP", DualPortRegFile) diff --git a/utils/physical_data.py b/utils/physical_data.py new file mode 100644 index 0000000..7ff03d2 --- /dev/null +++ b/utils/physical_data.py @@ -0,0 +1,116 @@ +#!/usr/bin/env python3 + +import math + + +class PhysicalData: + """Physical data container""" + + def __init__(self): + """Initializer""" + + self._width_um = None + self._height_um = None + self._snapped_width_um = None + self._snapped_height_um = None + self._pin_pitch = None + self._group_pitch = None + + def set_extents(self, width, height): + """Sets the extents of the memory (e.g. width and height)""" + + self._width_um = width + self._height_um = height + + def get_width(self, snapped=True): + """ + Returns the width of the memory in um. + + If snapped and the width has been snapped, the snapped width is + returned. Otherwise, the unsnapped width is returned + """ + + if snapped and self._snapped_width_um: + return self._snapped_width_um + return self._width_um + + def get_height(self, snapped=True): + """ + Returns the height of the memory in um. + + If snapped and the height has been snapped, the snapped height is + returned. Otherwise, the unsnapped height is returned + """ + + if snapped and self._snapped_height_um: + return self._snapped_height_um + return self._height_um + + def get_area(self, snapped=True): + """ + Returns the area of the memory in um^2. + + If snapped and the area has been snapped, the snapped area is + returned. Otherwise, the unsnapped area is returned + """ + + if snapped and self._snapped_width_um and self._snapped_height_um: + return self._snapped_width_um * self._snapped_height_um + return self._width_um * self._height_um + + def snap_side_to_grid(self, side_um, snap_nm): + """Snaps the length to the grid""" + + return (math.ceil((side_um * 1000.0) / snap_nm) * snap_nm) / 1000.0 + + def snap_to_grid(self, snap_width_nm, snap_height_nm): + """Snaps the width and height to the grid""" + + if not self._width_um and not self._height_um: + raise Exception("Error: width and height must be defined before snapping") + # Adjust to snap + self._snapped_width_um = self.snap_side_to_grid(self._width_um, snap_width_nm) + self._snapped_height_um = self.snap_side_to_grid( + self._height_um, snap_height_nm + ) + + def get_pin_pitch(self): + """Returns the pin pitch in um""" + + return self._pin_pitch + + def get_group_pitch(self): + """Returns the group pitch (spacing between pin groups) in um""" + + return self._group_pitch + + def set_pin_pitches(self, name, num_pins, min_pin_pitch, y_offset): + """Calculate the pin spacing (pitch)""" + + h = self.get_height() # snapped height + if not h: + raise Exception( + f"Error: attempting to set pin pitches before height ({name})" + ) + number_of_tracks_available = math.floor((h - 2 * y_offset) / min_pin_pitch) + number_of_spare_tracks = number_of_tracks_available - num_pins + + if number_of_spare_tracks < 0: + raise Exception( + "Error: not enough tracks for %s (num pins: %d, available tracks: %d)." + % (name, num_pins, number_of_tracks_available) + ) + + ## The next few lines of code till "pin_pitch = min.." spreads the pins + ## in higher multiples of pin pitch if there are available tracks + track_count = 1 + while number_of_spare_tracks > 0: + track_count += 1 + number_of_spare_tracks = number_of_tracks_available - num_pins * track_count + track_count -= 1 + + self._pin_pitch = min_pin_pitch * track_count + # Divide by the remaining 'spare' tracks into the inter-group spaces + # [4 groups -> 3 spaces] + extra = math.floor((number_of_tracks_available - num_pins * track_count) / 3) + self._group_pitch = extra * min_pin_pitch diff --git a/utils/ram.py b/utils/ram.py new file mode 100644 index 0000000..b6b0782 --- /dev/null +++ b/utils/ram.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 + +import math +from class_memory import Memory +from ram_verilog_exporter import RAMVerilogExporter +from ram_liberty_exporter import RAMLibertyExporter + + +class RAM(Memory): + """Base class for RAMs""" + + def __init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ): + """Initializer""" + Memory.__init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ) + + def write_verilog_file(self, out_file_name, is_blackbox=False): + """ + Writes the verilog content to a file + + If is_blackbox, then write the port declarations only. Otherwise, write + the full RTL + """ + + exporter = RAMVerilogExporter(self) + exporter.export_file(out_file_name, is_blackbox) + + def write_liberty_file(self, out_file_name): + """Writes the Liberty content to a file""" + + exporter = RAMLibertyExporter(self) + exporter.export_file(out_file_name) diff --git a/utils/ram_liberty_exporter.py b/utils/ram_liberty_exporter.py new file mode 100644 index 0000000..098dfa4 --- /dev/null +++ b/utils/ram_liberty_exporter.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 + +from liberty_exporter import LibertyExporter + + +class RAMLibertyExporter(LibertyExporter): + """RAM Liberty Exporter""" + + def __init__(self, memory): + """Initializer""" + LibertyExporter.__init__(self, memory) + + def write_cell(self, out_fh): + """ + Writes the Liberty cell + + Difference is that we pass True to the rw_pin_set writer to indicate + that this is a RAM. + """ + + name = self._memory.get_name() + self.write_memory_section(out_fh) + for i in range(0, self._memory.get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_rw_pin_set(out_fh, name, suffix, True) + self.write_clk_pin(out_fh) + + def write_memory_section(self, out_fh): + """Writes the memory section to the output stream""" + + out_fh.write(" memory() {\n") + out_fh.write(" type : ram;\n") + out_fh.write(" address_width : %d;\n" % self._memory.get_addr_width()) + out_fh.write(" word_width : %d;\n" % self._memory.get_width()) + out_fh.write(" }\n") diff --git a/utils/ram_verilog_exporter.py b/utils/ram_verilog_exporter.py new file mode 100644 index 0000000..6246204 --- /dev/null +++ b/utils/ram_verilog_exporter.py @@ -0,0 +1,74 @@ +#!/usr/bin/env python3 + +from verilog_exporter import VerilogExporter + + +class RAMVerilogExporter(VerilogExporter): + """RAM verilog exporter""" + + def __init__(self, memory): + """Initializer""" + VerilogExporter.__init__(self, memory) + + def export_module(self, out_fh): + """Exports the verilog module to the output stream""" + + mem = self.get_memory() + out_fh.write(f"module {mem.get_name()}\n") + out_fh.write("(\n") + for i in range(0, mem.get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_rw_port_decl_set(suffix, out_fh) + out_fh.write(" clk,\n") + out_fh.write(");\n") + out_fh.write(f" parameter DATA_WIDTH = {mem.get_width()};\n") + out_fh.write(f" parameter ADDR_WIDTH = {mem.get_addr_width()};\n") + out_fh.write("\n") + for i in range(0, mem.get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_rw_port_defn_set(suffix, out_fh) + out_fh.write(" input wire clk,\n") + out_fh.write("\n") + out_fh.write( + f" // Memory array: {mem.get_depth()} words of {mem.get_width()} bits\n" + ) + out_fh.write(" reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1];\n") + out_fh.write("\n") + out_fh.write(" // Registers for synchronous reads\n") + out_fh.write(" reg [ADDR_WIDTH-1:0] addr_a_reg;\n") + out_fh.write(" reg [ADDR_WIDTH-1:0] addr_b_reg;\n") + out_fh.write("\n") + out_fh.write(" integer i;\n") + out_fh.write("\n") + out_fh.write(" always @(posedge clk) begin\n") + for i in range(0, mem.get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_rw_port_always(suffix, out_fh) + out_fh.write(" // Synchronous readback\n") + for i in range(0, mem.get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_readback(suffix, out_fh) + out_fh.write(" end\n") + out_fh.write("endmodule\n") + + def write_rw_port_always(self, suffix, out_fh): + """Writes the always @ section for the port group""" + + out_fh.write(f" // ==== Port {suffix.upper()} write ====\n") + out_fh.write( + f" if (^we_{suffix} === 1'bx || ^addr_{suffix} === 1'bx) begin\n" + ) + out_fh.write( + " // Unknown write enable or address ? corrupt entire memory\n" + ) + out_fh.write(" for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1)\n") + out_fh.write(" mem[i] <= {DATA_WIDTH{1'bx}};\n") + out_fh.write(f" end else if (we_{suffix}) begin\n") + out_fh.write(f" mem[addr_{suffix}] <= din_{suffix};\n") + out_fh.write(" end\n") + + def write_readback(self, suffix, out_fh): + """Writes readback section for the port group""" + + out_fh.write(f" addr_{suffix}_reg <= addr_{suffix};\n") + out_fh.write(f" dout_{suffix} <= mem[addr_{suffix}_reg];\n") diff --git a/utils/reg_file.py b/utils/reg_file.py new file mode 100644 index 0000000..d56c7db --- /dev/null +++ b/utils/reg_file.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 + +from class_memory import Memory +from regfile_verilog_exporter import RegFileVerilogExporter +from regfile_liberty_exporter import RegFileLibertyExporter + + +class RegFile(Memory): + """Base class for Reg files""" + + def __init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ): + """Initializer""" + + Memory.__init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ) + + def write_verilog_file(self, out_file_name, is_blackbox=False): + """ + Writes the verilog content to a file + + If is_blackbox, then write the port declarations only. Otherwise, write + the full RTL + """ + + exporter = RegFileVerilogExporter(self) + exporter.export_file(out_file_name, is_blackbox) + + def write_liberty_file(self, out_file_name): + """Writes the Liberty content to a file""" + + exporter = RegFileLibertyExporter(self) + exporter.export_file(out_file_name) diff --git a/utils/regfile_liberty_exporter.py b/utils/regfile_liberty_exporter.py new file mode 100644 index 0000000..5c25949 --- /dev/null +++ b/utils/regfile_liberty_exporter.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 + +from liberty_exporter import LibertyExporter + + +class RegFileLibertyExporter(LibertyExporter): + """Reg file Liberty Exporter""" + + def __init__(self, memory): + """Initializer""" + LibertyExporter.__init__(self, memory) + + def write_cell(self, out_fh): + """ + Writes the Liberty cell + + Difference is that we pass False to the rw_pin_set writer to indicate + that this isn't a RAM. + """ + + name = self._memory.get_name() + for i in range(0, self._memory.get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_rw_pin_set(out_fh, name, suffix, False) + self.write_clk_pin(out_fh) diff --git a/utils/regfile_verilog_exporter.py b/utils/regfile_verilog_exporter.py new file mode 100644 index 0000000..1541bd2 --- /dev/null +++ b/utils/regfile_verilog_exporter.py @@ -0,0 +1,54 @@ +#!/usr/bin/env python3 + +from verilog_exporter import VerilogExporter + + +class RegFileVerilogExporter(VerilogExporter): + """Reg file verilog exporter""" + + def __init__(self, memory): + """Initializer""" + VerilogExporter.__init__(self, memory) + + def export_module(self, out_fh): + """Exports the verilog module to the output stream""" + + mem = self.get_memory() + out_fh.write(f"module {mem.get_name()}\n") + out_fh.write("(\n") + for i in range(0, self.get_memory().get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_rw_port_decl_set(suffix, out_fh) + out_fh.write(" clk,\n") + out_fh.write(");\n") + out_fh.write(f" parameter DATA_WIDTH = {mem.get_width()};\n") + out_fh.write(f" parameter ADDR_WIDTH = {mem.get_addr_width()};\n") + out_fh.write("\n") + for i in range(0, self.get_memory().get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_rw_port_defn_set(suffix, out_fh) + out_fh.write(" input wire clk,\n") + out_fh.write("\n") + out_fh.write( + f" // Memory array: {mem.get_depth()} words of {mem.get_width()} bits\n" + ) + out_fh.write(" reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1];\n") + out_fh.write("\n") + for i in range(0, mem.get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.write_rw_port_always(suffix, out_fh) + out_fh.write("endmodule\n") + + def write_rw_port_always(self, suffix, out_fh): + """Writes the always @ section for the port group""" + + out_fh.write(f" // Synchronous Port {suffix.upper()}\n") + out_fh.write(" always @(posedge clk) begin\n") + out_fh.write(f" if (we_{suffix}) begin\n") + out_fh.write(f" mem[addr_{suffix}] <= din_{suffix};\n") + out_fh.write(" end\n") + out_fh.write( + f" dout_{suffix} <= mem[addr_{suffix}]; // Read occurs after write (read-after-write OK)\n" + ) + out_fh.write(" end\n") + out_fh.write("\n") diff --git a/utils/run_utils.py b/utils/run_utils.py new file mode 100644 index 0000000..e101371 --- /dev/null +++ b/utils/run_utils.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python3 + +import os +import json +from pathlib import Path + + +class RunUtils: + @staticmethod + def get_config(config_file): + """Load the JSON configuration file""" + + with open(config_file, "r") as fid: + raw = [line.strip() for line in fid if not line.strip().startswith("#")] + json_data = json.loads("\n".join(raw)) + return json_data + + @staticmethod + def ensure_results_dir(output_dir, memory_name): + """Ensures that the results directory exists""" + + p = str(Path(output_dir).expanduser().resolve(strict=False)) + results_dir = os.sep.join([p, memory_name]) + if not os.path.exists(results_dir): + os.makedirs(results_dir) + return results_dir + + @staticmethod + def get_output_file_names(memory_name, output_dir): + """ + Returns the full paths to the output file names using the memory name + as the base name + """ + + results_dir = RunUtils.ensure_results_dir(output_dir, memory_name) + lib_file_name = os.path.join(results_dir, memory_name + ".lib") + lef_file_name = os.path.join(results_dir, memory_name + ".lef") + verilog_file_name = os.path.join(results_dir, memory_name + ".v") + sv_blackbox_file_name = os.path.join(results_dir, memory_name + ".sv") + return (lib_file_name, lef_file_name, verilog_file_name, sv_blackbox_file_name) + + @staticmethod + def write_memory(memory, output_dir): + """Generates the output file names and then writes the files""" + + (lib_file_name, lef_file_name, verilog_file_name, sv_blackbox_file_name) = ( + RunUtils.get_output_file_names(memory.get_name(), output_dir) + ) + RunUtils.write_all( + memory, + lib_file_name, + lef_file_name, + verilog_file_name, + sv_blackbox_file_name, + ) + + @staticmethod + def write_all( + memory, lib_file_name, lef_file_name, verilog_file_name, sv_blackbox_file_name + ): + """Writes the files""" + + memory.write_liberty_file(lib_file_name) + memory.write_lef_file(lef_file_name) + memory.write_verilog_file(verilog_file_name) + memory.write_verilog_file(sv_blackbox_file_name, True) diff --git a/utils/single_port_ram.py b/utils/single_port_ram.py new file mode 100755 index 0000000..7f447aa --- /dev/null +++ b/utils/single_port_ram.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# +# The Verilog, LEF and Liberty output for the single port RAM matches the +# previous implementation for backward compatibility +# + +from class_memory import Memory +from ram import RAM +from single_port_ram_verilog_exporter import SinglePortRAMVerilogExporter +from single_port_ram_liberty_exporter import SinglePortRAMLibertyExporter +from single_port_ram_lef_exporter import SinglePortRAMLefExporter + + +class SinglePortRAM(RAM): + """ + Class for single port RAM + + RAM has the following pins/busses + + output [DATA_WIDTH-1:0] rd_out + input [ADDR_WIDTH-1:0] addr_in + input we_in + input [DATA_WIDTH-1:0] wd_in + input clk + input ce_in + """ + + def __init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ): + """Initializer""" + RAM.__init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ) + self.num_rw_ports = 1 + + def get_num_pins(self): + """Returns the total number of logical pins""" + # rd_out (#bits) + wd_in (#bits) + addr_in (#addr_width) + we_in/ce_in/clk + return (2 * self.get_width()) + self.get_addr_width() + 3 + + def write_verilog_file(self, out_file_name, is_blackbox=False): + """ + Writes a verilog file + + If is_blackbox is set, it writes just the port declarations and a + blackbox pragma. Otherwise, it writes the full RTL. + """ + exporter = SinglePortRAMVerilogExporter(self) + exporter.export_file(out_file_name, is_blackbox) + + def write_liberty_file(self, out_file_name): + """Writes a Liberty file""" + exporter = SinglePortRAMLibertyExporter(self) + exporter.export_file(out_file_name) + + def write_lef_file(self, out_file_name): + """Writes a LEF file""" + exporter = SinglePortRAMLefExporter(self) + exporter.export_file(out_file_name) + + +if __name__ == "__main__": # pragma: nocover + Memory.main("RAM", "SP") diff --git a/utils/single_port_ram_lef_exporter.py b/utils/single_port_ram_lef_exporter.py new file mode 100644 index 0000000..4201ecb --- /dev/null +++ b/utils/single_port_ram_lef_exporter.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 + +from lef_exporter import LefExporter + + +class SinglePortRAMLefExporter(LefExporter): + """ + The single port RAM has different port names, since they were kept for + backward compatibility reasons. So, it needs its own create_signal_pins + method to account for the names + """ + + def __init__(self, memory): + """Initializer""" + LefExporter.__init__(self, memory) + + def create_signal_pins(self, fid, pin_pitch, group_pitch): + """LEF SIGNAL PINS""" + + mem = self.get_memory() + bits = mem.get_width() + y_step = mem.get_process_data().y_step + y_step = self.write_signal_bus(fid, "rd_out", bits, False, y_step, pin_pitch) + y_step += group_pitch + y_step = self.write_signal_bus(fid, "wd_in", bits, True, y_step, pin_pitch) + y_step += group_pitch + y_step = self.write_signal_bus( + fid, "addr_in", mem.get_addr_width(), True, y_step, pin_pitch + ) + y_step += group_pitch + y_step = self.add_pin(fid, "we_in", True, y_step, pin_pitch) + y_step = self.add_pin(fid, "ce_in", True, y_step, pin_pitch) + y_step = self.add_pin(fid, "clk", True, y_step, pin_pitch) diff --git a/utils/single_port_ram_liberty_exporter.py b/utils/single_port_ram_liberty_exporter.py new file mode 100644 index 0000000..c654dc0 --- /dev/null +++ b/utils/single_port_ram_liberty_exporter.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 + +from ram_liberty_exporter import RAMLibertyExporter + + +class SinglePortRAMLibertyExporter(RAMLibertyExporter): + """ + Liberty exporter for single port SRAM. It differs from the others due to + pin differences, which were kept for backward compatibility + """ + + def __init__(self, memory): + """Initializer""" + RAMLibertyExporter.__init__(self, memory) + + def write_cell(self, out_fh): + """Writes the Liberty cell""" + + name = self._memory.get_name() + timing_data = self._memory.get_timing_data() + self.write_memory_section(out_fh) + self.write_clk_pin(out_fh) + self.write_output_bus(out_fh, name, "rd_out", True) + self.write_pin(out_fh, name, "we_in") + self.write_pin(out_fh, name, "ce_in") + self.write_address_bus(out_fh, name, "addr_in") + self.write_data_bus(out_fh, name, "wd_in", True) diff --git a/utils/single_port_ram_verilog_exporter.py b/utils/single_port_ram_verilog_exporter.py new file mode 100644 index 0000000..d0d6891 --- /dev/null +++ b/utils/single_port_ram_verilog_exporter.py @@ -0,0 +1,125 @@ +#!/usr/bin/env python3 + +from verilog_exporter import VerilogExporter + + +class SinglePortRAMVerilogExporter(VerilogExporter): + """ + Single port RAM verilog exporter. Differs from others for backward + compatibility + """ + + def __init__(self, memory): + """Initializer""" + VerilogExporter.__init__(self, memory) + + def export_module(self, out_fh): + """Exports the verilog module to the output stream""" + + mem = self.get_memory() + out_fh.write(f"module {mem.get_name()}\n") + self.write_module_ports(out_fh) + out_fh.write(" reg [BITS-1:0] mem [0:WORD_DEPTH-1];\n") + out_fh.write("\n") + out_fh.write(" integer j;\n") + out_fh.write("\n") + out_fh.write(" always @(posedge clk)\n") + out_fh.write(" begin\n") + out_fh.write(" if (ce_in)\n") + out_fh.write(" begin\n") + out_fh.write( + " //if ((we_in !== 1'b1 && we_in !== 1'b0) && corrupt_mem_on_X_p)\n" + ) + out_fh.write(" if (corrupt_mem_on_X_p &&\n") + out_fh.write(" ((^we_in === 1'bx) || (^addr_in === 1'bx))\n") + out_fh.write(" )\n") + out_fh.write(" begin\n") + out_fh.write( + " // WEN or ADDR is unknown, so corrupt entire array (using unsynthesizeable for loop)\n" + ) + out_fh.write(" for (j = 0; j < WORD_DEPTH; j = j + 1)\n") + out_fh.write(" mem[j] <= 'x;\n") + out_fh.write( + ' $display("warning: ce_in=1, we_in is %b, addr_in = %x in ' + + mem.get_name() + + '", we_in, addr_in);\n' + ) + out_fh.write(" end\n") + out_fh.write(" else if (we_in)\n") + out_fh.write(" begin\n") + out_fh.write(" mem[addr_in] <= (wd_in) | (mem[addr_in]);\n") + out_fh.write(" end\n") + out_fh.write(" // read\n") + out_fh.write(" rd_out <= mem[addr_in];\n") + out_fh.write(" end\n") + out_fh.write(" else\n") + out_fh.write(" begin\n") + out_fh.write(" // Make sure read fails if ce_in is low\n") + out_fh.write(" rd_out <= 'x;\n") + out_fh.write(" end\n") + out_fh.write(" end\n") + out_fh.write("\n") + self.write_timing_check(out_fh) + out_fh.write("endmodule\n") + + def write_module_ports(self, out_fh): + """Writes the module port declarations""" + + mem = self.get_memory() + out_fh.write("(\n") + out_fh.write(" rd_out,\n") + out_fh.write(" addr_in,\n") + out_fh.write(" we_in,\n") + out_fh.write(" wd_in,\n") + out_fh.write(" clk,\n") + out_fh.write(" ce_in\n") + out_fh.write(");\n") + out_fh.write(f" parameter BITS = {mem.get_width()};\n") + out_fh.write(f" parameter WORD_DEPTH = {mem.get_depth()};\n") + out_fh.write(f" parameter ADDR_WIDTH = {mem.get_addr_width()};\n") + out_fh.write(f" parameter corrupt_mem_on_X_p = 1;\n") + out_fh.write("\n") + out_fh.write(" output reg [BITS-1:0] rd_out;\n") + out_fh.write(" input [ADDR_WIDTH-1:0] addr_in;\n") + out_fh.write(" input we_in;\n") + out_fh.write(" input [BITS-1:0] wd_in;\n") + out_fh.write(" input clk;\n") + out_fh.write(" input ce_in;\n") + out_fh.write("\n") + + def write_timing_check(self, out_fh): + """Writes timing check placeholder data""" + + out_fh.write( + " // Timing check placeholders (will be replaced during SDF back-annotation)\n" + ) + out_fh.write(" reg notifier;\n") + out_fh.write(" specify\n") + out_fh.write(" // Delay from clk to rd_out\n") + out_fh.write(" (posedge clk *> rd_out) = (0, 0);\n") + out_fh.write("\n") + out_fh.write(" // Timing checks\n") + out_fh.write(" $width (posedge clk, 0, 0, notifier);\n") + out_fh.write(" $width (negedge clk, 0, 0, notifier);\n") + out_fh.write(" $period (posedge clk, 0, notifier);\n") + out_fh.write(" $setuphold (posedge clk, we_in, 0, 0, notifier);\n") + out_fh.write(" $setuphold (posedge clk, ce_in, 0, 0, notifier);\n") + out_fh.write(" $setuphold (posedge clk, addr_in, 0, 0, notifier);\n") + out_fh.write(" $setuphold (posedge clk, wd_in, 0, 0, notifier);\n") + out_fh.write(" endspecify\n") + out_fh.write("\n") + + def export_blackbox(self, out_fh): + """Exports the SystemVerilog blackbox to the output stream""" + + mem = self.get_memory() + addr_bus_msb = mem.get_addr_bus_msb() + data_bus_msb = mem.get_data_bus_msb() + self.export_bb_header(out_fh) + out_fh.write(f" output reg [31:0] rd_out,\n") + out_fh.write(f" input [{addr_bus_msb}:0] addr_in,\n") + out_fh.write(" input we_in,\n") + out_fh.write(f" input [{data_bus_msb}:0] wd_in,\n") + out_fh.write(" input clk,\n") + out_fh.write(" input ce_in\n") + self.export_bb_footer(out_fh) diff --git a/utils/single_port_regfile.py b/utils/single_port_regfile.py new file mode 100755 index 0000000..60cb80f --- /dev/null +++ b/utils/single_port_regfile.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 + +from class_memory import Memory +from reg_file import RegFile + + +class SinglePortRegFile(RegFile): + """ + Class for single port register file + + Reg file has the following pins/busses + + input we_a, + input [ADDR_WIDTH-1:0] addr_a, + input [DATA_WIDTH-1:0] din_a, + output [DATA_WIDTH-1:0] dout_a, + input clk, + """ + + def __init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ): + """Initializer""" + RegFile.__init__( + self, name, width_in_bits, depth, num_banks, process_data, timing_data + ) + self.num_rw_ports = 1 + + def get_num_pins(self): + """Returns the total number of logical pins""" + # din (#bits) + dout (#bits) + addr (#addr_width) + we/clk + return (2 * self.get_width()) + self.get_addr_width() + 2 + + +if __name__ == "__main__": # pragma: nocover + Memory.main("RF", "SP") diff --git a/utils/timing_data.py b/utils/timing_data.py new file mode 100644 index 0000000..7d0f239 --- /dev/null +++ b/utils/timing_data.py @@ -0,0 +1,148 @@ +#!/usr/bin/env python3 + + +class TimingData: + """Class to hold timing-related data used in Liberty file generation""" + + def __init__(self, json_data=None): + """ + Initializer sets the timing data attributes if they are defined in the + JSON data passed in. Otherwise, it uses the ASAP7 defaults + """ + + self._asap7_defaults = { + "t_setup_ns": 0.050, + # arbitrary 50ps setup + "t_hold_ns": 0.050, + # arbitrary 50ps hold + "standby_leakage_per_bank_mW": 0.1289, + "access_time_ns": 0.2183, + "pin_dynamic_power_mW": 0.0013449, + "cap_input_pf": 0.005, + "cycle_time_ns": 0.1566, + "fo4_ps": 9.0632, + } + + for attr_name, value in self._asap7_defaults.items(): + if json_data and attr_name in json_data: + setattr(self, attr_name, float(json_data[attr_name])) + else: + setattr(self, attr_name, value) + + # TODO: Arbitrary indices for the NLDM table. This is used for Clk->Q + # arcs as well as setup/hold times. We only have a single value for + # these, there are two options. + # 1. adding some sort of static variation of the single value for + # each table entry, + # 2. use the same value so all interpolated values are the same. + # The 1st is more realistic but depend on good variation values which + # is process specific and I don't have a strategy for determining decent + # variation values without breaking NDA so right now we have no + # variations. + # + # The table indices are main min/max values for interpolation. The tools + # typically don't like extrapolation so a large range is nice, but makes + # the single value strategy described above even more unrealistic. + # + # convert from ps to fs + self.fo4 = float(self.fo4_ps) / 1e3 + + # convert from mW to W + self.clkpin_dynamic_power = self.pin_dynamic_power_mW * 1e3 + self.leakage = self.standby_leakage_per_bank_mW * 1e3 + self.pin_dynamic = self.pin_dynamic_power_mW * 1e1 + + # arbitrary (1x fo4, fear that 0 would cause issues) + self.min_slew = 1 * self.fo4 + # arbitrary (25x fo4 as ~100x fanout ... i know that is not really how + # it works) + self.max_slew = 25 * self.fo4 + + self.min_driver_in_cap = self.cap_input_pf + # arbitrary (1x driver, fear that 0 would cause issues) + self.min_load = 1 * self.min_driver_in_cap + # arbitrary (100x driver) + self.max_load = 100 * self.min_driver_in_cap + + # input pin transition with between 1xfo4 and 100xfo4 + self.slew_indices = "%.3f, %.3f" % (self.min_slew, self.max_slew) + # output capacitance table between a 1x and 32x inverter + self.load_indices = "%.3f, %.3f" % (self.min_load, self.max_load) + + def get_setup_time(self): + """Returns the setup time in ns""" + return self.t_setup_ns + + def get_hold_time(self): + """Returns the hold time in ns""" + return self.t_hold_ns + + def get_access_time(self): + """Returns the access time in ns""" + return self.access_time_ns + + def get_cycle_time(self): + """Returns the cycle time in ns""" + return self.cycle_time_ns + + def get_fo4(self): + """Returns the fo4 in fs""" + return self.fo4 + + def get_fo4_ps(self): + """Returns the fo4 in ps""" + return self.fo4_ps + + def get_clkpin_dynamic_power(self): + """Returns the clkpin dynamic power in W""" + return self.clkpin_dynamic_power + + def get_leakage_power(self): + """Returns the standby leakage power in W""" + return self.leakage + + def get_leakage_power_per_bank(self): + """Returns the standby leakage power per bank in mW""" + return self.standby_leakage_per_bank_mW + + def get_pin_dynamic_power(self): + """Returns the pin dynamic power in mW * 10""" + return self.pin_dynamic + + def get_pin_dynamic_power_mw(self): + """Returns the pin dynamic power in mW""" + return self.pin_dynamic_power_mW + + def get_min_slew(self): + """Returns the min slew""" + return self.min_slew + + def get_max_slew(self): + """Returns the max slew""" + return self.max_slew + + def get_min_driver_input_cap(self): + """Returns the minimum driver input capacitance in pF""" + # TODO: consolidate min_driver_in_cap and cap_input_pf + return self.min_driver_in_cap + + def get_input_cap(self): + """Returns the input capacitance in pF""" + # TODO: consolidate min_driver_in_cap and cap_input_pf + return self.cap_input_pf + + def get_min_load(self): + """Returns the min load in pF""" + return self.min_load + + def get_max_load(self): + """Returns the max load in pF""" + return self.max_load + + def get_slew_indices_str(self): + """Returns the slew indices string""" + return self.slew_indices + + def get_load_indices_str(self): + """Returns the load indices string""" + return self.load_indices diff --git a/utils/verilog_exporter.py b/utils/verilog_exporter.py new file mode 100644 index 0000000..91e2395 --- /dev/null +++ b/utils/verilog_exporter.py @@ -0,0 +1,87 @@ +#!/usr/bin/env python3 + +from exporter import Exporter + + +class VerilogExporter(Exporter): + """Verilog exporter base""" + + def __init__(self, memory): + """Initializer""" + + Exporter.__init__(self, memory) + + def export_file(self, file_name, is_blackbox=False): + """ + Exports the verilog content to a file. + + If is_blackbox, only write the port definitions. Otherwise, write the + full RTL + """ + + with open(file_name, "w") as out_fh: + self.export(out_fh, is_blackbox) + + def export(self, out_fh, is_blackbox=False): + """ + Exports the verilog content to an output stream. + + If is_blackbox, only write the port definitions. Otherwise, write the + full RTL + """ + if is_blackbox: + self.export_blackbox(out_fh) + else: + self.export_module(out_fh) + + # -------------- Utilities -------------- + def write_rw_port_decl_set(self, suffix, out_fh): + """Writes the RW port group declarations""" + + out_fh.write(f" we_{suffix},\n") + out_fh.write(f" addr_{suffix},\n") + out_fh.write(f" din_{suffix},\n") + out_fh.write(f" dout_{suffix},\n") + + def write_rw_port_defn_set(self, suffix, out_fh): + """Writes the RW port group definitions""" + + out_fh.write(f" // Port {suffix.upper()}\n") + out_fh.write(f" input wire we_{suffix},\n") + out_fh.write(f" input wire [ADDR_WIDTH-1:0] addr_{suffix},\n") + out_fh.write(f" input wire [DATA_WIDTH-1:0] din_{suffix},\n") + out_fh.write(f" output reg [DATA_WIDTH-1:0] dout_{suffix},\n") + out_fh.write("\n") + + def export_bb_header(self, out_fh): + """Writes the SystemVerilog blackbox header""" + + out_fh.write("(* blackbox *)\n") + out_fh.write("module {} (\n".format(self.get_memory().get_name())) + + def export_bb_footer(self, out_fh): + """Writes the SystemVerilog blackbox footer""" + + out_fh.write(");\n") + out_fh.write("endmodule\n") + + def export_bb_port_decl_set(self, suffix, out_fh): + """Writes the SystemVerilog port declarations""" + + mem = self.get_memory() + addr_bus_msb = mem.get_addr_bus_msb() + data_bus_msb = mem.get_data_bus_msb() + out_fh.write(f" input we_{suffix},\n") + out_fh.write(f" input [{addr_bus_msb}:0] addr_{suffix},\n") + out_fh.write(f" input [{data_bus_msb}:0] din_{suffix},\n") + out_fh.write(f" output reg [{data_bus_msb}:0] dout_{suffix},\n") + + def export_blackbox(self, out_fh): + """Writes the blackbox content to the output stream""" + + self.export_bb_header(out_fh) + for i in range(0, self.get_memory().get_num_rw_ports()): + suffix = chr(ord("a") + i) + self.export_bb_port_decl_set(suffix, out_fh) + out_fh.write(" clk,\n") + self.export_bb_footer(out_fh)