variables.yaml

---
GENERATE_ARTIFACTS_ON_FAILURE:
  description: >
    For instance Bazel needs artifacts (.odb and .rpt files) on a failure to
    allow the user to save hours on re-running the failed step locally, but when
    working with a Makefile flow, it is more natural to fail the step and leave
    the user to manually inspect the logs and artifacts directly via the file
    system.
    Set to 1 to change the behavior to generate artifacts upon failure to e.g.
    do a global route. The exit code will still be non-zero on all other
    failures that aren't covered by the "useful to inspect the artifacts on
    failure" use-case.
    Example: just like detailed routing, a global route that fails with
    congestion, is not a build failure(as in exit code non-zero), it is a
    successful(as in zero exit code) global route that produce reports
    detailing the problem.
    Detailed route will not proceed, if there is global routing congestion
    This allows build systems, such as bazel, to create artifacts for global and
    detailed route, even if the operation had problems, without having know
    about the semantics between global and detailed route.
    Considering that global and detailed route can run for a long time and use a
    lot of memory, this allows inspecting results on a laptop for a build that
    ran on a server.
  default: 0
TNS_END_PERCENT:
  description: >
    Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all
    violating endpoints by default (reduce to 5% for runtime).
    Specifies how many percent of violating paths to fix [0-100]. Worst path
    will always be fixed.
  default: 100
  stages:
    - place
    - cts
    - floorplan
    - grt
ROUTING_LAYER_ADJUSTMENT:
  default: 0.5
  description: >
    Adjusts routing layer capacities to manage congestion and
    improve detailed routing. High values ease detailed routing
    but risk excessive detours and long global routing times,
    while low values reduce global routing failure but can
    complicate detailed routing.
    The global routing running time normally reduces
    dramatically (entirely design specific, but going from hours to
    minutes has been observed) when the value is
    low (such as 0.10).
    Sometimes, global routing will succeed with lower values and
    fail with higher values. Exploring results with different
    values can help shed light on the problem. Start with
    a too low value, such as 0.10, and bisect
    to value that works by doing multiple global routing runs.
    As a last resort, `make global_route_issue` and using
    the tools/OpenROAD/etc/whittle.py can be useful to debug
    global routing errors. If there is something specific that is
    impossible to route, such as a clock line over a macro, global
    routing will terminate with DRC errors routes that could
    have been routed were it not for the specific impossible routes.
    whittle.py should weed out the possible routes and leave
    a minimal failing case that pinpoints the problem.
  stages:
    - floorplan
    - place
    - grt
    - route
    - final
RECOVER_POWER:
  description: >
    Specifies how many percent of paths with positive slacks can be slowed for
    power savings [0-100].
  default: 0
SKIP_INCREMENTAL_REPAIR:
  default: 0
  description: >
    Skip incremental repair in global route.
  stages:
    - grt
DETAILED_METRICS:
  description: >
    If set, then calls report_metrics prior to repair operations in the CTS
    and global route stages
  default: 0
  stages:
    - cts
    - grt
CORE_UTILIZATION:
  description: |
    The core utilization percentage (0-100).
  stages:
    - floorplan
  tunable: 1
  type: float
CORE_AREA:
  description: >
    The core area specified as a list of lower-left and upper-right corners in
    microns
    (X1 Y1 X2 Y2).
  stages:
    - floorplan
  tunable: 1
REPORT_CLOCK_SKEW:
  description: >
    Report clock skew as part of reporting metrics, starting at CTS, before which
    there is no clock skew.
    This metric can be quite time-consuming, so it can be useful to disable.
  stages:
    - cts
    - grt
    - route
    - final
  default: 1
SKIP_REPORT_METRICS:
  description: >
    If set to 1, then metrics, report_metrics does nothing. Useful to speed up
    builds.
  stages:
    - floorplan
    - place
    - cts
    - grt
    - route
    - final
  default: 0
PROCESS:
  description: |
    Technology node or process in use.
CORNER:
  description: >
    PVT corner library selection. Only available for ASAP7 and GF180 PDKs.
CORNERS:
  description: >
    List of timing corner names for multi-corner analysis (e.g. "slow fast").
    When set, liberty files are loaded per corner using uppercase
    <CORNER>_LIB_FILES environment variables (e.g. corner "slow" reads
    SLOW_LIB_FILES) and timing models are generated per corner.
  stages:
    - All stages
TECH_LEF:
  description: >
    A technology LEF file of the PDK that includes all relevant information
    regarding metal layers, vias, and spacing requirements.
SC_LEF:
  description: |
    Path to technology standard cell LEF file.
GDS_FILES:
  description: |
    Path to platform GDS files.
LIB_FILES:
  description: >
    A Liberty file of the standard cell library with PVT characterization,
    input and output characteristics, timing and power definitions for each
    cell.
LIB_MODEL:
  description: >
    Selects between NLDM and CCS timing models for the ASAP7 platform.
    Valid values: NLDM (default), CCS. Used in
    flow/platforms/asap7/config.mk to pick the LIB_DIR subdirectory and
    accumulate the corresponding $(CORNER)_$(LIB_MODEL)_LIB_FILES list,
    and in flow/scripts/load.tcl to gate CCS-specific Tcl branches.
  default: NLDM
PLATFORM_TCL:
  description: |
    Specifies a Tcl script with commands to run before loading design.
DONT_USE_CELLS:
  description: |
    Dont use cells eases pin access in detailed routing.
SYNTH_GUT:
  description: >
    Load design and remove all internal logic before doing synthesis. This is
    useful when creating a mock .lef abstract that has a smaller area than the
    amount of logic would allow. bazel-orfs uses this to mock SRAMs, for
    instance.
  stages:
    - synth
  default: 0
SYNTH_HIERARCHICAL:
  description: |
    Enable to Synthesis hierarchically, otherwise considered flat synthesis.
  stages:
    - synth
  default: 0
SYNTH_MEMORY_MAX_BITS:
  description: >
    Maximum number of bits for memory synthesis.
    Ideally, real RAM or realistic fakeram should be used for RAMs
    much larger than 1024 bits.
    To temporarily ignore the RAM concerns and investigate other
    aspects of the design, consider setting `SYNTH_MOCK_LARGE_MEMORIES=1`,
    or adjusting `SYNTH_MEMORY_MAX_BITS`.
  default: 4096
  stages:
    - synth
SYNTH_MOCK_LARGE_MEMORIES:
  description: >
    Reduce Yosys inferred memories larger than SYNTH_MEMORY_MAX_BITS to 1 row.
    Yosys will generally infer memories from behavioral Verilog code, whether
    the memories are in standalone modules or instantiated within some
    larger module.
    fakeram and empty Verilog memories(blackboxes) of memories will not
    be inferred memories by Yosys and are therefore not affected by
    this variable.
    This is useful and convenient to separate the concern of instantiating
    and placing memories from investigating other issues with a design,
    though it comes at the expense of the increased accuracy that using
    realistic fakemem would provide.
    Memories with a single 1 row will of course have unrealistically good
    timing and area characteristics, but timing will still correctly terminate
    in a register.
    Large port memories, typically register files, will still have the
    retain a lot of the port logic that can be useful to investigate issues.
    This can be especially useful during development of designs where the
    behavioral model comes first and suitable memories are matched up
    when the design RTL is stable.
    A typical use case would be Chisel which will generate a behavioral model
    for a memories with the required clocks, ports, etc. in addition to a
    computer readable file with the specification of the memories that
    is used to
    [automatically](https://chipyard.readthedocs.io/en/stable/Tools/Barstools.html/)
    match up suitable memory macros later in the flow.
    During an architectural screening study, a large range of memory
    configurations can be investigated quickly with this option,
    without getting bogged down in the concern of how to realize the
    memories in silicon for emphemral RTL configurations that exist
    only long enough to run through the ORFS flow to create a table
    of some characteristics of a design configuration.
  default: 0
  stages:
    - synth
SYNTH_KEEP_MOCKED_MEMORIES:
  description: >
    When `SYNTH_MOCK_LARGE_MEMORIES=1`, setting this to 1,
    will keep mocked memories (not flattening them).
    This preserves some of the access logic complexity and
    avoids optimizations outside of the mocked memory.
  default: 1
  stages:
    - synth
SYNTH_HDL_FRONTEND:
  description: >
    Select an alternative language frontend to ingest the design. Available option
    is "slang". If the variable is empty, design is read with the Yosys read_verilog
    command.
  stages:
    - synth
SLANG_PLUGIN_PATH:
  description: >
    Path to the slang plugin for Yosys. This can be a full path to a
    custom-built plugin (e.g. for Bazel builds) or just the plugin name.
  default: slang
  stages:
    - synth
SYNTH_SLANG_ARGS:
  description: >
    Additional arguments passed to the slang frontend during synthesis.
  stages:
    - synth
  default: ""
SYNTH_BLACKBOXES:
  description: >
    List of cells treated as a black box by Yosys. With Bazel, this can be used
    to run synthesis in parallel for the large modules of the design.
    Non-existant modules are ignored silently, useful when listing modules
    statically, even if modules come and go dynamically.
  stages:
    - synth
SYNTH_CHECKPOINT:
  description: >
    Path to a Yosys RTLIL checkpoint to read in place of the default
    canonicalization checkpoint at the start of synth.tcl.
    Intended for parallel synthesis flows that reuse a checkpoint taken after
    coarse synthesis and `keep_hierarchy` have already been decided, so each
    partition skips that common prefix.
    Leave unset for the normal flow.
  stages:
    - synth
SYNTH_SKIP_KEEP:
  description: >
    Only meaningful together with SYNTH_CHECKPOINT. When set, signals that
    the supplied checkpoint is still canonical RTLIL (coarse synth and
    `keep_hierarchy` have not been run yet), so synth.tcl runs the full
    coarse+fine synthesis flattened.
    When unset and SYNTH_CHECKPOINT is used, synth.tcl assumes the
    checkpoint already has coarse synth + `keep_hierarchy` done and
    resumes from `coarse:fine`.
  stages:
    - synth
  default: 0
SYNTH_NETLIST_FILES:
  description: >
    Skips synthesis and uses the supplied netlist files. If the netlist files
    contains duplicate modules, which can happen when using hierarchical
    synthesis on indvidual netlist files and combining here,
    subsequent modules are silently ignored and only the first module is used.
  stages:
    - synth
SYNTH_CANONICALIZE_TCL:
  description: >
    Specifies a Tcl script with commands to run as part of the synth
    canonicalize step.
  stages:
    - synth
SYNTH_RETIME_MODULES:
  description: >
    *This is an experimental option and may cause adverse effects.*
    *No effort has been made to check if the retimed RTL is logically equivalent
    to the non-retimed RTL.*
    List of modules to apply automatic retiming to. These modules must not get
    dissolved and as such they should either be the top module or be included
    in SYNTH_KEEP_MODULES.
    The main use case is to quickly identify if performance can be improved by
    manually retiming the input RTL.
    Retiming will treat module ports like register endpoints/startpoints.
    The objective function of retiming isn't informed by SDC, even the clock
    period is ignored. As such, retiming will optimize for best delay
    at potentially high register number cost. Automatic retiming can produce
    suboptimal results as its timing model is crude and it doesn't find the
    optimal distribution of registers on long pipelines. See OR discussion  # 8080.
  stages:
    - synth
SYNTH_REPEATABLE_BUILD:
  description: >
    License to prune anything that makes builds less repeatable, typically
    used with Bazel to ensure that builds are bit-for-bit identical so that
    caching works optimally.
    Removes debug information that encodes paths, timestamps, etc.
  stages:
    - synth
  default: 0
SYNTH_INSBUF:
  description: >
    Insert input buffers on top-level input ports during synthesis.
    Useful to disable when doing parallel synthesis and
    concatenating netlists later as we're generating netlists
    of submodules.
  stages:
    - synth
  default: 1
DFF_MAP_FILE:
  description: |
    Optional mapping file supplied to Yosys to map D flip-flops
  stages:
    - synth
LATCH_MAP_FILE:
  description: |
    Optional mapping file supplied to Yosys to map latches
  stages:
    - synth
CLKGATE_MAP_FILE:
  description: |
    Optional mapping file supplied to Yosys to map clock gating cells
  stages:
    - synth
ADDER_MAP_FILE:
  description: |
    Optional mapping file supplied to Yosys to map adders
  stages:
    - synth
TIEHI_CELL_AND_PORT:
  description: >
    Tie high cells used in Yosys synthesis to replace a logical 1 in the
    Netlist.
  stages:
    - synth
    - floorplan
TIELO_CELL_AND_PORT:
  description: |
    Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.
  stages:
    - synth
    - floorplan
TIE_SEPARATION:
  description: |
    Distance separating tie high/low instances from the load.
  stages:
    - floorplan
  default: 0
UNSET_ABC9_BOX_CELLS:
  description: |
    List of cells to unset the abc9_box attribute on
  stages:
    - synth
EARLY_SIZING_CAP_RATIO:
  description: |
    Ratio between the input pin capacitance and the output pin load during initial gate sizing.
  stages:
    - place
MIN_BUF_CELL_AND_PORTS:
  description: |
    Used to insert a buffer cell to pass through wires. Used in synthesis.
  stages:
    - synth
ABC_CLOCK_PERIOD_IN_PS:
  description: >
    Clock period to be used by STA during synthesis. Default value read from
    `constraint.sdc`.
  stages:
    - synth
ABC_DRIVER_CELL:
  description: |
    Default driver cell used during ABC synthesis.
  stages:
    - synth
ABC_LOAD_IN_FF:
  description: |
    During synthesis set_load value used.
  stages:
    - synth
SYNTH_MINIMUM_KEEP_SIZE:
  description: >
    For hierarchical synthesis, we keep modules of larger area than given by
    this variable and flatten smaller modules.
    The area unit used is the size of a basic nand2 gate from the
    platform's standard cell library. The default value is platform specific.
  stages:
    - synth
  default: 0
SYNTH_WRAPPED_OPERATORS:
  description: >
    Synthesize multiple architectural options for each arithmetic operator in the
    design. These options are available for switching among in later stages of
    the flow.
  stages:
    - All stages
SYNTH_WRAPPED_ADDERS:
  description: >
    Specify the adder modules that can be used for synthesis, separated by commas.
    The default adder module is determined by the first element of this variable.
  stages:
    - synth
SYNTH_WRAPPED_MULTIPLIERS:
  description: >
    Specify the multiplier modules that can be used for synthesis, separated by commas.
    The default multiplier module is determined by the first element of this variable.
  stages:
    - synth
SWAP_ARITH_OPERATORS:
  description: >
    Improve timing QoR by swapping ALU and MULT arithmetic operators.
  stages:
    - All stages
FLOORPLAN_DEF:
  description: |
    Use the DEF file to initialize floorplan. Mutually exclusive with FOOTPRINT or DIE_AREA/CORE_AREA or CORE_UTILIZATION.
  stages:
    - floorplan
    - place
DONT_BUFFER_PORTS:
  description: >
    Do not buffer input/output ports during floorplanning.
  stages:
    - place
  default: 0
BUFFER_PORTS_ARGS:
  description: >
    Specify arguments to the buffer_ports call during placement. Only used if DONT_BUFFER_PORTS=0.
  stages:
    - place
REMOVE_ABC_BUFFERS:
  description: >
    Remove abc buffers from the netlist. If timing repair in floorplanning is
    taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early
    instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.
  stages:
    - floorplan
  deprecated: 1
  default: 0
BALANCE_ROWS:
  description: |
    Balance rows during placement.
  stages:
    - place
  default: 0
ADDITIONAL_SITES:
  description: >
    Passed as -additional_sites to initialize_floorplan.
  stages:
    - floorplan
PLACE_SITE:
  description: |
    Placement site for core cells defined in the technology LEF file.
  stages:
    - floorplan
  type: string
  tunable: 1
LAYER_PARASITICS_FILE:
  description: |
    Path to per layer parasitics file. Defaults to $(PLATFORM_DIR)/setRC.tcl.
  type: string
TAPCELL_TCL:
  description: |
    Path to Endcap and Welltie cells file.
  stages:
    - floorplan
MACRO_PLACEMENT_TCL:
  description: |
    Specifies the path of a TCL file on how to place macros manually.
    The user may choose to place just some of the macros in the design.
    The macro placer will handle the remaining unplaced macros.
  stages:
    - floorplan
MACRO_PLACE_HALO:
  description: >
    Horizontal/vertical halo around macros (microns). Used by automatic macro
    placement.
  stages:
    - floorplan
MACRO_BLOCKAGE_HALO:
  description: >
    Distance beyond the edges of a macro that will also be covered by the
    blockage generated for that macro.
    Note that the default macro blockage halo comes from the largest of the
    specified MACRO_PLACE_HALO x or y values. This variable overrides that
    calculation.
  stages:
    - floorplan
PDN_TCL:
  description: >
    File path which has a set of power grid policies used by pdn to be applied
    to the design, such as layers to use, stripe width and spacing to generate
    the actual metal straps.
  stages:
    - floorplan
MAKE_TRACKS:
  description: |
    Tcl file that defines add routing tracks to a floorplan.
  stages:
    - floorplan
IO_CONSTRAINTS:
  description: |
    File path to the IO constraints .tcl file. Also used for manual placement.
  stages:
    - floorplan
IO_PLACER_H:
  description: >
    A list of metal layers on which the I/O pins are placed horizontally (top and
    bottom
    of the die).
  stages:
    - place
IO_PLACER_V:
  description: >
    A list of metal layers on which the I/O pins are placed vertically (sides of the
    die).
  stages:
    - place
GUI_TIMING:
  description: >
    Load timing information when opening GUI. For large designs, this can be
    quite time consuming. Useful to disable when investigating non-timing
    aspects like floorplan, placement, routing, etc.
  default: 1
FILL_CELLS:
  description: >
    Fill cells are used to fill empty sites. If not set or empty, fill cell
    insertion is skipped.
  stages:
    - route
TAP_CELL_NAME:
  description: |
    Name of the cell to use in tap cell insertion.
CELL_PAD_IN_SITES_GLOBAL_PLACEMENT:
  description: >
    Cell padding on both sides in site widths to ease routability during global
    placement.
  stages:
    - place
    - floorplan
  default: 0
  type: int
  tunable: 1
DETAIL_PLACEMENT_ARGS:
  description: >
    Specify arguments to the detailed_placement call during placement.
  stages:
    - place
CELL_PAD_IN_SITES_DETAIL_PLACEMENT:
  description: >
    Cell padding on both sides in site widths to ease routability in detail
    placement.
  stages:
    - place
    - cts
    - grt
  default: 0
  type: int
  tunable: 1
PLACE_PINS_ARGS:
  description: |
    Arguments to place_pins
  stages:
    - place
PLACE_DENSITY:
  description: >
    The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread.
    The intended effort is also communicated by this parameter. Use a low value for
    faster builds and higher value for better quality of results.
    If a too low value is used, the placer will not be able to place all cells and
    a recommended minimum placement density can be found in the logs.
    A too high value can lead to excessive runtimes, even timeouts and subtle failures
    in the flow after placement, such as in CTS or global routing when timing repair
    fails.
    The default is platform specific.
  stages:
    - floorplan
    - place
PLACE_DENSITY_LB_ADDON:
  description: >
    Check the lower boundary of the PLACE_DENSITY and add
    PLACE_DENSITY_LB_ADDON if it exists.
  stages:
    - floorplan
    - place
  tunable: 1
  type: float
REPAIR_PDN_VIA_LAYER:
  description: |
    Remove power grid vias which generate DRC violations after detailed routing.
GLOBAL_PLACEMENT_ARGS:
  description: >
    Use additional tuning parameters during global placement other than default
    args defined in global_place.tcl.
  stages:
    - place
ENABLE_DPO:
  description: |
    Enable detail placement with improve_placement feature.
  default: 1
DPO_MAX_DISPLACEMENT:
  description: |
    Specifies how far an instance can be moved when optimizing.
  default: 5 1
DPL_USE_OLD_DIAMOND:
  description: |
    Use the former diamond search legalizer for detailed placement instead of the default negotiation legalizer.
  default: 0
  stages:
    - place
    - cts
    - grt
GPL_TIMING_DRIVEN:
  description: |
    Specifies whether the placer should use timing driven placement.
  stages:
    - place
  default: 1
GPL_ROUTABILITY_DRIVEN:
  description: |
    Specifies whether the placer should use routability driven placement.
  stages:
    - place
  default: 1
GPL_KEEP_OVERFLOW:
  description: >
    Passed as -keep_resize_below_overflow to global_placement.
    Only used when GPL_TIMING_DRIVEN is enabled.
  stages:
    - place
MIN_PLACE_STEP_COEF:
  description: >
    Sets the minimum phi coefficient (pcof_min / µ_k Lower Bound) for global
    placement optimization. This parameter controls the step size lower bound
    in the RePlAce Nesterov optimization algorithm. Lower values may improve
    convergence but can increase runtime.
    Valid range: 0.95-1.05
  default: 0.95
  stages:
    - place
  tunable: 1
  type: float
MAX_PLACE_STEP_COEF:
  description: >
    Sets the maximum phi coefficient (pcof_max / µ_k Upper Bound) for global
    placement optimization. This parameter controls the step size upper bound
    in the RePlAce Nesterov optimization algorithm. Higher values allow more
    aggressive optimization but may risk divergence.
    Valid range: 1.00-1.20
  default: 1.05
  stages:
    - place
  tunable: 1
  type: float
CAP_MARGIN:
  description: >
    Specifies a capacitance margin when fixing max capacitance violations. This
    option allows you to overfix.
  tunable: 1
SLEW_MARGIN:
  description: >
    Specifies a slew margin when fixing max slew violations. This option allows
    you to overfix.
  tunable: 1
CTS_ARGS:
  description: |
    Override `clock_tree_synthesis` arguments.
  stages:
    - cts
CTS_SNAPSHOTS:
  description: |
    Create ODB/SDC files at different stages of CTS.
  stages:
    - cts
  default: 0
HOLD_SLACK_MARGIN:
  description: >
    Specifies a time margin for the slack when fixing hold violations.
    This option allows you to overfix or underfix (negative value, terminate
    retiming before 0 or positive slack).
    floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin).
    This avoids overrepair in floorplan for hold by default, but allows skipping
    hold repair using a negative HOLD_SLACK_MARGIN.
    Exiting timing repair early is useful in exploration where
    the .sdc has a fixed clock period at the design's target clock period and where
    HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running
    times) when exploring different parameter settings.
    When an ideal clock is used, that is before CTS,
    a clock insertion delay of 0 is used in timing paths. This creates
    a mismatch between macros that have a .lib file from after CTS, when
    the clock is propagated. To mitigate this, OpenSTA will use subtract
    the clock insertion delay of macros when calculating timing with ideal
    clock. Provided that min_clock_tree_path
    and max_clock_tree_path are in the .lib file, which is the case for
    macros built with OpenROAD. This is less accurate than if OpenROAD had
    created a placeholder clock tree for timing estimation purposes
    prior to CTS.
    There will inevitably be inaccuracies in the timing calculation prior
    to CTS. Use a slack margin that is low enough, even negative, to
    avoid overrepair. Inaccuracies in the timing prior to CTS can also
    lead to underrepair, but there no obvious and simple way to avoid
    underrapir in these cases.
    Overrepair can lead to excessive runtimes in repair or too much buffering
    being added, which can present itself as congestion of hold cells or
    buffer cells.
    Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration
    when trying to find the minimum clock period for a design.
    The SDC_FILE for a design can be quite complicated and instead of
    modifying the clock period in the SDC_FILE, which can be non-trivial,
    the clock period can be fixed at the target frequency and the
    SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible
    current minimum clock period.
  stages:
    - cts
    - floorplan
    - grt
  default: 0
SETUP_SLACK_MARGIN:
  description: |
    Specifies a time margin for the slack when fixing setup violations.
    This option allows you to overfix or underfix(negative value, terminate
    retiming before 0 or positive slack).
    See HOLD_SLACK_MARGIN for more details.
  stages:
    - cts
    - floorplan
    - grt
  default: 0
  tunable: 1
SETUP_MOVE_SEQUENCE:
  description: >
    Passed as -sequence to repair_timing. This should be a string of move
    keywords separated by commas.
  stages:
    - cts
    - floorplan
    - grt
SKIP_GATE_CLONING:
  description: >
    Do not use gate cloning transform to fix timing violations (default: use
    gate cloning).
  stages:
    - cts
    - floorplan
    - grt
SKIP_LAST_GASP:
  description: >
    Do not use last gasp optimization to fix timing violations (default: use
    gate last gasp).
  stages:
    - cts
    - floorplan
    - grt
SKIP_BUFFER_REMOVAL:
  description: >
    Passed as -skip_buffer_removal to repair_timing. Do not remove buffers
    as a transform to fix timing violations (default: allow buffer removal).
  stages:
    - cts
    - floorplan
    - grt
SKIP_PIN_SWAP:
  description: >
    Do not use pin swapping as a transform to fix timing violations (default:
    use pin swapping).
  stages:
    - cts
    - floorplan
    - grt
SKIP_VT_SWAP:
  description: >
    Do not perform VT swap to improve QoR (default: do VT swap).
  stages:
    - cts
    - floorplan
    - grt
SKIP_CRIT_VT_SWAP:
  description: >
    Do not perform VT swap on critical cells to improve QoR (default: do critical
    VT swap).
    This is an additional VT swap on critical cells that remain near the end of setup
    fixing.
    If SKIP_VT_SWAP is set to 1, this also disables critical cell VT swap.
  stages:
    - cts
    - floorplan
    - grt
SKIP_CTS_REPAIR_TIMING:
  description: >
    Skipping CTS repair, which can take a long time, can be useful in
    architectural exploration or when getting CI up and running.
  stages:
    - cts
  default: 0
SKIP_REPAIR_TIE_FANOUT:
  description: >
    Skip repair_tie_fanout at floorplan step.
  stages:
    - floorplan
  default: 0
MIN_ROUTING_LAYER:
  description: |
    The lowest metal layer name to be used in routing.
  stages:
    - floorplan
    - place
    - grt
    - route
    - final
MAX_ROUTING_LAYER:
  description: |
    The highest metal layer name to be used in routing.
  stages:
    - floorplan
    - place
    - grt
    - route
    - final
MIN_CLK_ROUTING_LAYER:
  description: >
    The lowest metal layer name to be used for clock-net routing in global
    routing. Used in flow/platforms/*/fastroute.tcl as the lower bound of
    `set_routing_layers -clock`. Typically higher than MIN_ROUTING_LAYER so
    clock nets prefer the upper, lower-RC layers. No `stages:` list because
    floorplan.tcl also `source`s the platform fastroute.tcl.
VIA_IN_PIN_MIN_LAYER:
  description: >
    Passed as -via_in_pin_bottom_layer to pin_access and detailed_route.
  stages:
    - grt
    - route
VIA_IN_PIN_MAX_LAYER:
  description: >
    Passed as -via_in_pin_top_layer to pin_access and detailed_route.
  stages:
    - grt
    - route
DETAILED_ROUTE_ARGS:
  description: |
    Add additional arguments for debugging purposes during detail route.
  stages:
    - route
DISABLE_VIA_GEN:
  description: >
    Passed as -disable_via_gen to detailed_route.
  stages:
    - route
MACRO_EXTENSION:
  description: |
    Sets the number of GCells added to the blockages boundaries from macros.
DETAILED_ROUTE_END_ITERATION:
  description: >
    Maximum number of iterations.
  default: 64
  stages:
    - route
OR_K:
  description: >
    Passed as -or_k to detailed routing.
  stages:
    - route
OR_SEED:
  description: >
    Passed as -or_seed to detailed routing.
  stages:
    - route
RCX_RULES:
  description: |
    RC Extraction rules file path.
SET_RC_TCL:
  description: |
    Metal & Via RC definition file path.
FILL_CONFIG:
  description: |
    JSON rule file for metal fill during chip finishing.
KLAYOUT_TECH_FILE:
  description: |
    A mapping from LEF/DEF to GDS using the KLayout tool.
IR_DROP_LAYER:
  description: |
    Default metal layer to report IR drop.
PLATFORM:
  required: true
  description: |
    Specifies process design kit or technology node to be used.
DESIGN_NAME:
  required: true
  description: |
    The name of the top-level module of the design.
VERILOG_FILES:
  required: true
  description: >
    The path to the design Verilog/SystemVerilog files providing a description
    of modules.
  stages:
    - synth
VERILOG_DEFINES:
  description: >
    Preprocessor defines passed to the language frontend.
    Example: `-D HPDCACHE_ASSERT_OFF`
  stages:
    - synth
SDC_FILE:
  required: true
  description: |
    The path to design constraint (SDC) file.
  stages:
    - synth
SDC_GUT:
  description: >
    Load design and remove all internal logic before doing synthesis. This is
    useful when creating a mock .lef abstract that has a smaller area than the
    amount of logic would allow. bazel-orfs uses this to mock SRAMs, for
    instance.
  stages:
    - synth
ADDITIONAL_FILES:
  description: |
    Additional files to be added to `make issue` archive.
ADDITIONAL_LEFS:
  description: >
    Hardened macro LEF view files listed here. The LEF information of the
    macros is immutable and used throughout all stages. Stored in the .odb file.
ADDITIONAL_LIBS:
  description: >
    Hardened macro library files listed here. The library information is
    immutable and used throughout all stages. Not stored in the .odb file.
ADDITIONAL_GDS:
  description: |
    Hardened macro GDS files listed here.
  stages:
    - final
VERILOG_INCLUDE_DIRS:
  description: |
    Specifies the include directories for the Verilog input files.
  stages:
    - synth
DESIGN_NICKNAME:
  description: >
    DESIGN_NICKNAME just changes the directory name that ORFS outputs to be
    DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or
    conflicts with a different design.
ABC_AREA:
  description: |
    Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.
  stages:
    - synth
  default: 0
PWR_NETS_VOLTAGES:
  description: |
    Used for IR Drop calculation.
  stages:
    - final
GND_NETS_VOLTAGES:
  description: |
    Used for IR Drop calculation.
  stages:
    - final
BLOCKS:
  description: >
    Blocks used as hard macros in a hierarchical flow. Do note that you have to
    specify block-specific inputs file in the directory mentioned by Makefile.
CDL_FILES:
  description: |
    Insert additional Circuit Description Language (`.cdl`) netlist files.
DFF_LIB_FILE:
  description: >
    Single Liberty file for flip-flop technology mapping (dfflibmap) during
    synthesis. Takes precedence over DFF_MAP_FILE when set.
  stages:
    - synth
SYNTH_KEEP_MODULES:
  description: |
    Mark modules to keep from getting removed in flattening.
  stages:
    - synth
SYNTH_ARGS:
  description: |
    Optional synthesis variables for yosys.
  stages:
    - synth
SYNTH_OPERATIONS_ARGS:
  description: >
    Extra arguments appended to the Yosys synth command operations list.
    When set, replaces the default Kogge-Stone adder extra-map.
  stages:
    - synth
SYNTH_HIER_SEPARATOR:
  description: |
    Separator used for the synthesis flatten stage.
  default: .
  stages:
    - synth
SYNTH_OPT_HIER:
  description: |
    Optimize constants across hierarchical boundaries.
  stages:
    - synth
VERILOG_TOP_PARAMS:
  description: |
    Apply toplevel params (if exist). Passed in as a list of key value pairs
    in tcl syntax; separated by spaces: PARAM1 VALUE1 PARAM2 VALUE2
  stages:
    - synth
CORE_ASPECT_RATIO:
  description: >
    The core aspect ratio (height / width).
    This variable is only used when `CORE_UTILIZATION` is set.
  stages:
    - floorplan
  default: 1.0
  tunable: 1
  type: float
CORE_MARGIN:
  description: >
    The margin between the core area and die area, specified in microns.
    Allowed values are either one value for all margins or a set of four
    values, one for each margin. The order of the four values are:
    `{bottom top left right}`.
    This variable is only used when `CORE_UTILIZATION` is set.
  stages:
    - floorplan
  default: 1.0
  tunable: 1
  type: float
DIE_AREA:
  description: >
    The die area specified as a list of lower-left and upper-right corners in
    microns
    (X1 Y1 X2 Y2).
  stages:
    - floorplan
  tunable: 1
MACRO_ROWS_HALO_X:
  description: >
    Horizontal distance between the edge of the macro and the beginning of the
    rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks
    design.
  stages:
    - floorplan
MACRO_ROWS_HALO_Y:
  description: >
    Vertical distance between the edge of the macro and the beginning of the
    rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks
    design.
  stages:
    - floorplan
MACRO_WRAPPERS:
  description: |
    The wrapper file that replaces existing macros with their wrapped version.
  stages:
    - floorplan
CTS_BUF_DISTANCE:
  description: |
    Distance (in microns) between buffers.
  stages:
    - cts
  tunable: 1
  type: float
CTS_BUF_LIST:
  description: |
    List of cells used to construct the clock tree. Overrides buffer inference.
  stages:
    - cts
CLUSTER_FLOPS:
  description: >
    Enable clustering of flip-flops into multi-bit flip-flops, if the platform
    PDK includes multi-bit flip-flops
  stages:
    - place
  default: 0
CLUSTER_FLOPS_ARGS:
  description: >
    Additional arguments passed to the cluster_flops command.
    Only used when CLUSTER_FLOPS is set.
  stages:
    - place
  default: ""
CTS_CLUSTER_DIAMETER:
  description: >
    Maximum diameter (in microns) of sink cluster.
  stages:
    - cts
  tunable: 1
  type: float
CTS_CLUSTER_SIZE:
  description: >
    Maximum number of sinks per cluster.
  stages:
    - cts
  tunable: 1
  type: int
CTS_LIB_NAME:
  description: |
    Name of the Liberty library to use in selecting the clock buffers.
  stages:
    - cts
CTS_SNAPSHOT:
  description: |
    Creates ODB/SDC files prior to clock net and setup/hold repair.
  stages:
    - cts
POST_CTS_TCL:
  description: |
    Specifies a Tcl script with commands to run after CTS is completed.
  stages:
    - cts
POST_DENSITY_FILL_TCL:
  description: |
    Specifies a Tcl script with commands to run after density fill.
  stages:
    - final
POST_DETAIL_PLACE_TCL:
  description: |
    Specifies a Tcl script with commands to run after detailed placement.
  stages:
    - place
POST_DETAIL_ROUTE_TCL:
  description: |
    Specifies a Tcl script with commands to run after detailed route.
  stages:
    - route
POST_FILLCELL_TCL:
  description: |
    Specifies a Tcl script with commands to run after fillcell insertion.
  stages:
    - route
POST_FINAL_REPORT_TCL:
  description: |
    Specifies a Tcl script with commands to run after final report generation.
  stages:
    - final
POST_FLOORPLAN_TCL:
  description: |
    Specifies a Tcl script with commands to run after floorplan is completed.
  stages:
    - floorplan
POST_GLOBAL_PLACE_SKIP_IO_TCL:
  description: |
    Specifies a Tcl script with commands to run after global placement (skip IO).
  stages:
    - place
POST_GLOBAL_PLACE_TCL:
  description: |
    Specifies a Tcl script with commands to run after global placement.
  stages:
    - place
POST_GLOBAL_ROUTE_TCL:
  description: |
    Specifies a Tcl script with commands to run after global route.
  stages:
    - grt
POST_IO_PLACEMENT_TCL:
  description: |
    Specifies a Tcl script with commands to run after IO placement.
  stages:
    - place
POST_MACRO_PLACE_TCL:
  description: |
    Specifies a Tcl script with commands to run after macro placement.
  stages:
    - floorplan
POST_PDN_TCL:
  description: |
    Specifies a Tcl script with commands to run after PDN generation.
  stages:
    - floorplan
POST_REPAIR_TIMING_POST_PLACE_TCL:
  description: |
    Specifies a Tcl script with commands to run after post-place timing repair.
  stages:
    - place
POST_RESIZE_TCL:
  description: |
    Specifies a Tcl script with commands to run after resize.
  stages:
    - place
POST_SYNTH_TCL:
  description: |
    Specifies a Tcl script with commands to run after synthesis ODB generation.
  stages:
    - synth
POST_TAPCELL_TCL:
  description: |
    Specifies a Tcl script with commands to run after tapcell.
  stages:
    - floorplan
PRE_CTS_TCL:
  description: |
    Specifies a Tcl script with commands to run before CTS.
  stages:
    - cts
PRE_DENSITY_FILL_TCL:
  description: |
    Specifies a Tcl script with commands to run before density fill.
  stages:
    - final
PRE_DETAIL_PLACE_TCL:
  description: |
    Specifies a Tcl script with commands to run before detailed placement.
  stages:
    - place
PRE_DETAIL_ROUTE_TCL:
  description: |
    Specifies a Tcl script with commands to run before detailed route.
  stages:
    - route
PRE_FILLCELL_TCL:
  description: |
    Specifies a Tcl script with commands to run before fillcell insertion.
  stages:
    - route
PRE_FINAL_REPORT_TCL:
  description: |
    Specifies a Tcl script with commands to run before final report generation.
  stages:
    - final
PRE_FLOORPLAN_TCL:
  description: |
    Specifies a Tcl script with commands to run before floorplan.
  stages:
    - floorplan
PRE_GLOBAL_PLACE_SKIP_IO_TCL:
  description: |
    Specifies a Tcl script with commands to run before global placement (skip IO).
  stages:
    - place
PRE_GLOBAL_PLACE_TCL:
  description: |
    Specifies a Tcl script with commands to run before global placement.
  stages:
    - place
PRE_IO_PLACEMENT_TCL:
  description: |
    Specifies a Tcl script with commands to run before IO placement.
  stages:
    - place
PRE_MACRO_PLACE_TCL:
  description: |
    Specifies a Tcl script with commands to run before macro placement.
  stages:
    - floorplan
PRE_PDN_TCL:
  description: |
    Specifies a Tcl script with commands to run before PDN generation.
  stages:
    - floorplan
PRE_REPAIR_TIMING_POST_PLACE_TCL:
  description: |
    Specifies a Tcl script with commands to run before post-place timing repair.
  stages:
    - place
PRE_RESIZE_TCL:
  description: |
    Specifies a Tcl script with commands to run before resize.
  stages:
    - place
PRE_SYNTH_TCL:
  description: |
    Specifies a Tcl script with commands to run before synthesis ODB generation.
  stages:
    - synth
PRE_TAPCELL_TCL:
  description: |
    Specifies a Tcl script with commands to run before tapcell.
  stages:
    - floorplan
FASTROUTE_TCL:
  description: |
    Specifies a Tcl script with commands to run before FastRoute.
USE_FILL:
  description: >
    Whether to perform metal density filling.
  default: 0
SEAL_GDS:
  description: |
    Seal macro to place around the design.
ABSTRACT_SOURCE:
  description: |
    Which .odb file to use to create abstract
  stages:
    - generate_abstract
PRE_GLOBAL_ROUTE_TCL:
  description: |
    Specifies a Tcl script with commands to run before global route.
  stages:
    - grt
GLOBAL_ROUTE_ARGS:
  description: >
    Replaces default arguments for global route.
  stages:
    - grt
  default: -congestion_iterations 30 -congestion_report_iter_step 5 -verbose
ENABLE_RESISTANCE_AWARE:
  description: >
    Passed as -resistance_aware to global_route.
  stages:
    - grt
MATCH_CELL_FOOTPRINT:
  description: >
    Enforce sizing operations to only swap cells that have the same layout
    boundary.
  stages:
    - floorplan
    - place
    - cts
    - route
  default: 0
RTLMP_MAX_LEVEL:
  description: >
    Maximum depth of the physical hierarchy tree.
  default: 2
  stages:
    - floorplan
RTLMP_MAX_INST:
  description: >
    Maximum number of standard cells in a cluster. If unset, rtl_macro_placer
    will calculate a value based on the design attributes.
  stages:
    - floorplan
RTLMP_MIN_INST:
  description: >
    Minimum number of standard cells in a cluster. If unset, rtl_macro_placer
    will calculate a value based on the design attributes.
  stages:
    - floorplan
RTLMP_MAX_MACRO:
  description: >
    Maximum number of macros in a cluster. If unset, rtl_macro_placer will
    calculate a value based on the design attributes.
  stages:
    - floorplan
RTLMP_MIN_MACRO:
  description: >
    Minimum number of macros in a cluster. If unset, rtl_macro_placer will
    calculate a value based on the design attributes.
  stages:
    - floorplan
RTLMP_MIN_AR:
  description: >
    Specifies the minimum aspect ratio (height/width).
  default: 0.33
  stages:
    - floorplan
RTLMP_AREA_WT:
  description: >
    Weight for the area of the current floorplan.
  default: 0.1
  stages:
    - floorplan
RTLMP_WIRELENGTH_WT:
  description: >
    Weight for half-perimiter wirelength.
  default: 100.0
  stages:
    - floorplan
RTLMP_OUTLINE_WT:
  description: >
    Weight for violating the fixed outline constraint, meaning that all
    clusters should be placed within the shape of their parent cluster.
  default: 100.00
  stages:
    - floorplan
RTLMP_BOUNDARY_WT:
  description: >
    Weight for the boundary or how far the hard macro clusters are from
    boundaries.
  default: 50.0
  stages:
    - floorplan
RTLMP_NOTCH_WT:
  description: >
    Weight for the notch, or the existence of dead space that cannot be used
    for placement and routing.
  default: 50.0
  stages:
    - floorplan
RTLMP_RPT_DIR:
  description: >
    Path to the directory where reports are saved.
  stages:
    - floorplan
RTLMP_FENCE_LX:
  description: >
    Defines the lower left X coordinate for the global fence bounding box in
    microns.
  default: 0.0
  stages:
    - floorplan
RTLMP_FENCE_LY:
  description: >
    Defines the lower left Y coordinate for the global fence bounding box in
    microns.
  default: 0.0
  stages:
    - floorplan
RTLMP_FENCE_UX:
  description: >
    Defines the upper right X coordinate for the global fence bounding box in
    microns.
  default: 0.0
  stages:
    - floorplan
RTLMP_FENCE_UY:
  description: >
    Defines the upper right Y coordinate for the global fence bounding box in
    microns.
  default: 0.0
  stages:
    - floorplan
RTLMP_ARGS:
  description: >
    Overrides all other RTL macro placer arguments.
  stages:
    - floorplan
GDS_ALLOW_EMPTY:
  description: >
    Single regular expression of module names of macros that have no .gds file
  stages:
    - final
RUN_SCRIPT:
  description: >
    Path to script to run from `make run`, python or tcl script detected by
    .py or .tcl extension.
RUN_LOG_NAME_STEM:
  description: >
    Stem of the log file name, the log file will be named
    `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.
  default: run
YOSYS_FLAGS:
  description: >
    Flags to pass to yosys.
  stages:
    - synth
  default: -v 3
FOOTPRINT:
  description: |
    Custom footprint definition file for ICeWall-based floorplan initialization. Mutually exclusive with FLOORPLAN_DEF or DIE_AREA/CORE_AREA or CORE_UTILIZATION.
  stages:
    - floorplan
FOOTPRINT_TCL:
  description: |
    Specifies a Tcl script with custom footprint-related commands for floorplan setup.
  stages:
    - floorplan
FLOW_VARIANT:
  description: >
    Flow variant to use, used in the flow variant directory name.
  default: base
RULES_JSON:
  description: >
    json files with the metrics baseline regression rules.
    In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json,
    but ORFS does not mandate the users source directory layout and
    this can be placed elsewhere when the user sets up an ORFS
    config.mk or from bazel-orfs.
  stages:
    - test
SKIP_ANTENNA_REPAIR_PRE_GRT:
  default: 0
  description: >
    Skips antenna repair pre-global routing.
  stages:
    - grt
SKIP_ANTENNA_REPAIR_POST_DRT:
  default: 0
  description: >
    Skips antenna repair post-detailed routing.
  stages:
    - route
SKIP_ANTENNA_REPAIR:
  default: 0
  description: >
    Skips antenna repair entirely.
  stages:
    - grt
SKIP_DETAILED_ROUTE:
  default: 0
  description: >
    Skips detailed route.
  stages:
    - route
    - final
MAX_REPAIR_ANTENNAS_ITER_DRT:
  default: 5
  description: >
    Defines the maximum number of iterations post-detailed routing repair
    antennas will run.
  stages:
    - route
MAX_REPAIR_ANTENNAS_ITER_GRT:
  default: 5
  description: >
    Defines the maximum number of iterations post global routing repair
    antennas will run.
  stages:
    - grt
OPENROAD_HIERARCHICAL:
  description: >
    Feature toggle to enable to run OpenROAD in hierarchical mode,
    otherwise considered flat. Will eventually be the default and
    this option will be retired.
  default: 0
  stages:
    - All stages
MAX_REPAIR_TIMING_ITER:
  description: >
    Maximum number of iterations for repair setup and repair hold.
  stages:
    - cts
    - floorplan
    - grt
    - place
NUM_CORES:
  description: >
    Passed to `openroad -threads $(NUM_CORES)`, defaults to numbers
    of cores in system as determined by system specific code in Makefile,
    `nproc` is tried first.
    OpenROAD does not limit itself to this number of cores across
    OpenROAD running instances, which can lead to overprovisioning
    in contexts such as bazel-orfs where there could be many
    routing, or place jobs running at the same time.
  stages:
    - All stages
KEEP_VARS:
  description: >
    Feature toggle to keep intermediate variables during the flow.
    This is useful for the single-run flow, where all stages of the flow
    are run in a single OpenROAD instance.
  default: 0
  stages:
    - All stages
WRITE_ODB_AND_SDC_EACH_STAGE:
  description: >
    Save out .sdc and .odb file after each stage, useful to disable
    when using a single OpenROAD instance to run all stages of the flow.
  stages:
    - All stages
  default: 1
LEC_CHECK:
  description: >
    Perform a formal equivalence check between before and after netlists.
    If this fails, report an issue to OpenROAD.
  default: 0
  stages:
    - cts
LEC_AUX_VERILOG_FILES:
  description: >
    Additional Verilog files (e.g. blackbox stubs) to include in LEC
    equivalence checks. Appended to the generated Verilog netlist before
    running the formal equivalence check.
  stages:
    - cts
REMOVE_CELLS_FOR_LEC:
  description: >
    String patterns directly passed to write_verilog -remove_cells <> for
    lec checks.
  type: string
ASAP7_USE_VT:
  description: >
    A space separated list of VT options to use with the ASAP7 standard cell library:
    RVT, LVT, SLVT.
  stages:
    - All stages
  default: RVT
CACHED_REPORTS:
  description: >
    List of pre-existing report files to copy into the reports directory
    before synthesis. Used when reusing prior synthesis results with
    SYNTH_NETLIST_FILES.
  stages:
    - synth
CDL_FILE:
  description: >
    CDL master netlist file used as the -masters argument to write_cdl
    for generating Circuit Description Language output.
  stages:
    - final