Commit 126fc13
committed
use Yosys 0.59
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>1 parent 6f50804 commit 126fc13
1 file changed
Lines changed: 1 addition & 1 deletion
- .github/actions/setup-build-env/action.yml+62-5
- .github/actions/setup-iverilog/action.yml+70
- .github/workflows/codeql.yml+6-3
- .github/workflows/extra-builds.yml+2-2
- .github/workflows/test-build.yml+12-41
- .github/workflows/test-compile.yml+4-1
- .github/workflows/test-sanitizers.yml+4-46
- .github/workflows/wheels.yml+6-6
- .github/workflows/wheels/_run_cibw_linux.py+2-2
- .gitignore-1
- Brewfile+1-1
- CHANGELOG+19-1
- Makefile+20-14
- README.md+4-4
- abc+1-1
- backends/cxxrtl/cxxrtl_backend.cc+1-15
- backends/rtlil/rtlil_backend.cc+2-1
- backends/verilog/verilog_backend.cc+3-2
- docs/source/cmd/index_techlibs_ecp5.rst-5
- docs/source/cmd/index_techlibs_lattice_nexus.rst-5
- docs/source/conf.py+2-2
- docs/source/getting_started/installation.rst+40-34
- docs/source/requirements.txt+1
- docs/source/using_yosys/pyosys.rst+8
- docs/source/using_yosys/verilog.rst+17-9
- docs/source/yosys_internals/extending_yosys/test_suites.rst+66-3
- docs/source/yosys_internals/formats/rtlil_rep.rst+9-8
- flake.nix+1-1
- frontends/ast/simplify.cc+51-21
- frontends/verific/verific.cc+1
- frontends/verilog/preproc.cc+1-5
- frontends/verilog/verilog_parser.y+22-2
- kernel/hashlib.h+1-1
- kernel/io.cc+19
- kernel/io.h+2
- kernel/rtlil.cc+523-488
- kernel/rtlil.h+228-43
- kernel/utils.h+18-6
- passes/cmds/show.cc+4-3
- passes/cmds/timeest.cc+40-15
- passes/hierarchy/hierarchy.cc+48-21
- passes/techmap/abc.cc+54-56
- passes/techmap/abc9_ops.cc+2-2
- passes/techmap/dfflibmap.cc+9-2
- passes/techmap/libparse.cc+147-83
- passes/techmap/libparse.h+9-5
- pyosys/generator.py+76-33
- pyosys/wrappers_tpl.cc+7-1
- pyproject.toml+1-1
- setup.py+1
- techlibs/gatemate/Makefile.inc+4
- techlibs/gowin/adc.v+260
- techlibs/gowin/cells_xtra.py+10
- techlibs/gowin/cells_xtra_gw5a.v+263-83
- tests/liberty/XNOR2X1.lib.verilogsim.ok+1-1
- tests/liberty/dff.lib+2-2
- tests/liberty/dff.lib.filtered.ok+2-2
- tests/liberty/dff.lib.verilogsim.ok+4-4
- tests/liberty/normal.lib.verilogsim.ok+21-21
- tests/liberty/unquoted.lib+60
- tests/liberty/unquoted.lib.filtered.ok+60
- tests/liberty/unquoted.lib.verilogsim.ok+39
- tests/pyosys/test_idstring_lifetime.py+28
- tests/pyosys/test_indirect_inheritance.py+15
- tests/pyosys/test_monitor.py+1-1
- tests/svinterfaces/positional_args.ys+33
- tests/svinterfaces/run-test.sh+1
- tests/techmap/abc_state.ys+26
- tests/techmap/dfflibmap_dff_not_next.lib+24
- tests/techmap/dfflibmap_formal.ys+31
- tests/unit/Makefile+2-2
- tests/unit/techmap/libparseTest.cc+6-1
- tests/various/timeest.ys+12
- tests/verific/port_bus_order.ys+13
- tests/verilog/.gitignore+2
- tests/verilog/local_include.sh+30
- tests/verilog/local_include.v+4
- tests/verilog/package_import_specific.sv+14
- tests/verilog/package_import_specific.ys+5
- tests/verilog/package_import_specific_module.sv+16
0 commit comments