gt2n: add jpeg design as a third reference

Adds jpeg_encoder as a larger reference benchmark alongside gcd and
aes -- representative of designs that meaningfully exercise the
upper-stack routing layers and the multi-W / multi-Vt library menu.
config.mk mirrors the asap7 / nangate45 jpeg configurations
(ABC_AREA=1, TNS_END_PERCENT=100, conservative CORE_UTILIZATION).

constraint.sdc uses a 1500 ps clock as a first-pass loose target;
period_min lands around 950 ps so the design has substantial
headroom to tighten once OpenRCX rules replace the analytical RC.

Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>

Author: mguthaus

flow/designs/gt2n/jpeg/config.mk

@@ -0,0 +1,16 @@
+export DESIGN_NICKNAME = jpeg
+export DESIGN_NAME     = jpeg_encoder
+export PLATFORM        = gt2n
+
+export VERILOG_FILES        = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
+export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
+export SDC_FILE             = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export ABC_AREA = 1
+
+# Floorplan: jpeg_encoder is larger than aes; start conservative.
+export CORE_UTILIZATION       = 40
+export CORE_ASPECT_RATIO      = 1
+export CORE_MARGIN            = 2
+export PLACE_DENSITY_LB_ADDON = 0.20
+export TNS_END_PERCENT        = 100

flow/designs/gt2n/jpeg/constraint.sdc

@@ -0,0 +1,16 @@
+current_design jpeg_encoder
+
+set clk_name clk
+set clk_port_name clk
+# GT2N lib uses time_unit = 1 ps. 1500 ps -> 667 MHz. Loose first-pass
+# target with the analytical-RC stand-in -- tighten once the optimize-ppa
+# loop has the baseline period_min.
+set clk_period 1000
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]