flow: Tune secure exploration sizing configs

Lower core utilization for selected GF12 and IHP-SG13G2 secure exploration designs to provide additional placement and repair headroom.

Remove the temporary CTS comment now that the global sizing repair_timing phase sequence is the branch behavior.

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Author: jhkim-pii

flow/designs/gf12/ibex/config.mk

@@ -12,7 +12,7 @@ export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
-export CORE_UTILIZATION = 40 
+export CORE_UTILIZATION = 32
 export CORE_ASPECT_RATIO = 1
 export CORE_MARGIN = 2
 

flow/designs/gf12/jpeg/config.mk

@@ -8,7 +8,7 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
 export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 export ABC_AREA = 1
 
-export CORE_UTILIZATION = 45
+export CORE_UTILIZATION = 36
 export CORE_ASPECT_RATIO = 1
 export CORE_MARGIN = 2
 

flow/designs/ihp-sg13g2/ibex/config.mk

@@ -15,7 +15,7 @@ export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
 # Adders degrade ibex setup repair
 export ADDER_MAP_FILE :=
 
-export CORE_UTILIZATION = 70
+export CORE_UTILIZATION = 55
 export PLACE_DENSITY_LB_ADDON = 0.2
 export TNS_END_PERCENT = 100
 export CTS_BUF_DISTANCE = 60

flow/scripts/cts.tcl

@@ -66,7 +66,6 @@ if { !$::env(SKIP_CTS_REPAIR_TIMING) } {
     write_lec_verilog 4_before_rsz_lec.v
   }
 
-  # Run LR global sizing before the legacy setup-repair phases (PR 10599 experiment)
   repair_timing_helper -phases "GLOBAL_SIZING LEGACY LAST_GASP CRIT_VT_SWAP"
 
   if { $lec_enabled } {