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jhkim-piijhkim-pii
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flow: Tune IO clock latency estimates
Set real and virtual IO clock latency estimates from propagated CTS clock latency reported in CI artifacts. Use the representative average of source and target clock latency from 4_cts_final reports so IO virtual clocks track observed post-CTS insertion delay more closely. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
1 parent a6e23b0 commit 5511fcc

60 files changed

Lines changed: 284 additions & 131 deletions

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‎flow/designs/asap7/aes/constraint.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ set clk_port [get_ports $clk_port_name]
88
create_clock -name $clk_name -period $clk_period $clk_port
99
set clk_io_name vclk_$clk_name
1010
create_clock -name $clk_io_name -period $clk_period
11-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_name]
12-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_io_name]
11+
set_clock_latency 77.930 [get_clocks $clk_name]
12+
set_clock_latency 77.930 [get_clocks $clk_io_name]
1313

1414
set non_clock_inputs [all_inputs -no_clocks]
1515

‎flow/designs/asap7/ethmac/constraint.sdc‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@ set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
66
set top_io_clk_name vclk_$top_clk_name
77
create_clock -name $top_io_clk_name -period $clk_period
8-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $top_clk_name]
9-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $top_io_clk_name]
8+
set_clock_latency 229.195 [get_clocks $top_clk_name]
9+
set_clock_latency 229.195 [get_clocks $top_io_clk_name]
1010
set non_clock_inputs [all_inputs -no_clocks]
1111
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name $non_clock_inputs
1212
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name [all_outputs]
@@ -17,8 +17,8 @@ set tx_clk_period 300
1717
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
1818
set tx_io_clk_name vclk_$tx_clk_name
1919
create_clock -name $tx_io_clk_name -period $tx_clk_period
20-
set_clock_latency [expr $tx_clk_period * $clk_io_pct * 0.5] [get_clocks $tx_clk_name]
21-
set_clock_latency [expr $tx_clk_period * $clk_io_pct * 0.5] [get_clocks $tx_io_clk_name]
20+
set_clock_latency 55.660 [get_clocks $tx_clk_name]
21+
set_clock_latency 55.660 [get_clocks $tx_io_clk_name]
2222
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
2323
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name $mtx_non_clock_inputs
2424
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name [all_outputs]
@@ -29,8 +29,8 @@ set rx_clk_period 300
2929
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
3030
set rx_io_clk_name vclk_$rx_clk_name
3131
create_clock -name $rx_io_clk_name -period $rx_clk_period
32-
set_clock_latency [expr $rx_clk_period * $clk_io_pct * 0.5] [get_clocks $rx_clk_name]
33-
set_clock_latency [expr $rx_clk_period * $clk_io_pct * 0.5] [get_clocks $rx_io_clk_name]
32+
set_clock_latency 76.515 [get_clocks $rx_clk_name]
33+
set_clock_latency 76.515 [get_clocks $rx_io_clk_name]
3434
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
3535
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name $mrx_non_clock_inputs
3636
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name [all_outputs]

‎flow/designs/asap7/ethmac_lvt/constraint.sdc‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@ set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
66
set top_io_clk_name vclk_$top_clk_name
77
create_clock -name $top_io_clk_name -period $clk_period
8-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $top_clk_name]
9-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $top_io_clk_name]
8+
set_clock_latency 205.790 [get_clocks $top_clk_name]
9+
set_clock_latency 205.790 [get_clocks $top_io_clk_name]
1010
set non_clock_inputs [all_inputs -no_clocks]
1111
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name $non_clock_inputs
1212
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name [all_outputs]
@@ -17,8 +17,8 @@ set tx_clk_period 300
1717
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
1818
set tx_io_clk_name vclk_$tx_clk_name
1919
create_clock -name $tx_io_clk_name -period $tx_clk_period
20-
set_clock_latency [expr $tx_clk_period * $clk_io_pct * 0.5] [get_clocks $tx_clk_name]
21-
set_clock_latency [expr $tx_clk_period * $clk_io_pct * 0.5] [get_clocks $tx_io_clk_name]
20+
set_clock_latency 68.165 [get_clocks $tx_clk_name]
21+
set_clock_latency 68.165 [get_clocks $tx_io_clk_name]
2222
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
2323
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name $mtx_non_clock_inputs
2424
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name [all_outputs]
@@ -29,8 +29,8 @@ set rx_clk_period 300
2929
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
3030
set rx_io_clk_name vclk_$rx_clk_name
3131
create_clock -name $rx_io_clk_name -period $rx_clk_period
32-
set_clock_latency [expr $rx_clk_period * $clk_io_pct * 0.5] [get_clocks $rx_clk_name]
33-
set_clock_latency [expr $rx_clk_period * $clk_io_pct * 0.5] [get_clocks $rx_io_clk_name]
32+
set_clock_latency 85.660 [get_clocks $rx_clk_name]
33+
set_clock_latency 85.660 [get_clocks $rx_io_clk_name]
3434
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
3535
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name $mrx_non_clock_inputs
3636
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name [all_outputs]

‎flow/designs/asap7/gcd/constraint.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@ set clk_port [get_ports $clk_port_name]
1010
create_clock -name $clk_name -period $clk_period $clk_port
1111
set clk_io_name vclk_$clk_name
1212
create_clock -name $clk_io_name -period $clk_period
13-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_name]
14-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_io_name]
13+
set_clock_latency 36.225 [get_clocks $clk_name]
14+
set_clock_latency 36.225 [get_clocks $clk_io_name]
1515

1616
set non_clock_inputs [all_inputs -no_clocks]
1717

‎flow/designs/asap7/ibex/constraint.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ set clk_port [get_ports $clk_port_name]
88
create_clock -name $clk_name -period $clk_period $clk_port
99
set clk_io_name vclk_$clk_name
1010
create_clock -name $clk_io_name -period $clk_period
11-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_name]
12-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_io_name]
11+
set_clock_latency 161.775 [get_clocks $clk_name]
12+
set_clock_latency 161.775 [get_clocks $clk_io_name]
1313

1414
set non_clock_inputs [all_inputs -no_clocks]
1515

‎flow/designs/asap7/ibex/constraint_pos_slack.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ set clk_port [get_ports $clk_port_name]
88
create_clock -name $clk_name -period $clk_period $clk_port
99
set clk_io_name vclk_$clk_name
1010
create_clock -name $clk_io_name -period $clk_period
11-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_name]
12-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_io_name]
11+
set_clock_latency 161.775 [get_clocks $clk_name]
12+
set_clock_latency 161.775 [get_clocks $clk_io_name]
1313

1414
set non_clock_inputs [all_inputs -no_clocks]
1515

‎flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ current_design jpeg_encoder
88

99
create_clock -name "tclk" -period 1000.0 -waveform {0.0 500.0} [get_ports clk]
1010
create_clock -name vclk -period 1000.0
11-
set_clock_latency 50.0 [get_clocks {tclk}]
12-
set_clock_latency 50.0 [get_clocks {vclk}]
11+
set_clock_latency 204.110 [get_clocks {tclk}]
12+
set_clock_latency 204.110 [get_clocks {vclk}]
1313
set_propagated_clock [get_clocks tclk]
1414
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[5]}]
1515
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[4]}]

‎flow/designs/asap7/jpeg_lvt/jpeg_postCTS_14nm.sdc‎

Lines changed: 0 additions & 1 deletion
This file was deleted.

‎flow/designs/asap7/jpeg_lvt/jpeg_postCTS_14nm.sdc‎

Lines changed: 154 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,154 @@
1+
set sdc_version 2.0
2+
3+
set_units -capacitance 1.0fF
4+
set_units -time 1.0ps
5+
6+
# Set the current design
7+
current_design jpeg_encoder
8+
9+
create_clock -name "tclk" -period 1000.0 -waveform {0.0 500.0} [get_ports clk]
10+
create_clock -name vclk -period 1000.0
11+
set_clock_latency 176.470 [get_clocks {tclk}]
12+
set_clock_latency 176.470 [get_clocks {vclk}]
13+
set_propagated_clock [get_clocks tclk]
14+
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[5]}]
15+
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[4]}]
16+
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[3]}]
17+
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[2]}]
18+
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[1]}]
19+
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[0]}]
20+
set_load -pin_load -max 3.0 [get_ports {size[3]}]
21+
set_load -pin_load -max 3.0 [get_ports {size[2]}]
22+
set_load -pin_load -max 3.0 [get_ports {size[1]}]
23+
set_load -pin_load -max 3.0 [get_ports {size[0]}]
24+
set_load -pin_load -max 3.0 [get_ports {rlen[3]}]
25+
set_load -pin_load -max 3.0 [get_ports {rlen[2]}]
26+
set_load -pin_load -max 3.0 [get_ports {rlen[1]}]
27+
set_load -pin_load -max 3.0 [get_ports {rlen[0]}]
28+
set_load -pin_load -max 3.0 [get_ports {amp[11]}]
29+
set_load -pin_load -max 3.0 [get_ports {amp[10]}]
30+
set_load -pin_load -max 3.0 [get_ports {amp[9]}]
31+
set_load -pin_load -max 3.0 [get_ports {amp[8]}]
32+
set_load -pin_load -max 3.0 [get_ports {amp[7]}]
33+
set_load -pin_load -max 3.0 [get_ports {amp[6]}]
34+
set_load -pin_load -max 3.0 [get_ports {amp[5]}]
35+
set_load -pin_load -max 3.0 [get_ports {amp[4]}]
36+
set_load -pin_load -max 3.0 [get_ports {amp[3]}]
37+
set_load -pin_load -max 3.0 [get_ports {amp[2]}]
38+
set_load -pin_load -max 3.0 [get_ports {amp[1]}]
39+
set_load -pin_load -max 3.0 [get_ports {amp[0]}]
40+
set_load -pin_load -max 3.0 [get_ports douten]
41+
set_max_delay 500 -from [list \
42+
[get_clocks tclk]] -to [list \
43+
[get_ports douten] \
44+
[get_ports {amp[0]}] \
45+
[get_ports {amp[1]}] \
46+
[get_ports {amp[2]}] \
47+
[get_ports {amp[3]}] \
48+
[get_ports {amp[4]}] \
49+
[get_ports {amp[5]}] \
50+
[get_ports {amp[6]}] \
51+
[get_ports {amp[7]}] \
52+
[get_ports {amp[8]}] \
53+
[get_ports {amp[9]}] \
54+
[get_ports {amp[10]}] \
55+
[get_ports {amp[11]}] \
56+
[get_ports {rlen[0]}] \
57+
[get_ports {rlen[1]}] \
58+
[get_ports {rlen[2]}] \
59+
[get_ports {rlen[3]}] \
60+
[get_ports {size[0]}] \
61+
[get_ports {size[1]}] \
62+
[get_ports {size[2]}] \
63+
[get_ports {size[3]}] \
64+
[get_ports {qnt_cnt[0]}] \
65+
[get_ports {qnt_cnt[1]}] \
66+
[get_ports {qnt_cnt[2]}] \
67+
[get_ports {qnt_cnt[3]}] \
68+
[get_ports {qnt_cnt[4]}] \
69+
[get_ports {qnt_cnt[5]}]]
70+
set_min_delay 500 \
71+
-from [list \
72+
[get_ports ena] \
73+
[get_ports rst]] \
74+
-to [list \
75+
[get_clocks tclk]]
76+
77+
group_path -weight 1.000000 -name cg_enable_group_tclk -through [list \
78+
[get_pins qnr_RC_CG_HIER_INST3/enable] \
79+
[get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
80+
[get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
81+
[get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
82+
[get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
83+
[get_pins qnr_RC_CG_HIER_INST3/enable] \
84+
[get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
85+
[get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
86+
[get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
87+
[get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
88+
[get_pins qnr_RC_CG_HIER_INST3/enable] \
89+
[get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
90+
[get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
91+
[get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
92+
[get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
93+
[get_pins RC_CG_DECLONE_HIER_INST/enable] \
94+
[get_pins qnr_RC_CG_HIER_INST3/enable] \
95+
[get_pins rle_rz1_RC_CG_HIER_INST134/enable] \
96+
[get_pins rle_rz2_RC_CG_HIER_INST136/enable] \
97+
[get_pins rle_rz3_RC_CG_HIER_INST138/enable] \
98+
[get_pins rle_rz4_RC_CG_HIER_INST140/enable] \
99+
[get_pins RC_CG_DECLONE_HIER_INST/enable]]
100+
set_clock_gating_check -setup 0.0
101+
102+
set_input_delay 100 -clock vclk [get_ports ena]
103+
set_input_delay 100 -clock vclk [get_ports rst]
104+
105+
set_input_delay 100 -clock vclk [get_ports {qnt_val[0]}]
106+
set_input_delay 100 -clock vclk [get_ports {qnt_val[1]}]
107+
set_input_delay 100 -clock vclk [get_ports {qnt_val[2]}]
108+
set_input_delay 100 -clock vclk [get_ports {qnt_val[3]}]
109+
set_input_delay 100 -clock vclk [get_ports {qnt_val[4]}]
110+
set_input_delay 100 -clock vclk [get_ports {qnt_val[5]}]
111+
set_input_delay 100 -clock vclk [get_ports {qnt_val[6]}]
112+
set_input_delay 100 -clock vclk [get_ports {qnt_val[7]}]
113+
set_input_delay 100 -clock vclk [get_ports {din[0]}]
114+
set_input_delay 100 -clock vclk [get_ports {din[1]}]
115+
set_input_delay 100 -clock vclk [get_ports {din[2]}]
116+
set_input_delay 100 -clock vclk [get_ports {din[3]}]
117+
set_input_delay 100 -clock vclk [get_ports {din[4]}]
118+
set_input_delay 100 -clock vclk [get_ports {din[5]}]
119+
set_input_delay 100 -clock vclk [get_ports {din[6]}]
120+
set_input_delay 100 -clock vclk [get_ports {din[7]}]
121+
set_input_delay 100 -clock vclk [get_ports dstrb]
122+
set_output_delay 100 -clock vclk [get_ports douten]
123+
set_output_delay 100 -clock vclk [get_ports {amp[0]}]
124+
set_output_delay 100 -clock vclk [get_ports {amp[1]}]
125+
set_output_delay 100 -clock vclk [get_ports {amp[2]}]
126+
set_output_delay 100 -clock vclk [get_ports {amp[3]}]
127+
set_output_delay 100 -clock vclk [get_ports {amp[4]}]
128+
set_output_delay 100 -clock vclk [get_ports {amp[5]}]
129+
set_output_delay 100 -clock vclk [get_ports {amp[6]}]
130+
set_output_delay 100 -clock vclk [get_ports {amp[7]}]
131+
set_output_delay 100 -clock vclk [get_ports {amp[8]}]
132+
set_output_delay 100 -clock vclk [get_ports {amp[9]}]
133+
set_output_delay 100 -clock vclk [get_ports {amp[10]}]
134+
set_output_delay 100 -clock vclk [get_ports {amp[11]}]
135+
set_output_delay 100 -clock vclk [get_ports {rlen[0]}]
136+
set_output_delay 100 -clock vclk [get_ports {rlen[1]}]
137+
set_output_delay 100 -clock vclk [get_ports {rlen[2]}]
138+
set_output_delay 100 -clock vclk [get_ports {rlen[3]}]
139+
set_output_delay 100 -clock vclk [get_ports {size[0]}]
140+
set_output_delay 100 -clock vclk [get_ports {size[1]}]
141+
set_output_delay 100 -clock vclk [get_ports {size[2]}]
142+
set_output_delay 100 -clock vclk [get_ports {size[3]}]
143+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[0]}]
144+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[1]}]
145+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[2]}]
146+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[3]}]
147+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[4]}]
148+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[5]}]
149+
set_max_fanout 40.000 [current_design]
150+
set_max_transition 80.0 [current_design]
151+
set_clock_uncertainty -setup 20.0 [get_clocks tclk]
152+
set_clock_uncertainty -hold 20.0 [get_clocks tclk]
153+
154+
set_false_path -from [get_ports {ena rst}] -to [get_clocks tclk]

‎flow/designs/asap7/riscv32i/constraint.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@ set clk_port [get_ports $clk_port_name]
1010
create_clock -name $clk_name -period $clk_period $clk_port
1111
set clk_io_name vclk_$clk_name
1212
create_clock -name $clk_io_name -period $clk_period
13-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_name]
14-
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_io_name]
13+
set_clock_latency 142.965 [get_clocks $clk_name]
14+
set_clock_latency 142.965 [get_clocks $clk_io_name]
1515

1616
set non_clock_inputs [all_inputs -no_clocks]
1717
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs

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