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gt2n: apply black and tclfmt formatting
Satisfy the lint (psf/black) and Tclint CI checks: - black-format flow/platforms/gt2n/itf_to_rc.py - tclfmt flow/platforms/gt2n/setRC.tcl and flow/designs/gt2n/jpeg/constraint.sdc Signed-off-by: mrg <mrg@ucsc.edu>
1 parent 1a8812a commit 5f6e867

3 files changed

Lines changed: 109 additions & 72 deletions

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flow/designs/gt2n/jpeg/constraint.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,5 +12,5 @@ set clk_port [get_ports $clk_port_name]
1212
create_clock -name $clk_name -period $clk_period $clk_port
1313

1414
set non_clock_inputs [all_inputs -no_clocks]
15-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
15+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
1616
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/platforms/gt2n/itf_to_rc.py

Lines changed: 68 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -11,66 +11,103 @@
1111
Cb = eps0 * eps_below * W / d_below parallel-plate to layer below
1212
Cc = eps0 * eps_side * T / SMIN between sidewalls of min-spaced neighbors
1313
"""
14+
1415
import re
1516

1617
EPS0 = 8.854e-3
1718
FRINGE_FACTOR = 1.5
1819
PF_PER_FF = 1.0e-3
1920

20-
ROUTING = {'M0','M1','M2','M3','M4','M5','M6','M7','M8','M9','M10','M11','M12','M13',
21-
'RDL','BPR','BM1','BM2','BM3','BM4','BRDL'}
21+
ROUTING = {
22+
"M0",
23+
"M1",
24+
"M2",
25+
"M3",
26+
"M4",
27+
"M5",
28+
"M6",
29+
"M7",
30+
"M8",
31+
"M9",
32+
"M10",
33+
"M11",
34+
"M12",
35+
"M13",
36+
"RDL",
37+
"BPR",
38+
"BM1",
39+
"BM2",
40+
"BM3",
41+
"BM4",
42+
"BRDL",
43+
}
2244

2345
# dielectrics to ignore when looking up neighbors (file-end placeholder)
24-
IGNORE_DIELS = {'dummy_diel'}
46+
IGNORE_DIELS = {"dummy_diel"}
47+
2548

2649
def parse_itf(path):
27-
text = re.sub(r'\$[^\n]*\n', '\n', open(path).read())
50+
text = re.sub(r"\$[^\n]*\n", "\n", open(path).read())
2851
entries = []
29-
for m in re.finditer(r'(DIELECTRIC|CONDUCTOR|VIA)\s+(\w+)\s*\{([^}]*)\}', text):
52+
for m in re.finditer(r"(DIELECTRIC|CONDUCTOR|VIA)\s+(\w+)\s*\{([^}]*)\}", text):
3053
kind, name, body = m.group(1), m.group(2), m.group(3)
31-
params = {k: float(v) for k, v in re.findall(r'(\w+)\s*=\s*([\d.]+)', body)}
54+
params = {k: float(v) for k, v in re.findall(r"(\w+)\s*=\s*([\d.]+)", body)}
3255
# also accept upper/lower text fields like FROM/TO for VIA
33-
for k, v in re.findall(r'(\w+)\s*=\s*([A-Za-z]\w*)', body):
56+
for k, v in re.findall(r"(\w+)\s*=\s*([A-Za-z]\w*)", body):
3457
params.setdefault(k, v)
3558
entries.append((kind, name, params))
3659
return entries
3760

61+
3862
def metal_rc(entries, idx):
3963
cond = entries[idx][2]
4064
# dielectric above (closest, ignoring placeholders)
4165
above = None
42-
for j in range(idx-1, -1, -1):
43-
if entries[j][0]=='DIELECTRIC' and entries[j][1] not in IGNORE_DIELS:
44-
above = entries[j][2]; break
66+
for j in range(idx - 1, -1, -1):
67+
if entries[j][0] == "DIELECTRIC" and entries[j][1] not in IGNORE_DIELS:
68+
above = entries[j][2]
69+
break
4570
# dielectric below (closest, stop at next conductor)
4671
below = None
47-
for j in range(idx+1, len(entries)):
48-
if entries[j][0]=='CONDUCTOR': break
49-
if entries[j][0]=='DIELECTRIC' and entries[j][1] not in IGNORE_DIELS:
50-
below = entries[j][2]; break
51-
W, S, T = cond['WMIN'], cond['SMIN'], cond['THICKNESS']
52-
R = cond['RPSQ'] / W
53-
def pp(d): return EPS0 * d['ER'] * W / d['THICKNESS'] if d else 0.0
72+
for j in range(idx + 1, len(entries)):
73+
if entries[j][0] == "CONDUCTOR":
74+
break
75+
if entries[j][0] == "DIELECTRIC" and entries[j][1] not in IGNORE_DIELS:
76+
below = entries[j][2]
77+
break
78+
W, S, T = cond["WMIN"], cond["SMIN"], cond["THICKNESS"]
79+
R = cond["RPSQ"] / W
80+
81+
def pp(d):
82+
return EPS0 * d["ER"] * W / d["THICKNESS"] if d else 0.0
83+
5484
Ca, Cb = pp(above), pp(below)
55-
eps_side = (above or below)['ER'] if (above or below) else 1.0
85+
eps_side = (above or below)["ER"] if (above or below) else 1.0
5686
Cc = EPS0 * eps_side * T / S
57-
C_fF = (Ca + Cb)*FRINGE_FACTOR + 2*Cc
87+
C_fF = (Ca + Cb) * FRINGE_FACTOR + 2 * Cc
5888
return R, C_fF * PF_PER_FF
5989

60-
if __name__ == '__main__':
61-
entries = parse_itf('/home/mrg/orfs/GT2N/nxtgrd/GT2.itf')
62-
print('# Per-length metal R and C, derived analytically from GT2.itf.')
63-
print('# R/um = RPSQ / WMIN (matches Fig 1(b) of the GT2N paper).')
64-
print('# C/um = parallel-plate-to-neighbor + sidewall-coupling, fringe-scaled 1.5x.')
65-
print('# pulling_resistance_unit=1ohm -> ohm/um ; capacitive_load_unit(1, pf) -> pf/um.')
90+
91+
if __name__ == "__main__":
92+
entries = parse_itf("/home/mrg/orfs/GT2N/nxtgrd/GT2.itf")
93+
print("# Per-length metal R and C, derived analytically from GT2.itf.")
94+
print("# R/um = RPSQ / WMIN (matches Fig 1(b) of the GT2N paper).")
95+
print(
96+
"# C/um = parallel-plate-to-neighbor + sidewall-coupling, fringe-scaled 1.5x."
97+
)
98+
print(
99+
"# pulling_resistance_unit=1ohm -> ohm/um ; capacitive_load_unit(1, pf) -> pf/um."
100+
)
66101
print()
67-
for i,(kind,name,_) in enumerate(entries):
68-
if kind=='CONDUCTOR' and name in ROUTING:
102+
for i, (kind, name, _) in enumerate(entries):
103+
if kind == "CONDUCTOR" and name in ROUTING:
69104
R, C = metal_rc(entries, i)
70-
print(f'set_layer_rc -layer {name:<5} -resistance {R:8.3f} -capacitance {C:.3e}')
105+
print(
106+
f"set_layer_rc -layer {name:<5} -resistance {R:8.3f} -capacitance {C:.3e}"
107+
)
71108
print()
72-
print('# Via resistance (single via). Derived from ITF VIA RPV values.')
109+
print("# Via resistance (single via). Derived from ITF VIA RPV values.")
73110
print()
74-
for kind,name,p in entries:
75-
if kind=='VIA' and name.startswith(('V','BV')) and 'RPV' in p:
111+
for kind, name, p in entries:
112+
if kind == "VIA" and name.startswith(("V", "BV")) and "RPV" in p:
76113
print(f'set_layer_rc -via {name:<4} -resistance {p["RPV"]:.3f}')

flow/platforms/gt2n/setRC.tcl

Lines changed: 40 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -26,52 +26,52 @@
2626
# Via R is per via.
2727

2828
# Frontside routing
29-
set_layer_rc -layer M0 -resistance 621.75 -capacitance 1.200e-04
30-
set_layer_rc -layer M1 -resistance 437.50 -capacitance 1.023e-04
31-
set_layer_rc -layer M2 -resistance 621.75 -capacitance 9.980e-05
32-
set_layer_rc -layer M3 -resistance 437.50 -capacitance 1.023e-04
33-
set_layer_rc -layer M4 -resistance 166.95 -capacitance 1.088e-04
34-
set_layer_rc -layer M5 -resistance 166.95 -capacitance 1.051e-04
35-
set_layer_rc -layer M6 -resistance 26.55 -capacitance 1.119e-04
36-
set_layer_rc -layer M7 -resistance 26.55 -capacitance 1.051e-04
37-
set_layer_rc -layer M8 -resistance 26.55 -capacitance 1.051e-04
38-
set_layer_rc -layer M9 -resistance 26.55 -capacitance 1.051e-04
39-
set_layer_rc -layer M10 -resistance 7.48 -capacitance 1.091e-04
40-
set_layer_rc -layer M11 -resistance 7.48 -capacitance 1.051e-04
41-
set_layer_rc -layer M12 -resistance 0.64 -capacitance 1.205e-04
42-
set_layer_rc -layer M13 -resistance 0.64 -capacitance 1.205e-04
43-
set_layer_rc -layer RDL -resistance 0.01 -capacitance 3.572e-04
29+
set_layer_rc -layer M0 -resistance 621.75 -capacitance 1.200e-04
30+
set_layer_rc -layer M1 -resistance 437.50 -capacitance 1.023e-04
31+
set_layer_rc -layer M2 -resistance 621.75 -capacitance 9.980e-05
32+
set_layer_rc -layer M3 -resistance 437.50 -capacitance 1.023e-04
33+
set_layer_rc -layer M4 -resistance 166.95 -capacitance 1.088e-04
34+
set_layer_rc -layer M5 -resistance 166.95 -capacitance 1.051e-04
35+
set_layer_rc -layer M6 -resistance 26.55 -capacitance 1.119e-04
36+
set_layer_rc -layer M7 -resistance 26.55 -capacitance 1.051e-04
37+
set_layer_rc -layer M8 -resistance 26.55 -capacitance 1.051e-04
38+
set_layer_rc -layer M9 -resistance 26.55 -capacitance 1.051e-04
39+
set_layer_rc -layer M10 -resistance 7.48 -capacitance 1.091e-04
40+
set_layer_rc -layer M11 -resistance 7.48 -capacitance 1.051e-04
41+
set_layer_rc -layer M12 -resistance 0.64 -capacitance 1.205e-04
42+
set_layer_rc -layer M13 -resistance 0.64 -capacitance 1.205e-04
43+
set_layer_rc -layer RDL -resistance 0.01 -capacitance 3.572e-04
4444

4545
# Backside routing
46-
set_layer_rc -layer BPR -resistance 24.31 -capacitance 7.793e-05
47-
set_layer_rc -layer BM1 -resistance 7.48 -capacitance 1.535e-04
48-
set_layer_rc -layer BM2 -resistance 7.48 -capacitance 1.051e-04
49-
set_layer_rc -layer BM3 -resistance 0.64 -capacitance 1.205e-04
50-
set_layer_rc -layer BM4 -resistance 0.64 -capacitance 8.666e-05
51-
set_layer_rc -layer BRDL -resistance 0.01 -capacitance 1.006e-04
46+
set_layer_rc -layer BPR -resistance 24.31 -capacitance 7.793e-05
47+
set_layer_rc -layer BM1 -resistance 7.48 -capacitance 1.535e-04
48+
set_layer_rc -layer BM2 -resistance 7.48 -capacitance 1.051e-04
49+
set_layer_rc -layer BM3 -resistance 0.64 -capacitance 1.205e-04
50+
set_layer_rc -layer BM4 -resistance 0.64 -capacitance 8.666e-05
51+
set_layer_rc -layer BRDL -resistance 0.01 -capacitance 1.006e-04
5252

5353
# Frontside via R (per via, derived from ITF RPV)
54-
set_layer_rc -via V0 -resistance 54.99
55-
set_layer_rc -via V1 -resistance 54.99
56-
set_layer_rc -via V2 -resistance 54.99
57-
set_layer_rc -via V3 -resistance 45.78
58-
set_layer_rc -via V4 -resistance 27.80
59-
set_layer_rc -via V5 -resistance 14.89
60-
set_layer_rc -via V6 -resistance 13.26
61-
set_layer_rc -via V7 -resistance 13.26
62-
set_layer_rc -via V8 -resistance 13.26
63-
set_layer_rc -via V9 -resistance 7.65
64-
set_layer_rc -via V10 -resistance 6.08
65-
set_layer_rc -via V11 -resistance 6.08
66-
set_layer_rc -via V12 -resistance 0.95
67-
set_layer_rc -via V13 -resistance 0.15
54+
set_layer_rc -via V0 -resistance 54.99
55+
set_layer_rc -via V1 -resistance 54.99
56+
set_layer_rc -via V2 -resistance 54.99
57+
set_layer_rc -via V3 -resistance 45.78
58+
set_layer_rc -via V4 -resistance 27.80
59+
set_layer_rc -via V5 -resistance 14.89
60+
set_layer_rc -via V6 -resistance 13.26
61+
set_layer_rc -via V7 -resistance 13.26
62+
set_layer_rc -via V8 -resistance 13.26
63+
set_layer_rc -via V9 -resistance 7.65
64+
set_layer_rc -via V10 -resistance 6.08
65+
set_layer_rc -via V11 -resistance 6.08
66+
set_layer_rc -via V12 -resistance 0.95
67+
set_layer_rc -via V13 -resistance 0.15
6868

6969
# Backside via R (per via, derived from ITF RPV)
70-
set_layer_rc -via BV0 -resistance 25.10
71-
set_layer_rc -via BV1 -resistance 6.08
72-
set_layer_rc -via BV2 -resistance 6.08
73-
set_layer_rc -via BV3 -resistance 0.95
74-
set_layer_rc -via BV4 -resistance 0.15
70+
set_layer_rc -via BV0 -resistance 25.10
71+
set_layer_rc -via BV1 -resistance 6.08
72+
set_layer_rc -via BV2 -resistance 6.08
73+
set_layer_rc -via BV3 -resistance 0.95
74+
set_layer_rc -via BV4 -resistance 0.15
7575

7676
set_wire_rc -signal -layer M3
7777
set_wire_rc -clock -layer M5

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