@@ -33,20 +33,19 @@ export CORE_UTILIZATION = 70
3333export CORE_ASPECT_RATIO = 1.3
3434export CORE_MARGIN = 2
3535
36- export chameleon_DIR = $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NICKNAME )
37- export LEC_AUX_VERILOG_FILES = $(chameleon_DIR ) /lec_blackbox_stubs.v
36+ export LEC_AUX_VERILOG_FILES = $(DESIGN_DIR ) /lec_blackbox_stubs.v
3837
39- export ADDITIONAL_GDS = $(chameleon_DIR ) /gds/apb_sys_0.gds.gz \
40- $(chameleon_DIR ) /gds/DMC_32x16HC.gds.gz \
41- $(chameleon_DIR ) /gds/DFFRAM_4K.gds.gz \
42- $(chameleon_DIR ) /gds/ibex_wrapper.gds.gz
38+ export ADDITIONAL_GDS = $(DESIGN_DIR ) /gds/apb_sys_0.gds.gz \
39+ $(DESIGN_DIR ) /gds/DMC_32x16HC.gds.gz \
40+ $(DESIGN_DIR ) /gds/DFFRAM_4K.gds.gz \
41+ $(DESIGN_DIR ) /gds/ibex_wrapper.gds.gz
4342
44- export ADDITIONAL_LEFS = $(chameleon_DIR ) /lef/apb_sys_0.lef \
45- $(chameleon_DIR ) /lef/DFFRAM_4K.lef \
46- $(chameleon_DIR ) /lef/DMC_32x16HC.lef \
47- $(chameleon_DIR ) /lef/ibex_wrapper.lef
43+ export ADDITIONAL_LEFS = $(DESIGN_DIR ) /lef/apb_sys_0.lef \
44+ $(DESIGN_DIR ) /lef/DFFRAM_4K.lef \
45+ $(DESIGN_DIR ) /lef/DMC_32x16HC.lef \
46+ $(DESIGN_DIR ) /lef/ibex_wrapper.lef
4847
49- # export MACRO_PLACEMENT_TCL = $(chameleon_DIR )/macro_placement.tcl
48+ # export MACRO_PLACEMENT_TCL = $(DESIGN_DIR )/macro_placement.tcl
5049
5150export FP_PDN_RAIL_WIDTH = 0.48
5251export FP_PDN_RAIL_OFFSET = 0
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