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jhkim-piijhkim-pii
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flow: Use virtual clocks for IO delays
Create virtual IO reference clocks for SDC input and output delay constraints so post-CTS propagated real clocks do not become the external timing reference. Propagate only the real design clocks in post-CTS SDCs while preserving virtual clock latency for IO timing. Update the OpenROAD submodule pointer to include the CTS virtual clock latency fix used by these constraints. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
1 parent 00913f3 commit 732bf73

121 files changed

Lines changed: 16478 additions & 16219 deletions

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‎flow/designs/asap7/aes-mbff/rules-base.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
"compare": "<="
1515
},
1616
"constraints__clocks__count": {
17-
"value": 1,
17+
"value": 2,
1818
"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {
@@ -109,4 +109,4 @@
109109
"value": 1947,
110110
"compare": "<="
111111
}
112-
}
112+
}

‎flow/designs/asap7/aes/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,12 @@ set clk_io_pct 0.2
66
set clk_port [get_ports $clk_port_name]
77

88
create_clock -name $clk_name -period $clk_period $clk_port
9+
set clk_io_name vclk_$clk_name
10+
create_clock -name $clk_io_name -period $clk_period
11+
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_name]
12+
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_io_name]
913

1014
set non_clock_inputs [all_inputs -no_clocks]
1115

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
16+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
17+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/asap7/aes/rules-base.json‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
"compare": "<="
1515
},
1616
"constraints__clocks__count": {
17-
"value": 1,
17+
"value": 2,
1818
"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {

‎flow/designs/asap7/ethmac/constraint.sdc‎

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,29 +3,41 @@ set clk_period 1000
33
set clk_io_pct 0.2
44
set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
6+
set top_io_clk_name vclk_$top_clk_name
7+
create_clock -name $top_io_clk_name -period $clk_period
8+
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $top_clk_name]
9+
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $top_io_clk_name]
610
set non_clock_inputs [all_inputs -no_clocks]
7-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
8-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
11+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name $non_clock_inputs
12+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name [all_outputs]
913

1014
set tx_clk_name mtx_clk_pad_i
1115
set tx_clk_port [get_ports $tx_clk_name]
1216
set tx_clk_period 300
1317
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
18+
set tx_io_clk_name vclk_$tx_clk_name
19+
create_clock -name $tx_io_clk_name -period $tx_clk_period
20+
set_clock_latency [expr $tx_clk_period * $clk_io_pct * 0.5] [get_clocks $tx_clk_name]
21+
set_clock_latency [expr $tx_clk_period * $clk_io_pct * 0.5] [get_clocks $tx_io_clk_name]
1422
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
15-
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
16-
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
23+
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name $mtx_non_clock_inputs
24+
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name [all_outputs]
1725

1826
set rx_clk_name mrx_clk_pad_i
1927
set rx_clk_port [get_ports $rx_clk_name]
2028
set rx_clk_period 300
2129
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
30+
set rx_io_clk_name vclk_$rx_clk_name
31+
create_clock -name $rx_io_clk_name -period $rx_clk_period
32+
set_clock_latency [expr $rx_clk_period * $clk_io_pct * 0.5] [get_clocks $rx_clk_name]
33+
set_clock_latency [expr $rx_clk_period * $clk_io_pct * 0.5] [get_clocks $rx_io_clk_name]
2234
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
23-
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
24-
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
35+
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name $mrx_non_clock_inputs
36+
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name [all_outputs]
2537

2638
set_clock_groups -name core_clock -logically_exclusive \
27-
-group [get_clocks $top_clk_name] \
28-
-group [get_clocks $tx_clk_name] \
29-
-group [get_clocks $rx_clk_name]
39+
-group [concat [get_clocks $top_clk_name] [get_clocks $top_io_clk_name]] \
40+
-group [concat [get_clocks $tx_clk_name] [get_clocks $tx_io_clk_name]] \
41+
-group [concat [get_clocks $rx_clk_name] [get_clocks $rx_io_clk_name]]
3042

3143
set_max_fanout 10 [current_design]

‎flow/designs/asap7/ethmac/rules-base.json‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
"compare": "<="
1515
},
1616
"constraints__clocks__count": {
17-
"value": 3,
17+
"value": 6,
1818
"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {

‎flow/designs/asap7/ethmac_lvt/constraint.sdc‎

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,27 +3,39 @@ set clk_period 1000
33
set clk_io_pct 0.2
44
set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
6+
set top_io_clk_name vclk_$top_clk_name
7+
create_clock -name $top_io_clk_name -period $clk_period
8+
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $top_clk_name]
9+
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $top_io_clk_name]
610
set non_clock_inputs [all_inputs -no_clocks]
7-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
8-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
11+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name $non_clock_inputs
12+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name [all_outputs]
913

1014
set tx_clk_name mtx_clk_pad_i
1115
set tx_clk_port [get_ports $tx_clk_name]
1216
set tx_clk_period 300
1317
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
18+
set tx_io_clk_name vclk_$tx_clk_name
19+
create_clock -name $tx_io_clk_name -period $tx_clk_period
20+
set_clock_latency [expr $tx_clk_period * $clk_io_pct * 0.5] [get_clocks $tx_clk_name]
21+
set_clock_latency [expr $tx_clk_period * $clk_io_pct * 0.5] [get_clocks $tx_io_clk_name]
1422
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
15-
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
16-
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
23+
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name $mtx_non_clock_inputs
24+
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name [all_outputs]
1725

1826
set rx_clk_name mrx_clk_pad_i
1927
set rx_clk_port [get_ports $rx_clk_name]
2028
set rx_clk_period 300
2129
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
30+
set rx_io_clk_name vclk_$rx_clk_name
31+
create_clock -name $rx_io_clk_name -period $rx_clk_period
32+
set_clock_latency [expr $rx_clk_period * $clk_io_pct * 0.5] [get_clocks $rx_clk_name]
33+
set_clock_latency [expr $rx_clk_period * $clk_io_pct * 0.5] [get_clocks $rx_io_clk_name]
2234
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
23-
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
24-
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
35+
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name $mrx_non_clock_inputs
36+
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name [all_outputs]
2537

2638
set_clock_groups -name core_clock -logically_exclusive \
27-
-group [get_clocks $top_clk_name] \
28-
-group [get_clocks $tx_clk_name] \
29-
-group [get_clocks $rx_clk_name]
39+
-group [concat [get_clocks $top_clk_name] [get_clocks $top_io_clk_name]] \
40+
-group [concat [get_clocks $tx_clk_name] [get_clocks $tx_io_clk_name]] \
41+
-group [concat [get_clocks $rx_clk_name] [get_clocks $rx_io_clk_name]]

‎flow/designs/asap7/ethmac_lvt/rules-base.json‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
"compare": "<="
1515
},
1616
"constraints__clocks__count": {
17-
"value": 3,
17+
"value": 6,
1818
"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {
@@ -62,7 +62,7 @@
6262
"compare": ">="
6363
},
6464
"globalroute__timing__setup__tns": {
65-
"value": -260.0,
65+
"value": -310.0,
6666
"compare": ">="
6767
},
6868
"globalroute__timing__hold__ws": {
@@ -109,4 +109,4 @@
109109
"value": 8537,
110110
"compare": "<="
111111
}
112-
}
112+
}

‎flow/designs/asap7/gcd-ccs/rules-base.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
"compare": "<="
1515
},
1616
"constraints__clocks__count": {
17-
"value": 1,
17+
"value": 2,
1818
"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {
@@ -109,4 +109,4 @@
109109
"value": 63,
110110
"compare": "<="
111111
}
112-
}
112+
}

‎flow/designs/asap7/gcd/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,12 @@ set clk_io_pct 0.2
88
set clk_port [get_ports $clk_port_name]
99

1010
create_clock -name $clk_name -period $clk_period $clk_port
11+
set clk_io_name vclk_$clk_name
12+
create_clock -name $clk_io_name -period $clk_period
13+
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_name]
14+
set_clock_latency [expr $clk_period * $clk_io_pct * 0.5] [get_clocks $clk_io_name]
1115

1216
set non_clock_inputs [all_inputs -no_clocks]
1317

14-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
15-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
18+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
19+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/asap7/gcd/rules-base.json‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
"compare": "<="
1515
},
1616
"constraints__clocks__count": {
17-
"value": 1,
17+
"value": 2,
1818
"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {

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