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malibertymaliberty
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Merge pull request #3861 from The-OpenROAD-Project-staging/pdk-0.15-tuning
Updated cva6, ibex, and jpeg for PDK 0.15
2 parents 419cd9b + f475260 commit 7c614f3

11 files changed

Lines changed: 117 additions & 15 deletions

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‎flow/designs/rapidus2hp/cva6/config.mk‎

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@ export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x128m2b1w0c1p0d0
9797
DEFAULT_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
9898
_0P2A_6T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.2a_6T.sdc
9999
_0P2A_8T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.2a_8T.sdc
100+
_0P15_8T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.15_8T.sdc
100101
_0P3_6T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.3_6T.sdc
101102
_0P3_8T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_0.3_8T.sdc
102103

@@ -107,12 +108,18 @@ export SDC_FILE = $(strip \
107108
$(_0P2A_6T_SDC_FILE), \
108109
$(_0P2A_8T_SDC_FILE) \
109110
), \
110-
$(if $(filter 0.3,$(RAPIDUS_PDK_VERSION)), \
111-
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
112-
$(_0P3_6T_SDC_FILE), \
113-
$(_0P3_8T_SDC_FILE) \
111+
$(if $(filter 0.15,$(RAPIDUS_PDK_VERSION)), \
112+
$(if $(filter ra02h184_HST_45CPP,$(PLACE_SITE)), \
113+
$(_0P15_8T_SDC_FILE), \
114+
$(DEFAULT_SDC_FILE) \
114115
), \
115-
$(DEFAULT_SDC_FILE) \
116+
$(if $(filter 0.3,$(RAPIDUS_PDK_VERSION)), \
117+
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
118+
$(_0P3_6T_SDC_FILE), \
119+
$(_0P3_8T_SDC_FILE) \
120+
), \
121+
$(DEFAULT_SDC_FILE) \
122+
) \
116123
) \
117124
))
118125

‎flow/designs/rapidus2hp/cva6/constraint_0.15_8T.sdc‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
# Derived from cva6_synth.tcl and Makefiles
2+
3+
source $::env(PLATFORM_DIR)/util.tcl
4+
5+
set clk_name main_clk
6+
set clk_port clk_i
7+
set clk_ports_list [list $clk_port]
8+
set clk_period 650
9+
10+
convert_time_value clk_period
11+
12+
set input_delay [convert_time_value 0.46]
13+
set output_delay [convert_time_value 0.11]
14+
15+
16+
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

‎flow/designs/rapidus2hp/cva6/test/test_params.py‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,10 @@ def get_exp_sdc(self, place_site, pdk_version):
3434
return os.path.join(
3535
self._design_full_dir, f"constraint_{pdk_version}_8T.sdc"
3636
)
37+
if pdk_version == "0.15" and place_site in ["", "ra02h184_HST_45CPP"]:
38+
return os.path.join(
39+
self._design_full_dir, f"constraint_{pdk_version}_8T.sdc"
40+
)
3741

3842
return os.path.join(self._design_full_dir, "constraint.sdc")
3943

‎flow/designs/rapidus2hp/ibex/config.mk‎

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,11 +50,20 @@ else
5050
))
5151
endif
5252

53-
export CORE_UTILIZATION = $(strip $(if $(filter 0.3,$(RAPIDUS_PDK_VERSION)), \
54-
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
53+
export CORE_UTILIZATION = $(strip \
54+
$(if $(filter 0.15,$(RAPIDUS_PDK_VERSION)), \
55+
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
56+
52, \
57+
65 \
58+
), \
59+
$(if $(filter 0.3,$(RAPIDUS_PDK_VERSION)), \
60+
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
5561
60, \
56-
65), \
57-
70))
62+
65 \
63+
), \
64+
70 \
65+
) \
66+
))
5867

5968
export CORE_ASPECT_RATIO = 1
6069
export CORE_MARGIN = 0.75

‎flow/designs/rapidus2hp/ibex/constraint_0.15.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ source $::env(PLATFORM_DIR)/util.tcl
22

33
set clk_name core_clock
44
set clk_port_name clk_i
5-
set clk_period 550
5+
set clk_period 450
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]

‎flow/designs/rapidus2hp/ibex/test/test_params.py‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,10 @@ def get_exp_util(self, place_site, pdk_version):
2828
if place_site == "ra02h138_DST_45CPP":
2929
return 60
3030
return 65
31+
if pdk_version == "0.15":
32+
if place_site == "ra02h138_DST_45CPP":
33+
return 52
34+
return 65
3135
return 70
3236

3337
def get_exp_sdc(self, place_site, pdk_version):

‎flow/designs/rapidus2hp/jpeg/config.mk‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,15 +12,19 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
1212

1313
DEFAULT_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
1414
_0P2A_8T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_0.2a_8T.sdc
15-
_0P15_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_0.15.sdc
15+
_0P15_6T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_0.15_6T.sdc
16+
_0P15_8T_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_0.15_8T.sdc
1617
_0P3_SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_0.3.sdc
1718

1819
# Use $(if) to defer conditional eval until all makefiles are read
1920
export SDC_FILE = $(strip \
2021
$(if $(and $(filter 0.2a,$(RAPIDUS_PDK_VERSION)),$(filter ra02h184_HST_45CPP,$(PLACE_SITE))), \
2122
$(_0P2A_8T_SDC_FILE), \
2223
$(if $(filter 0.15,$(RAPIDUS_PDK_VERSION)), \
23-
$(_0P15_SDC_FILE), \
24+
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
25+
$(_0P15_6T_SDC_FILE), \
26+
$(_0P15_8T_SDC_FILE) \
27+
), \
2428
$(if $(filter 0.3,$(RAPIDUS_PDK_VERSION)), \
2529
$(_0P3_SDC_FILE), \
2630
$(DEFAULT_SDC_FILE) \

‎flow/designs/rapidus2hp/jpeg/jpeg_encoder15_0.15_6T.sdc‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
source $::env(PLATFORM_DIR)/util.tcl
2+
3+
current_design jpeg_encoder
4+
5+
set clk_name clk
6+
set clk_port_name clk
7+
set clk_period 150
8+
set clk_io_pct 0.2
9+
10+
convert_time_value clk_period
11+
12+
set clk_port [get_ports $clk_port_name]
13+
14+
create_clock -name $clk_name -period $clk_period $clk_port
15+
16+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
17+
18+
set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
19+
$non_clock_inputs
20+
set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
21+
[all_outputs]

‎flow/designs/rapidus2hp/jpeg/jpeg_encoder15_0.15_8T.sdc‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
source $::env(PLATFORM_DIR)/util.tcl
2+
3+
current_design jpeg_encoder
4+
5+
set clk_name clk
6+
set clk_port_name clk
7+
set clk_period 250
8+
set clk_io_pct 0.2
9+
10+
convert_time_value clk_period
11+
12+
set clk_port [get_ports $clk_port_name]
13+
14+
create_clock -name $clk_name -period $clk_period $clk_port
15+
16+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
17+
18+
set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
19+
$non_clock_inputs
20+
set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
21+
[all_outputs]

‎flow/designs/rapidus2hp/jpeg/test/test_params.py‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,15 @@ def get_exp_sdc(self, place_site, pdk_version):
2929
return os.path.join(
3030
self._design_full_dir, f"jpeg_encoder15_{pdk_version}_8T.sdc"
3131
)
32-
if pdk_version in ["", "0.15", "0.3"]:
32+
if pdk_version == "0.15":
33+
if place_site in ["", "ra02h184_HST_45CPP"]:
34+
return os.path.join(
35+
self._design_full_dir, f"jpeg_encoder15_{pdk_version}_8T.sdc"
36+
)
37+
return os.path.join(
38+
self._design_full_dir, f"jpeg_encoder15_{pdk_version}_6T.sdc"
39+
)
40+
if pdk_version in ["", "0.3"]:
3341
if pdk_version == "":
3442
pdk_version = "0.3"
3543
return os.path.join(

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