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nanocohnanocoh
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Merge branch 'The-OpenROAD-Project:master' into signoff-single-commit
2 parents d345f28 + 4810cd9 commit 8b98a3f

13 files changed

Lines changed: 141 additions & 88 deletions

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‎flow/designs/asap7/riscv32i-mock-sram/rules-base.json‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -36,35 +36,35 @@
3636
"compare": ">="
3737
},
3838
"cts__timing__hold__ws": {
39-
"value": -50.0,
39+
"value": -47.5,
4040
"compare": ">="
4141
},
4242
"cts__timing__hold__tns": {
43-
"value": -200.0,
43+
"value": -190.0,
4444
"compare": ">="
4545
},
4646
"globalroute__antenna_diodes_count": {
4747
"value": 100,
4848
"compare": "<="
4949
},
5050
"globalroute__timing__setup__ws": {
51-
"value": -51.5,
51+
"value": -104.0,
5252
"compare": ">="
5353
},
5454
"globalroute__timing__setup__tns": {
55-
"value": -202.0,
55+
"value": -1050.0,
5656
"compare": ">="
5757
},
5858
"globalroute__timing__hold__ws": {
59-
"value": -50.0,
59+
"value": -47.5,
6060
"compare": ">="
6161
},
6262
"globalroute__timing__hold__tns": {
63-
"value": -200.0,
63+
"value": -190.0,
6464
"compare": ">="
6565
},
6666
"detailedroute__route__wirelength": {
67-
"value": 84714,
67+
"value": 73284,
6868
"compare": "<="
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},
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"detailedroute__route__drc_errors": {
@@ -80,19 +80,19 @@
8080
"compare": "<="
8181
},
8282
"finish__timing__setup__ws": {
83-
"value": -50.0,
83+
"value": -128.0,
8484
"compare": ">="
8585
},
8686
"finish__timing__setup__tns": {
87-
"value": -200.0,
87+
"value": -12600.0,
8888
"compare": ">="
8989
},
9090
"finish__timing__hold__ws": {
91-
"value": -50.0,
91+
"value": -47.5,
9292
"compare": ">="
9393
},
9494
"finish__timing__hold__tns": {
95-
"value": -200.0,
95+
"value": -190.0,
9696
"compare": ">="
9797
},
9898
"finish__design__instance__area": {

‎flow/designs/asap7/riscv32i/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,8 @@ ifeq ($(BLOCKS),)
1414
export ADDITIONAL_LIBS = $(LIB_DIR)/fakeram7_256x32.lib
1515
endif
1616

17-
export DIE_AREA = 0 0 80 90
18-
export CORE_AREA = 5 5 75 85
17+
export CORE_UTILIZATION = 62
18+
export CORE_MARGIN = 5
1919

2020
export PLACE_DENSITY_LB_ADDON = 0.10
2121

‎flow/designs/asap7/riscv32i/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design riscv_top
22

33
set clk_name clk
44
set clk_port_name clk
5-
set clk_period 1000
5+
set clk_period 950
66
set clk_io_pct 0.125
77

88
set clk_port [get_ports $clk_port_name]

‎flow/designs/asap7/riscv32i/rules-base.json‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -36,11 +36,11 @@
3636
"compare": ">="
3737
},
3838
"cts__timing__hold__ws": {
39-
"value": -50.0,
39+
"value": -47.5,
4040
"compare": ">="
4141
},
4242
"cts__timing__hold__tns": {
43-
"value": -200.0,
43+
"value": -190.0,
4444
"compare": ">="
4545
},
4646
"globalroute__antenna_diodes_count": {
@@ -56,15 +56,15 @@
5656
"compare": ">="
5757
},
5858
"globalroute__timing__hold__ws": {
59-
"value": -50.0,
59+
"value": -47.5,
6060
"compare": ">="
6161
},
6262
"globalroute__timing__hold__tns": {
63-
"value": -200.0,
63+
"value": -190.0,
6464
"compare": ">="
6565
},
6666
"detailedroute__route__wirelength": {
67-
"value": 74215,
67+
"value": 70525,
6868
"compare": "<="
6969
},
7070
"detailedroute__route__drc_errors": {
@@ -84,15 +84,15 @@
8484
"compare": ">="
8585
},
8686
"finish__timing__setup__tns": {
87-
"value": -200.0,
87+
"value": -196.0,
8888
"compare": ">="
8989
},
9090
"finish__timing__hold__ws": {
91-
"value": -50.0,
91+
"value": -47.5,
9292
"compare": ">="
9393
},
9494
"finish__timing__hold__tns": {
95-
"value": -200.0,
95+
"value": -190.0,
9696
"compare": ">="
9797
},
9898
"finish__design__instance__area": {

‎flow/designs/gf180/aes/config.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)
66
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
77
export ABC_AREA = 1
88

9-
export CORE_UTILIZATION = 35
9+
export CORE_UTILIZATION = 50
1010
export CORE_ASPECT_RATIO = 1
1111
export CORE_MARGIN = 2
1212

‎flow/designs/gf180/aes/rules-base.json‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
"compare": "<="
1313
},
1414
"placeopt__design__instance__count__stdcell": {
15-
"value": 24274,
15+
"value": 23788,
1616
"compare": "<="
1717
},
1818
"detailedplace__design__violations": {
@@ -28,11 +28,11 @@
2828
"compare": "<="
2929
},
3030
"cts__timing__setup__ws": {
31-
"value": -0.97,
31+
"value": -0.925,
3232
"compare": ">="
3333
},
3434
"cts__timing__setup__tns": {
35-
"value": -107.0,
35+
"value": -102.0,
3636
"compare": ">="
3737
},
3838
"cts__timing__hold__ws": {
@@ -48,11 +48,11 @@
4848
"compare": "<="
4949
},
5050
"globalroute__timing__setup__ws": {
51-
"value": -1.08,
51+
"value": -1.06,
5252
"compare": ">="
5353
},
5454
"globalroute__timing__setup__tns": {
55-
"value": -124.0,
55+
"value": -119.0,
5656
"compare": ">="
5757
},
5858
"globalroute__timing__hold__ws": {
@@ -80,11 +80,11 @@
8080
"compare": "<="
8181
},
8282
"finish__timing__setup__ws": {
83-
"value": -1.05,
83+
"value": -1.04,
8484
"compare": ">="
8585
},
8686
"finish__timing__setup__tns": {
87-
"value": -118.0,
87+
"value": -114.0,
8888
"compare": ">="
8989
},
9090
"finish__timing__hold__ws": {

‎flow/designs/rapidus2hp/hercules_is_int/config.mk‎

Lines changed: 27 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -27,26 +27,38 @@ export SYNTH_HDL_FRONTEND ?= slang
2727
export SYNTH_HIERARCHICAL ?= 0
2828

2929
# Use $(if) to defer conditional eval until all makefiles are read
30-
#
31-
# | PDK Version | Front End | Place Site | Utilization |
32-
# | ------------| --------- | ---------- | ----------- |
33-
# | all | slang | 6T | 30 |
34-
# | non-0.3 | slang | 8T | 52 |
35-
# | all | verific | 6T | 30 |
36-
# | non-0.3 | verific | 8T | 54 |
37-
# | 0.3 | any | 8T | 56 |
38-
3930
export CORE_UTILIZATION = $(strip \
4031
$(if $(filter 0.3,$(RAPIDUS_PDK_VERSION)), \
41-
56, \
42-
$(if $(filter slang,$(SYNTH_HDL_FRONTEND)), \
43-
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
32+
$(if $(filter ra02h138_DST_45CPP,$(PLACE_SITE)), \
33+
$(if $(filter slang,$(SYNTH_HDL_FRONTEND)), \
34+
$(if $(filter 14LM,$(LAYER_STACK_OPTION)), \
35+
52, \
36+
$(if $(filter 16LM,$(LAYER_STACK_OPTION)), \
37+
54, \
38+
56 \
39+
) \
40+
), \
41+
$(if $(filter 14LM,$(LAYER_STACK_OPTION)), \
42+
50, \
43+
56 \
44+
) \
45+
), \
46+
56 \
47+
), \
48+
$(if $(filter 0.15,$(RAPIDUS_PDK_VERSION)), \
49+
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
4450
30, \
4551
52 \
4652
), \
47-
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
48-
30, \
49-
54 \
53+
$(if $(filter slang,$(SYNTH_HDL_FRONTEND)), \
54+
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
55+
30, \
56+
52 \
57+
), \
58+
$(if $(filter ra02h138_DST_45CPP SC6T,$(PLACE_SITE)), \
59+
30, \
60+
54 \
61+
) \
5062
) \
5163
) \
5264
))

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