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flow/docs/rcx: add GRT-vs-RCX parasitic divergence study
Synthetic left-to-right fan-out designs swept 1..128 across asap7, sky130hd, ihp-sg13g2 and gt2n, measuring WNS at every flow stage plus per-net GRT-estimated vs OpenRCX-extracted parasitics. Shows the global-route WNS estimate diverges from the RCX sign-off for long/high-fan-out nets on asap7 (closes at GRT, fails at finish), is negligible at 130nm, and unmeasurable on gt2n (no OpenRCX deck). Adds a fan-out column to write_net_rc.tcl (used by correlateRC.py), a normalized cross-PDK plotter (bazelisk run //flow/docs/rcx:update), an actionable per-net divergence report, and a README proposing global route flag out-of-envelope nets. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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‎flow/designs/asap7/rcx-fanout-1/config.mk‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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export PLATFORM = asap7
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export DESIGN_NAME = fanout_1
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export DESIGN_NICKNAME = rcx-fanout-1
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export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_1.v
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export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-1/constraint.sdc
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export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-1/io.tcl
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export DIE_AREA = 0 0 150.0 12.0
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export CORE_AREA = 1.0 1.0 149.0 11.0
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export PLACE_DENSITY = 0.10
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# Tiny design: keep the run fast.
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export SKIP_LAST_GASP ?= 1

‎flow/designs/asap7/rcx-fanout-1/constraint.sdc‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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current_design fanout_1
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set clk_period 250
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create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]
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if {[llength [get_ports -quiet reset]] == 1} {
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set_false_path -from [get_ports reset]
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}
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set non_clk_inputs [all_inputs -no_clocks]
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set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
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set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
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set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
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group_path -name reg2reg -from [all_registers] -to [all_registers]

‎flow/designs/asap7/rcx-fanout-1/io.tcl‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
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# fan-out net spans the die from west to east.
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set_io_pin_constraint -direction INPUT -region left:*
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set_io_pin_constraint -direction OUTPUT -region right:*

‎flow/designs/asap7/rcx-fanout-128/config.mk‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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export PLATFORM = asap7
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export DESIGN_NAME = fanout_128
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export DESIGN_NICKNAME = rcx-fanout-128
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export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_128.v
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export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-128/constraint.sdc
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export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-128/io.tcl
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export DIE_AREA = 0 0 264.0 19.8
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export CORE_AREA = 1.0 1.0 263.0 18.8
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export PLACE_DENSITY = 0.10
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# Tiny design: keep the run fast.
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export SKIP_LAST_GASP ?= 1

‎flow/designs/asap7/rcx-fanout-128/constraint.sdc‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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current_design fanout_128
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set clk_period 250
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create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]
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if {[llength [get_ports -quiet reset]] == 1} {
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set_false_path -from [get_ports reset]
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}
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set non_clk_inputs [all_inputs -no_clocks]
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set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
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set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
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set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
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group_path -name reg2reg -from [all_registers] -to [all_registers]

‎flow/designs/asap7/rcx-fanout-128/io.tcl‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
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# fan-out net spans the die from west to east.
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set_io_pin_constraint -direction INPUT -region left:*
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set_io_pin_constraint -direction OUTPUT -region right:*

‎flow/designs/asap7/rcx-fanout-16/config.mk‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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export PLATFORM = asap7
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export DESIGN_NAME = fanout_16
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export DESIGN_NICKNAME = rcx-fanout-16
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export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_16.v
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export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-16/constraint.sdc
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export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-16/io.tcl
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export DIE_AREA = 0 0 150.0 12.0
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export CORE_AREA = 1.0 1.0 149.0 11.0
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export PLACE_DENSITY = 0.10
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# Tiny design: keep the run fast.
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export SKIP_LAST_GASP ?= 1

‎flow/designs/asap7/rcx-fanout-16/constraint.sdc‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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current_design fanout_16
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set clk_period 250
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create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]
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if {[llength [get_ports -quiet reset]] == 1} {
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set_false_path -from [get_ports reset]
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}
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set non_clk_inputs [all_inputs -no_clocks]
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set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
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set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
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set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
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group_path -name reg2reg -from [all_registers] -to [all_registers]

‎flow/designs/asap7/rcx-fanout-16/io.tcl‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
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# fan-out net spans the die from west to east.
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set_io_pin_constraint -direction INPUT -region left:*
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set_io_pin_constraint -direction OUTPUT -region right:*

‎flow/designs/asap7/rcx-fanout-2/config.mk‎

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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
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export PLATFORM = asap7
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export DESIGN_NAME = fanout_2
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export DESIGN_NICKNAME = rcx-fanout-2
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export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_2.v
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export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-2/constraint.sdc
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export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-2/io.tcl
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export DIE_AREA = 0 0 150.0 12.0
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export CORE_AREA = 1.0 1.0 149.0 11.0
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export PLACE_DENSITY = 0.10
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# Tiny design: keep the run fast.
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export SKIP_LAST_GASP ?= 1

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