Add option of synthesis using 'syn'

Signed-off-by: Martin Povišer <povik@cutebit.org>

Author: povik

docs/user/FlowVariables.md

@@ -311,6 +311,7 @@ configuration file.
 | <a name="SYNTH_RETIME_MODULES"></a>SYNTH_RETIME_MODULES| *This is an experimental option and may cause adverse effects.* *No effort has been made to check if the retimed RTL is logically equivalent to the non-retimed RTL.* List of modules to apply automatic retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. The main use case is to quickly identify if performance can be improved by manually retiming the input RTL. Retiming will treat module ports like register endpoints/startpoints. The objective function of retiming isn't informed by SDC, even the clock period is ignored. As such, retiming will optimize for best delay at potentially high register number cost. Automatic retiming can produce suboptimal results as its timing model is crude and it doesn't find the optimal distribution of registers on long pipelines. See OR discussion  # 8080.| |
 | <a name="SYNTH_SKIP_KEEP"></a>SYNTH_SKIP_KEEP| Only meaningful together with SYNTH_CHECKPOINT. When set, signals that the supplied checkpoint is still canonical RTLIL (coarse synth and `keep_hierarchy` have not been run yet), so synth.tcl runs the full coarse+fine synthesis flattened. When unset and SYNTH_CHECKPOINT is used, synth.tcl assumes the checkpoint already has coarse synth + `keep_hierarchy` done and resumes from `coarse:fine`.| 0|
 | <a name="SYNTH_SLANG_ARGS"></a>SYNTH_SLANG_ARGS| Additional arguments passed to the slang frontend during synthesis.| |
+| <a name="SYNTH_USE_SYN"></a>SYNTH_USE_SYN| If set to 1, run synthesis using the "syn" tool built into OpenROAD (the synth_syn.tcl flow) instead of the default Yosys-based flow. Defaults to 0 (Yosys flow).| 0|
 | <a name="SYNTH_WRAPPED_ADDERS"></a>SYNTH_WRAPPED_ADDERS| Specify the adder modules that can be used for synthesis, separated by commas. The default adder module is determined by the first element of this variable.| |
 | <a name="SYNTH_WRAPPED_MULTIPLIERS"></a>SYNTH_WRAPPED_MULTIPLIERS| Specify the multiplier modules that can be used for synthesis, separated by commas. The default multiplier module is determined by the first element of this variable.| |
 | <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| |
@@ -349,6 +350,7 @@ configuration file.
 - [PRE_SYNTH_TCL](#PRE_SYNTH_TCL)
 - [SDC_FILE](#SDC_FILE)
 - [SDC_GUT](#SDC_GUT)
+- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [SLANG_PLUGIN_PATH](#SLANG_PLUGIN_PATH)
 - [SYNTH_ARGS](#SYNTH_ARGS)
 - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
@@ -371,6 +373,7 @@ configuration file.
 - [SYNTH_RETIME_MODULES](#SYNTH_RETIME_MODULES)
 - [SYNTH_SKIP_KEEP](#SYNTH_SKIP_KEEP)
 - [SYNTH_SLANG_ARGS](#SYNTH_SLANG_ARGS)
+- [SYNTH_USE_SYN](#SYNTH_USE_SYN)
 - [SYNTH_WRAPPED_ADDERS](#SYNTH_WRAPPED_ADDERS)
 - [SYNTH_WRAPPED_MULTIPLIERS](#SYNTH_WRAPPED_MULTIPLIERS)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)

flow/Makefile

@@ -404,7 +404,11 @@ floorplan_to_place: $(RESULTS_DIR)/1_synth.odb $(RESULTS_DIR)/1_synth.sdc
 
 # ==============================================================================
 
+ifeq ($(SYNTH_USE_SYN),1)
+$(eval $(call do-step,1_synth,$(VERILOG_FILES) $(SDC_FILE) $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(LIB_FILES),synth_syn))
+else
 $(eval $(call do-step,1_synth,$(RESULTS_DIR)/1_2_yosys.v $(RESULTS_DIR)/1_2_yosys.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(LIB_FILES),synth_odb))
+endif
 
 $(RESULTS_DIR)/1_synth.sdc: $(RESULTS_DIR)/1_synth.odb
 

flow/scripts/synth_syn.tcl

@@ -0,0 +1,76 @@
+utl::set_metrics_stage "synth__{}"
+source $::env(SCRIPTS_DIR)/load.tcl
+erase_non_stage_variables synth
+
+source_env_var_if_exists PLATFORM_TCL
+source $::env(SCRIPTS_DIR)/read_liberty.tcl
+
+read_lef $::env(TECH_LEF)
+read_lef $::env(SC_LEF)
+if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } {
+  foreach lef $::env(ADDITIONAL_LEFS) {
+    read_lef $lef
+  }
+}
+if { [env_var_exists_and_non_empty DONT_USE_CELLS] } {
+  set_dont_use $::env(DONT_USE_CELLS)
+}
+
+# Setup verilog include directories
+set vIdirsArgs ""
+if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } {
+  foreach dir $::env(VERILOG_INCLUDE_DIRS) {
+    lappend vIdirsArgs "-I$dir"
+  }
+  set vIdirsArgs [join $vIdirsArgs]
+}
+
+set elaborate_args [list \
+  -D SYNTHESIS --compat=vcs --ignore-assertions --no-implicit-memories --top $::env(DESIGN_NAME) \
+  {*}$vIdirsArgs {*}[env_var_or_empty VERILOG_DEFINES]]
+
+lappend elaborate_args {*}$::env(VERILOG_FILES)
+
+# Apply top-level parameters
+dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] {
+  lappend elaborate_args -G "$key=$value"
+}
+
+# Apply module blackboxing based on module names as they appear
+# in the input, that is before any module name mangling done
+# by elaboration and synthesis
+if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } {
+  foreach m $::env(SYNTH_BLACKBOXES) {
+    lappend elaborate_args --blackboxed-module "$m"
+  }
+}
+
+lappend elaborate_args {*}$::env(SYNTH_SLANG_ARGS)
+
+# If the sources are solely .v files, enable Verilog compatibility
+set has_non_v_files false
+foreach fn $::env(VERILOG_FILES) {
+  if { [file extension [string trim $fn]] != ".v" } {
+    set has_non_v_files true
+  }
+}
+if { !$has_non_v_files } {
+  lappend elaborate_args --std=1364-2005
+}
+
+sv_elaborate {*}$elaborate_args
+syn::stats
+
+synthesize
+
+read_sdc $::env(SDC_FILE)
+repair_design -pre_placement
+
+report_metrics 1 "synth" false false
+
+orfs_write_db $::env(RESULTS_DIR)/1_synth.odb
+# Canonicalize 1_synth.sdc. The original SDC_FILE provided by
+# the user could have dependencies, such as sourcing util.tcl,
+# which are read in here and a canonicalized version is written
+# out by OpenSTA that has no dependencies.
+orfs_write_sdc $::env(RESULTS_DIR)/1_synth.sdc

flow/scripts/variables.json

@@ -115,6 +115,7 @@ SKIP_REPORT_METRICS:
     If set to 1, then metrics, report_metrics does nothing. Useful to speed up
     builds.
   stages:
+    - synth
     - floorplan
     - place
     - cts
@@ -180,6 +181,14 @@ SYNTH_HIERARCHICAL:
   stages:
     - synth
   default: 0
+SYNTH_USE_SYN:
+  description: >
+    If set to 1, run synthesis using the "syn" tool built into OpenROAD
+    (the synth_syn.tcl flow) instead of the default Yosys-based flow.
+    Defaults to 0 (Yosys flow).
+  stages:
+    - synth
+  default: 0
 SYNTH_MEMORY_MAX_BITS:
   description: >
     Maximum number of bits for memory synthesis.

flow/scripts/variables.yaml

@@ -209,6 +209,7 @@ def merge_jsons(root_path, output, files):
         with open(path, "r") as file:
             data = json.load(file)
         output.update(data)
+    return len(paths) != 0
 
 
 def extract_metrics(
@@ -246,21 +247,26 @@ def extract_metrics(
     # Synthesis
     # =========================================================================
 
+    # Try sourcing metrics from OpenROAD's syn flow first, fall back to parsing
+    # Yosys reports otherwise
+    found_synthesis_json = merge_jsons(logPath, metrics_dict, "1_*.json")
+
     # The new format (>= 0.57) with -hierarchy is:
     #    <count> <area> <local_count> <local_area> cells
-    extractTagFromFile(
-        "synth__design__instance__count__stdcell",
-        metrics_dict,
-        "^\\s+(\\d+)\\s+[-0-9.]+\\s+\\S+\\s+\\S+\\s+cells$",
-        rptPath + "/synth_stat.txt",
-    )
+    if not found_synthesis_json:
+        extractTagFromFile(
+            "synth__design__instance__count__stdcell",
+            metrics_dict,
+            "^\\s+(\\d+)\\s+[-0-9.]+\\s+\\S+\\s+\\S+\\s+cells$",
+            rptPath + "/synth_stat.txt",
+        )
 
-    extractTagFromFile(
-        "synth__design__instance__area__stdcell",
-        metrics_dict,
-        "Chip area for (?:top )?module.*: +(\\S+)",
-        rptPath + "/synth_stat.txt",
-    )
+        extractTagFromFile(
+            "synth__design__instance__area__stdcell",
+            metrics_dict,
+            "Chip area for (?:top )?module.*: +(\\S+)",
+            rptPath + "/synth_stat.txt",
+        )
 
     # Netlist hashes: fingerprints of the canonical RTLIL (pre-ABC) and
     # the final post-synthesis Verilog so the rules-base.json check
@@ -271,6 +277,7 @@ def extract_metrics(
     )
     metrics_dict["synth__netlist__hash"] = file_sha1(resultPath + "/1_2_yosys.v")
 
+
     # Clocks
     # =========================================================================
     clk_list = read_sdc(resultPath + "/2_floorplan.sdc")