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Merge pull request #4277 from VLSIDA/bspdn-gt2n-pr
gt2n: add 2nm BSPDN platform with gcd and aes designs
2 parents fcf00b7 + 11a10d7 commit c06bf3c

54 files changed

Lines changed: 277880 additions & 1 deletion

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‎.gitignore‎

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@@ -63,6 +63,7 @@ flow/platforms/*
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!flow/platforms/sky130io
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!flow/platforms/sky130ram
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!flow/platforms/gf180
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!flow/platforms/gt2n
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flow/private
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# network

‎flow/designs/gt2n/aes/config.mk‎

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export DESIGN_NICKNAME = aes
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export DESIGN_NAME = aes_cipher_top
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export PLATFORM = gt2n
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export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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# AES is bigger than gcd; give the floorplan more room.
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export CORE_UTILIZATION = 30
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
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export PLACE_DENSITY_LB_ADDON = 0.20
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export TNS_END_PERCENT = 100
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# workaround for high congestion in post-grt repair (matches nangate45/aes)
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export SKIP_INCREMENTAL_REPAIR = 1
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export SWAP_ARITH_OPERATORS = 1
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export OPENROAD_HIERARCHICAL = 1
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# Highest layer aes actually routes on (M11-M13 carry no wire). Capping here
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# instead of the platform M13 top shrinks the detailed-route grid, vias, and
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# DRC. See platforms/gt2n/config.mk.
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export MAX_ROUTING_LAYER = M10

‎flow/designs/gt2n/aes/constraint.sdc‎

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current_design aes_cipher_top
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set clk_name clk
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set clk_port_name clk
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# GT2N lib uses time_unit = 1 ps. 500 ps -> 2 GHz target; first-pass
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# loose, can tighten once routing is clean.
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set clk_period 500
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [all_inputs -no_clocks]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/gt2n/aes/rules-base.json‎

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{
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"synth__canonical_netlist__hash": {
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"value": "e9426c391e35d86c9f9023e814fd4826714b89b5",
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"compare": "==",
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"level": "warning"
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},
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"synth__netlist__hash": {
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"value": "93f9e9316090c4b4b44bf35599036a9c5cdfe109",
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"compare": "==",
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"level": "warning"
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},
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"synth__design__instance__area__stdcell": {
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"value": 492.0,
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"compare": "<="
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},
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"constraints__clocks__count": {
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"value": 1,
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 564,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 20700,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 1800,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 1800,
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"compare": "<="
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},
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"cts__timing__setup__ws": {
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"value": -25.0,
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"compare": ">="
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},
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"cts__timing__setup__tns": {
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"value": -100.0,
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"compare": ">="
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},
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"cts__timing__hold__ws": {
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"value": -25.0,
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"compare": ">="
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},
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"cts__timing__hold__tns": {
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"value": -100.0,
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"compare": ">="
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},
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"globalroute__antenna_diodes_count": {
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"value": 100,
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
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"value": -75.2,
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
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"value": -585.0,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
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"value": -41.2,
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"compare": ">="
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},
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"globalroute__timing__hold__tns": {
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"value": -1220.0,
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
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"value": 42394,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna__violating__nets": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna_diodes_count": {
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"value": 100,
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -75.2,
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"compare": ">="
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},
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"finish__timing__setup__tns": {
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"value": -585.0,
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"compare": ">="
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},
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"finish__timing__hold__ws": {
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"value": -41.2,
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"compare": ">="
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},
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"finish__timing__hold__tns": {
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"value": -1220.0,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 1636,
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"compare": "<="
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}
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}

‎flow/designs/gt2n/gcd/config.mk‎

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export DESIGN_NICKNAME = gcd
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export DESIGN_NAME = gcd
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export PLATFORM = gt2n
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
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export CORE_UTILIZATION = 25
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export CORE_MARGIN = 0.5
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export PLACE_DENSITY = 0.35
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export TNS_END_PERCENT = 100
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# Highest layer gcd actually routes on (M6-M13 carry no wire). Capping here
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# instead of the platform M13 top shrinks the detailed-route grid, vias, and
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# DRC. See platforms/gt2n/config.mk.
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export MAX_ROUTING_LAYER = M5

‎flow/designs/gt2n/gcd/constraint.sdc‎

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current_design gcd
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set clk_name core_clock
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set clk_port_name clk
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# 500 ps clock (2 GHz) — modest target; lib path delays grow once realistic
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# wire RC kicks in. Tighten once a clean run lands.
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set clk_period 500
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [all_inputs -no_clocks]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/gt2n/gcd/rules-base.json‎

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{
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"synth__canonical_netlist__hash": {
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"value": "94435b2c79066c9133b4aed43b6f5abf1ec21003",
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"compare": "==",
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"level": "warning"
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},
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"synth__netlist__hash": {
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"value": "102bf37d6da7bc1aa234e916ebbf91984197836d",
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"compare": "==",
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"level": "warning"
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},
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"synth__design__instance__area__stdcell": {
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"value": 18.8,
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"compare": "<="
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},
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"constraints__clocks__count": {
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"value": 1,
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 22,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 877,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 76,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 76,
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"compare": "<="
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},
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"cts__timing__setup__ws": {
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"value": -25.0,
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"compare": ">="
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},
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"cts__timing__setup__tns": {
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"value": -100.0,
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"compare": ">="
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},
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"cts__timing__hold__ws": {
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"value": -25.0,
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"compare": ">="
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},
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"cts__timing__hold__tns": {
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"value": -100.0,
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"compare": ">="
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},
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"globalroute__antenna_diodes_count": {
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"value": 100,
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
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"value": -25.0,
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
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"value": -100.0,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
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"value": -25.0,
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"compare": ">="
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},
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"globalroute__timing__hold__tns": {
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"value": -100.0,
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
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"value": 848,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna__violating__nets": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna_diodes_count": {
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"value": 100,
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -25.0,
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"compare": ">="
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},
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"finish__timing__setup__tns": {
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"value": -100.0,
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"compare": ">="
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},
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"finish__timing__hold__ws": {
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"value": -25.0,
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"compare": ">="
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},
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"finish__timing__hold__tns": {
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"value": -100.0,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 73,
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"compare": "<="
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}
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}

‎flow/designs/gt2n/jpeg/config.mk‎

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export DESIGN_NICKNAME = jpeg
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export DESIGN_NAME = jpeg_encoder
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export PLATFORM = gt2n
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export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
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export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export ABC_AREA = 1
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# Floorplan: jpeg_encoder is larger than aes; start conservative.
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export CORE_UTILIZATION = 40
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
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export PLACE_DENSITY_LB_ADDON = 0.20
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export TNS_END_PERCENT = 100
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# Highest layer jpeg actually routes on (M10-M13 carry no wire). Capping here
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# instead of the platform M13 top shrinks the detailed-route grid, vias, and
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# DRC. See platforms/gt2n/config.mk.
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export MAX_ROUTING_LAYER = M9

‎flow/designs/gt2n/jpeg/constraint.sdc‎

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current_design jpeg_encoder
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set clk_name clk
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set clk_port_name clk
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# GT2N lib uses time_unit = 1 ps. 1500 ps -> 667 MHz. Loose first-pass
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# target with the analytical-RC stand-in -- tighten once the optimize-ppa
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# loop has the baseline period_min.
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set clk_period 1000
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [all_inputs -no_clocks]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

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