@@ -209,7 +209,6 @@ def merge_jsons(root_path, output, files):
209209 with open (path , "r" ) as file :
210210 data = json .load (file )
211211 output .update (data )
212- return len (paths ) != 0
213212
214213
215214def extract_metrics (
@@ -246,27 +245,7 @@ def extract_metrics(
246245
247246 # Synthesis
248247 # =========================================================================
249-
250- # Try sourcing metrics from OpenROAD's syn flow first, fall back to parsing
251- # Yosys reports otherwise
252- found_synthesis_json = merge_jsons (logPath , metrics_dict , "1_*.json" )
253-
254- # The new format (>= 0.57) with -hierarchy is:
255- # <count> <area> <local_count> <local_area> cells
256- if not found_synthesis_json :
257- extractTagFromFile (
258- "synth__design__instance__count__stdcell" ,
259- metrics_dict ,
260- "^\\ s+(\\ d+)\\ s+[-0-9.]+\\ s+\\ S+\\ s+\\ S+\\ s+cells$" ,
261- rptPath + "/synth_stat.txt" ,
262- )
263-
264- extractTagFromFile (
265- "synth__design__instance__area__stdcell" ,
266- metrics_dict ,
267- "Chip area for (?:top )?module.*: +(\\ S+)" ,
268- rptPath + "/synth_stat.txt" ,
269- )
248+ merge_jsons (logPath , metrics_dict , "1_*.json" )
270249
271250 # Netlist hashes: fingerprints of the canonical RTLIL (pre-ABC) and
272251 # the final post-synthesis Verilog so the rules-base.json check
@@ -277,7 +256,6 @@ def extract_metrics(
277256 )
278257 metrics_dict ["synth__netlist__hash" ] = file_sha1 (resultPath + "/1_2_yosys.v" )
279258
280-
281259 # Clocks
282260 # =========================================================================
283261 clk_list = read_sdc (resultPath + "/2_floorplan.sdc" )
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