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Merge pull request #4291 from The-OpenROAD-Project-staging/log-synth-syn
add log_cmd in scripts/synth_syn.tcl
2 parents ff182f8 + cd6a30c commit d243ada

1 file changed

Lines changed: 9 additions & 9 deletions

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flow/scripts/synth_syn.tcl

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,15 @@ erase_non_stage_variables synth
55
source_env_var_if_exists PLATFORM_TCL
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source $::env(SCRIPTS_DIR)/read_liberty.tcl
77

8-
read_lef $::env(TECH_LEF)
9-
read_lef $::env(SC_LEF)
8+
log_cmd read_lef $::env(TECH_LEF)
9+
log_cmd read_lef $::env(SC_LEF)
1010
if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } {
1111
foreach lef $::env(ADDITIONAL_LEFS) {
12-
read_lef $lef
12+
log_cmd read_lef $lef
1313
}
1414
}
1515
if { [env_var_exists_and_non_empty DONT_USE_CELLS] } {
16-
set_dont_use $::env(DONT_USE_CELLS)
16+
log_cmd set_dont_use $::env(DONT_USE_CELLS)
1717
}
1818

1919
# Setup verilog include directories
@@ -58,13 +58,13 @@ if { !$has_non_v_files } {
5858
lappend elaborate_args --std=1364-2005
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}
6060

61-
sv_elaborate {*}$elaborate_args
62-
syn::stats
61+
log_cmd sv_elaborate {*}$elaborate_args
62+
log_cmd syn::stats
6363

64-
synthesize
64+
log_cmd synthesize
6565

66-
read_sdc $::env(SDC_FILE)
67-
repair_design -pre_placement
66+
log_cmd read_sdc $::env(SDC_FILE)
67+
log_cmd repair_design -pre_placement
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6969
report_metrics 1 "synth" false false
7070

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