synth: apply SYNTH_BLACKBOXES to loaded RTLIL after checkpoint read

The preamble already registers SYNTH_BLACKBOXES at the HDL-read stage,
but when synth.tcl is entered via a pre-loaded RTLIL checkpoint (see
SYNTH_CHECKPOINT) the preamble is not involved, so the blackbox list
needs a second application point on the loaded netlist.

Run the same list through `blackbox` between read_checkpoint and
hierarchy -check. Wrap each in `catch` so stale names from a static
list don't fail the flow — matches the existing "non-existent modules
are ignored silently" documentation for the variable.

The variable's doc entry already notes Bazel parallel synth; extended
to call out the post-checkpoint apply point for completeness.

Author: oharboe

docs/user/FlowVariables.md

@@ -289,7 +289,7 @@ configuration file.
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| |
 | <a name="SWAP_ARITH_OPERATORS"></a>SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| |
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| |
-| <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design. Non-existant modules are ignored silently, useful when listing modules statically, even if modules come and go dynamically.| |
+| <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design. Non-existant modules are ignored silently, useful when listing modules statically, even if modules come and go dynamically. The list is applied both at the HDL-read stage (preamble) and post-checkpoint in synth.tcl so it also takes effect when reading an RTLIL checkpoint directly via SYNTH_CHECKPOINT.| |
 | <a name="SYNTH_CANONICALIZE_TCL"></a>SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| 0|
 | <a name="SYNTH_HDL_FRONTEND"></a>SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| |

flow/scripts/synth.tcl

@@ -34,6 +34,16 @@ proc get_dfflegalize_args { file_path } {
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
 read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil
 
+# Apply SYNTH_BLACKBOXES to the loaded RTLIL. In the normal flow the
+# preamble already registered these at the HDL-read stage, so this pass
+# is a no-op; the `catch` also lets it run harmlessly when the named
+# modules aren't present in the design (e.g. from a stale static list).
+if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } {
+  foreach m $::env(SYNTH_BLACKBOXES) {
+    catch { blackbox $m }
+  }
+}
+
 hierarchy -check -top $::env(DESIGN_NAME)
 
 if { $::env(SYNTH_GUT) } {

flow/scripts/variables.yaml

@@ -254,6 +254,9 @@ SYNTH_BLACKBOXES:
     to run synthesis in parallel for the large modules of the design.
     Non-existant modules are ignored silently, useful when listing modules
     statically, even if modules come and go dynamically.
+    The list is applied both at the HDL-read stage (preamble) and
+    post-checkpoint in synth.tcl so it also takes effect when reading
+    an RTLIL checkpoint directly via SYNTH_CHECKPOINT.
   stages:
     - synth
 SYNTH_NETLIST_FILES: