Merge pull request #3810 from The-OpenROAD-Project-staging/tighten-cva6-0.2

Tightened rapidus2hp cva6 for PDK 0.2

Author: maliberty

flow/designs/rapidus2hp/cva6/config.mk

@@ -117,7 +117,7 @@ export SDC_FILE = $(strip \
     ))
 
 # Must be defined before the ifeq's
-export SYNTH_HDL_FRONTEND  = slang
+export SYNTH_HDL_FRONTEND  ?= slang
 export SYNTH_HIERARCHICAL = 1
 
 export CORE_UTILIZATION       = 65

flow/designs/rapidus2hp/cva6/constraint.sdc

@@ -5,7 +5,7 @@ source $::env(PLATFORM_DIR)/util.tcl
 set clk_name main_clk
 set clk_port clk_i
 set clk_ports_list [list $clk_port]
-set clk_period 1125
+set clk_period 800
 
 convert_time_value clk_period
 

flow/designs/rapidus2hp/cva6/rules-verific.json

@@ -36,11 +36,11 @@
         "compare": ">="
     },
     "cts__timing__hold__ws": {
-        "value": -56.2,
+        "value": -54.9,
         "compare": ">="
     },
     "cts__timing__hold__tns": {
-        "value": -268.0,
+        "value": -1320.0,
         "compare": ">="
     },
     "globalroute__antenna_diodes_count": {
@@ -52,31 +52,31 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -102000.0,
+        "value": -89500.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
-        "value": -36.1,
+        "value": -31.4,
         "compare": ">="
     },
     "globalroute__timing__hold__tns": {
-        "value": -134.0,
+        "value": -125.0,
         "compare": ">="
     },
     "finish__timing__setup__ws": {
         "value": -108.0,
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -102000.0,
+        "value": -89500.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
-        "value": -36.1,
+        "value": -31.4,
         "compare": ">="
     },
     "finish__timing__hold__tns": {
-        "value": -134.0,
+        "value": -125.0,
         "compare": ">="
     },
     "finish__design__instance__area": {