Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenROAD-flow-scripts into update_designs_config

Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>

Author: eder-matheus

flow/designs/asap7/aes-block/rules-base.json

@@ -24,15 +24,15 @@
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 1445,
+        "value": 923,
         "compare": "<="
     },
     "cts__timing__setup__ws": {
-        "value": -162.0,
+        "value": -124.0,
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -9000.0,
+        "value": -5920.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -48,11 +48,11 @@
         "compare": "<="
     },
     "globalroute__timing__setup__ws": {
-        "value": -164.0,
+        "value": -150.0,
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -8520.0,
+        "value": -6750.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -80,7 +80,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -129.0,
+        "value": -116.0,
         "compare": ">="
     },
     "finish__timing__setup__tns": {

flow/designs/asap7/aes/config.mk

@@ -29,3 +29,5 @@ else ifeq ($(FLOW_VARIANT),combine)
 	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v \
 	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v
 endif
+
+export LEC_CHECK = 1

flow/designs/asap7/ibex/rules-base.json

@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -35900.0,
+        "value": -29100.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -57400.0,
+        "value": -57800.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -34700.0,
+        "value": -22600.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

flow/designs/asap7/mock-alu/rules-base.json

@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -17200.0,
+        "value": -17300.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

flow/designs/asap7/riscv32i-mock-sram/rules-base.json

@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 73284,
+        "value": 72999,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -12600.0,
+        "value": -8360.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

flow/designs/asap7/riscv32i/rules-base.json

@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -200.0,
+        "value": -503.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 70525,
+        "value": 70494,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {

flow/designs/asap7/swerv_wrapper/rules-base.json

@@ -80,19 +80,19 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -412.0,
+        "value": -402.0,
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -78000.0,
+        "value": -75900.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
-        "value": -215.0,
+        "value": -200.0,
         "compare": ">="
     },
     "finish__timing__hold__tns": {
-        "value": -45700.0,
+        "value": -45200.0,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/asap7/uart/config.mk

@@ -18,3 +18,4 @@ export REMOVE_CELLS_FOR_EQY   = TAPCELL*
 export SKIP_GATE_CLONING      = 1
 export VERILOG_TOP_PARAMS     = DATA_WIDTH 8
 export SYNTH_HDL_FRONTEND     = slang
+export LEC_CHECK = 1

flow/designs/gf12/swerv_wrapper/macros.v

@@ -11,7 +11,7 @@ module ram_2048x39(CLK, ADR, D, Q, WE);
   wire n_21;
   gf12_1rf_lg11_w40_all mem(.CLK (CLK), .Q ({Q_int[39], Q}), .CEN
        (1'b1), .GWEN (n_21), .A (ADR), .D ({1'b0, D}), .EMA (3'b011),
-       .EMAW (2'b01), .RET1N (1'b1));
+       .EMAW (2'b01), .EMAS (1'b0), .STOV (1'b0), .RET1N (1'b1));
   assign n_21 = ~(WE);
 endmodule
 
@@ -28,7 +28,7 @@ module ram_64x21(CLK, ADR, D, Q, WE);
   wire n_16;
   gf12_1rf_lg6_w22_all mem(.CLK (CLK), .Q ({Q_int[21], Q}), .CEN
        (1'b1), .GWEN (n_16), .A (ADR), .D ({1'b0, D}), .EMA (3'b011),
-       .EMAW (2'b01), .RET1N (1'b1));
+       .EMAW (2'b01), .EMAS (1'b0), .STOV (1'b0), .RET1N (1'b1));
   assign n_16 = ~(WE);
 endmodule
 
@@ -43,7 +43,7 @@ module ram_256x34(CLK, ADR, D, Q, WE);
   wire [33:0] Q;
   wire n_51;
   gf12_1rf_lg8_w34_all mem(.CLK (CLK), .Q (Q), .CEN (1'b1), .GWEN
-       (n_51), .A (ADR), .D (D), .EMA (3'b011), .EMAW (2'b01), .RET1N
-       (1'b1));
+       (n_51), .A (ADR), .D (D), .EMA (3'b011), .EMAW (2'b01),
+       .EMAS (1'b0), .STOV (1'b0), .RET1N (1'b1));
   assign n_51 = ~(WE);
 endmodule

flow/designs/gf12/swerv_wrapper/rules-base.json

@@ -28,15 +28,15 @@
         "compare": "<="
     },
     "cts__timing__setup__ws": {
-        "value": -172.0,
+        "value": -84.0,
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -899.0,
+        "value": -374.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
-        "value": -108.0,
+        "value": -197.0,
         "compare": ">="
     },
     "cts__timing__hold__tns": {