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jhkim-piijhkim-pii
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flow: Use virtual clocks for IO delays
Create virtual IO reference clocks for SDC input and output delay constraints so post-CTS propagated real clocks do not become the external timing reference. Propagate only the real design clocks in post-CTS SDCs while preserving virtual clock latency for IO timing. Update the OpenROAD submodule pointer to include the CTS virtual clock latency fix used by these constraints. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
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64 files changed

Lines changed: 16383 additions & 16125 deletions

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‎flow/designs/asap7/aes/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,12 @@ set clk_io_pct 0.2
66
set clk_port [get_ports $clk_port_name]
77

88
create_clock -name $clk_name -period $clk_period $clk_port
9+
set clk_io_name vclk_$clk_name
10+
create_clock -name $clk_io_name -period $clk_period
11+
set_clock_latency $clk_period [get_clocks $clk_name]
12+
set_clock_latency $clk_period [get_clocks $clk_io_name]
913

1014
set non_clock_inputs [all_inputs -no_clocks]
1115

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
16+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
17+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/asap7/ethmac/constraint.sdc‎

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,29 +3,41 @@ set clk_period 1000
33
set clk_io_pct 0.2
44
set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
6+
set top_io_clk_name vclk_$top_clk_name
7+
create_clock -name $top_io_clk_name -period $clk_period
8+
set_clock_latency $clk_period [get_clocks $top_clk_name]
9+
set_clock_latency $clk_period [get_clocks $top_io_clk_name]
610
set non_clock_inputs [all_inputs -no_clocks]
7-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
8-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
11+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name $non_clock_inputs
12+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name [all_outputs]
913

1014
set tx_clk_name mtx_clk_pad_i
1115
set tx_clk_port [get_ports $tx_clk_name]
1216
set tx_clk_period 300
1317
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
18+
set tx_io_clk_name vclk_$tx_clk_name
19+
create_clock -name $tx_io_clk_name -period $tx_clk_period
20+
set_clock_latency $tx_clk_period [get_clocks $tx_clk_name]
21+
set_clock_latency $tx_clk_period [get_clocks $tx_io_clk_name]
1422
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
15-
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
16-
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
23+
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name $mtx_non_clock_inputs
24+
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name [all_outputs]
1725

1826
set rx_clk_name mrx_clk_pad_i
1927
set rx_clk_port [get_ports $rx_clk_name]
2028
set rx_clk_period 300
2129
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
30+
set rx_io_clk_name vclk_$rx_clk_name
31+
create_clock -name $rx_io_clk_name -period $rx_clk_period
32+
set_clock_latency $rx_clk_period [get_clocks $rx_clk_name]
33+
set_clock_latency $rx_clk_period [get_clocks $rx_io_clk_name]
2234
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
23-
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
24-
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
35+
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name $mrx_non_clock_inputs
36+
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name [all_outputs]
2537

2638
set_clock_groups -name core_clock -logically_exclusive \
27-
-group [get_clocks $top_clk_name] \
28-
-group [get_clocks $tx_clk_name] \
29-
-group [get_clocks $rx_clk_name]
39+
-group [concat [get_clocks $top_clk_name] [get_clocks $top_io_clk_name]] \
40+
-group [concat [get_clocks $tx_clk_name] [get_clocks $tx_io_clk_name]] \
41+
-group [concat [get_clocks $rx_clk_name] [get_clocks $rx_io_clk_name]]
3042

3143
set_max_fanout 10 [current_design]

‎flow/designs/asap7/ethmac_lvt/constraint.sdc‎

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,27 +3,39 @@ set clk_period 1000
33
set clk_io_pct 0.2
44
set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
6+
set top_io_clk_name vclk_$top_clk_name
7+
create_clock -name $top_io_clk_name -period $clk_period
8+
set_clock_latency $clk_period [get_clocks $top_clk_name]
9+
set_clock_latency $clk_period [get_clocks $top_io_clk_name]
610
set non_clock_inputs [all_inputs -no_clocks]
7-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
8-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
11+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name $non_clock_inputs
12+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name [all_outputs]
913

1014
set tx_clk_name mtx_clk_pad_i
1115
set tx_clk_port [get_ports $tx_clk_name]
1216
set tx_clk_period 300
1317
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
18+
set tx_io_clk_name vclk_$tx_clk_name
19+
create_clock -name $tx_io_clk_name -period $tx_clk_period
20+
set_clock_latency $tx_clk_period [get_clocks $tx_clk_name]
21+
set_clock_latency $tx_clk_period [get_clocks $tx_io_clk_name]
1422
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
15-
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
16-
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
23+
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name $mtx_non_clock_inputs
24+
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name [all_outputs]
1725

1826
set rx_clk_name mrx_clk_pad_i
1927
set rx_clk_port [get_ports $rx_clk_name]
2028
set rx_clk_period 300
2129
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
30+
set rx_io_clk_name vclk_$rx_clk_name
31+
create_clock -name $rx_io_clk_name -period $rx_clk_period
32+
set_clock_latency $rx_clk_period [get_clocks $rx_clk_name]
33+
set_clock_latency $rx_clk_period [get_clocks $rx_io_clk_name]
2234
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
23-
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
24-
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
35+
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name $mrx_non_clock_inputs
36+
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name [all_outputs]
2537

2638
set_clock_groups -name core_clock -logically_exclusive \
27-
-group [get_clocks $top_clk_name] \
28-
-group [get_clocks $tx_clk_name] \
29-
-group [get_clocks $rx_clk_name]
39+
-group [concat [get_clocks $top_clk_name] [get_clocks $top_io_clk_name]] \
40+
-group [concat [get_clocks $tx_clk_name] [get_clocks $tx_io_clk_name]] \
41+
-group [concat [get_clocks $rx_clk_name] [get_clocks $rx_io_clk_name]]

‎flow/designs/asap7/gcd/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,12 @@ set clk_io_pct 0.2
88
set clk_port [get_ports $clk_port_name]
99

1010
create_clock -name $clk_name -period $clk_period $clk_port
11+
set clk_io_name vclk_$clk_name
12+
create_clock -name $clk_io_name -period $clk_period
13+
set_clock_latency $clk_period [get_clocks $clk_name]
14+
set_clock_latency $clk_period [get_clocks $clk_io_name]
1115

1216
set non_clock_inputs [all_inputs -no_clocks]
1317

14-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
15-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
18+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
19+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/asap7/ibex/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,12 @@ set clk_io_pct 0.2
66
set clk_port [get_ports $clk_port_name]
77

88
create_clock -name $clk_name -period $clk_period $clk_port
9+
set clk_io_name vclk_$clk_name
10+
create_clock -name $clk_io_name -period $clk_period
11+
set_clock_latency $clk_period [get_clocks $clk_name]
12+
set_clock_latency $clk_period [get_clocks $clk_io_name]
913

1014
set non_clock_inputs [all_inputs -no_clocks]
1115

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
16+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
17+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/asap7/ibex/constraint_pos_slack.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,12 @@ set clk_io_pct 0.2
66
set clk_port [get_ports $clk_port_name]
77

88
create_clock -name $clk_name -period $clk_period $clk_port
9+
set clk_io_name vclk_$clk_name
10+
create_clock -name $clk_io_name -period $clk_period
11+
set_clock_latency $clk_period [get_clocks $clk_name]
12+
set_clock_latency $clk_period [get_clocks $clk_io_name]
913

1014
set non_clock_inputs [all_inputs -no_clocks]
1115

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
16+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
17+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc‎

Lines changed: 50 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,10 @@ set_units -time 1.0ps
77
current_design jpeg_encoder
88

99
create_clock -name "tclk" -period 1000.0 -waveform {0.0 500.0} [get_ports clk]
10-
set_propagated_clock [all_clocks]
10+
create_clock -name vclk -period 1000.0
11+
set_clock_latency 1000.0 [get_clocks {tclk}]
12+
set_clock_latency 1000.0 [get_clocks {vclk}]
13+
set_propagated_clock [get_clocks tclk]
1114
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[5]}]
1215
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[4]}]
1316
set_load -pin_load -max 3.0 [get_ports {qnt_cnt[3]}]
@@ -96,53 +99,53 @@ group_path -weight 1.000000 -name cg_enable_group_tclk -through [list \
9699
[get_pins RC_CG_DECLONE_HIER_INST/enable]]
97100
set_clock_gating_check -setup 0.0
98101

99-
set_input_delay 100 -clock tclk [get_ports ena]
100-
set_input_delay 100 -clock tclk [get_ports rst]
102+
set_input_delay 100 -clock vclk [get_ports ena]
103+
set_input_delay 100 -clock vclk [get_ports rst]
101104

102-
set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}]
103-
set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}]
104-
set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}]
105-
set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}]
106-
set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}]
107-
set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}]
108-
set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}]
109-
set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}]
110-
set_input_delay 100 -clock tclk [get_ports {din[0]}]
111-
set_input_delay 100 -clock tclk [get_ports {din[1]}]
112-
set_input_delay 100 -clock tclk [get_ports {din[2]}]
113-
set_input_delay 100 -clock tclk [get_ports {din[3]}]
114-
set_input_delay 100 -clock tclk [get_ports {din[4]}]
115-
set_input_delay 100 -clock tclk [get_ports {din[5]}]
116-
set_input_delay 100 -clock tclk [get_ports {din[6]}]
117-
set_input_delay 100 -clock tclk [get_ports {din[7]}]
118-
set_input_delay 100 -clock tclk [get_ports dstrb]
119-
set_output_delay 100 -clock tclk [get_ports douten]
120-
set_output_delay 100 -clock tclk [get_ports {amp[0]}]
121-
set_output_delay 100 -clock tclk [get_ports {amp[1]}]
122-
set_output_delay 100 -clock tclk [get_ports {amp[2]}]
123-
set_output_delay 100 -clock tclk [get_ports {amp[3]}]
124-
set_output_delay 100 -clock tclk [get_ports {amp[4]}]
125-
set_output_delay 100 -clock tclk [get_ports {amp[5]}]
126-
set_output_delay 100 -clock tclk [get_ports {amp[6]}]
127-
set_output_delay 100 -clock tclk [get_ports {amp[7]}]
128-
set_output_delay 100 -clock tclk [get_ports {amp[8]}]
129-
set_output_delay 100 -clock tclk [get_ports {amp[9]}]
130-
set_output_delay 100 -clock tclk [get_ports {amp[10]}]
131-
set_output_delay 100 -clock tclk [get_ports {amp[11]}]
132-
set_output_delay 100 -clock tclk [get_ports {rlen[0]}]
133-
set_output_delay 100 -clock tclk [get_ports {rlen[1]}]
134-
set_output_delay 100 -clock tclk [get_ports {rlen[2]}]
135-
set_output_delay 100 -clock tclk [get_ports {rlen[3]}]
136-
set_output_delay 100 -clock tclk [get_ports {size[0]}]
137-
set_output_delay 100 -clock tclk [get_ports {size[1]}]
138-
set_output_delay 100 -clock tclk [get_ports {size[2]}]
139-
set_output_delay 100 -clock tclk [get_ports {size[3]}]
140-
set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}]
141-
set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}]
142-
set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}]
143-
set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}]
144-
set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}]
145-
set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}]
105+
set_input_delay 100 -clock vclk [get_ports {qnt_val[0]}]
106+
set_input_delay 100 -clock vclk [get_ports {qnt_val[1]}]
107+
set_input_delay 100 -clock vclk [get_ports {qnt_val[2]}]
108+
set_input_delay 100 -clock vclk [get_ports {qnt_val[3]}]
109+
set_input_delay 100 -clock vclk [get_ports {qnt_val[4]}]
110+
set_input_delay 100 -clock vclk [get_ports {qnt_val[5]}]
111+
set_input_delay 100 -clock vclk [get_ports {qnt_val[6]}]
112+
set_input_delay 100 -clock vclk [get_ports {qnt_val[7]}]
113+
set_input_delay 100 -clock vclk [get_ports {din[0]}]
114+
set_input_delay 100 -clock vclk [get_ports {din[1]}]
115+
set_input_delay 100 -clock vclk [get_ports {din[2]}]
116+
set_input_delay 100 -clock vclk [get_ports {din[3]}]
117+
set_input_delay 100 -clock vclk [get_ports {din[4]}]
118+
set_input_delay 100 -clock vclk [get_ports {din[5]}]
119+
set_input_delay 100 -clock vclk [get_ports {din[6]}]
120+
set_input_delay 100 -clock vclk [get_ports {din[7]}]
121+
set_input_delay 100 -clock vclk [get_ports dstrb]
122+
set_output_delay 100 -clock vclk [get_ports douten]
123+
set_output_delay 100 -clock vclk [get_ports {amp[0]}]
124+
set_output_delay 100 -clock vclk [get_ports {amp[1]}]
125+
set_output_delay 100 -clock vclk [get_ports {amp[2]}]
126+
set_output_delay 100 -clock vclk [get_ports {amp[3]}]
127+
set_output_delay 100 -clock vclk [get_ports {amp[4]}]
128+
set_output_delay 100 -clock vclk [get_ports {amp[5]}]
129+
set_output_delay 100 -clock vclk [get_ports {amp[6]}]
130+
set_output_delay 100 -clock vclk [get_ports {amp[7]}]
131+
set_output_delay 100 -clock vclk [get_ports {amp[8]}]
132+
set_output_delay 100 -clock vclk [get_ports {amp[9]}]
133+
set_output_delay 100 -clock vclk [get_ports {amp[10]}]
134+
set_output_delay 100 -clock vclk [get_ports {amp[11]}]
135+
set_output_delay 100 -clock vclk [get_ports {rlen[0]}]
136+
set_output_delay 100 -clock vclk [get_ports {rlen[1]}]
137+
set_output_delay 100 -clock vclk [get_ports {rlen[2]}]
138+
set_output_delay 100 -clock vclk [get_ports {rlen[3]}]
139+
set_output_delay 100 -clock vclk [get_ports {size[0]}]
140+
set_output_delay 100 -clock vclk [get_ports {size[1]}]
141+
set_output_delay 100 -clock vclk [get_ports {size[2]}]
142+
set_output_delay 100 -clock vclk [get_ports {size[3]}]
143+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[0]}]
144+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[1]}]
145+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[2]}]
146+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[3]}]
147+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[4]}]
148+
set_output_delay 100 -clock vclk [get_ports {qnt_cnt[5]}]
146149
set_max_fanout 40.000 [current_design]
147150
set_max_transition 80.0 [current_design]
148151
set_clock_uncertainty -setup 20.0 [get_clocks tclk]

‎flow/designs/asap7/riscv32i/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,11 @@ set clk_io_pct 0.125
88
set clk_port [get_ports $clk_port_name]
99

1010
create_clock -name $clk_name -period $clk_period $clk_port
11+
set clk_io_name vclk_$clk_name
12+
create_clock -name $clk_io_name -period $clk_period
13+
set_clock_latency $clk_period [get_clocks $clk_name]
14+
set_clock_latency $clk_period [get_clocks $clk_io_name]
1115

1216
set non_clock_inputs [all_inputs -no_clocks]
13-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
14-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
17+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
18+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/asap7/uart/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,12 @@ set clk_io_pct 0.2
66
set clk_port [get_ports $clk_port_name]
77

88
create_clock -name $clk_name -period $clk_period $clk_port
9+
set clk_io_name vclk_$clk_name
10+
create_clock -name $clk_io_name -period $clk_period
11+
set_clock_latency $clk_period [get_clocks $clk_name]
12+
set_clock_latency $clk_period [get_clocks $clk_io_name]
913

1014
set non_clock_inputs [all_inputs -no_clocks]
1115

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
16+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
17+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/gf12/aes/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,15 @@ set clk_io_pct 0.2
88
set clk_port [get_ports $clk_port_name]
99

1010
create_clock -name $clk_name -period $clk_period $clk_port
11+
set clk_io_name vclk_$clk_name
12+
create_clock -name $clk_io_name -period $clk_period
13+
set_clock_latency $clk_period [get_clocks $clk_name]
14+
set_clock_latency $clk_period [get_clocks $clk_io_name]
1115

1216
set non_clock_inputs [all_inputs -no_clocks]
1317

14-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
15-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
18+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
19+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]
1620

1721
set_timing_derate -early 0.9500
1822
set_timing_derate -late 1.0500

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