Description
The equivalence checker built into Yosys, eqy, supports the use of .lib models. However, the ORFS flow currently only supports the use of verilog simulation models. This is problematic since it's not uncommon for simulation models for cells to be represented as UDPs, which are not supported by eqy. This makes the equivalence checking feature in ORFS unusable for many vendor libraries -- unless the user hacks the simulation models and replaces the UDP descriptions with synthesizable representations, but that's not really an acceptable solution.
Suggested Solution
To solve this, ORFS could provide a variable which controls what type of model is used for equivalence checking: verilog simulation models or eqy. This variable would be used to control branching logic in the write_eqy_script procedure in the load.tcl file. For example, the variable named EQUIVALENCE_CHECK_USE_LIBS could contain a list of .lib files to use, and the code could look like this:
proc write_eqy_script {} {
set top_cell [current_design]
set cell_files [get_verilog_cells_for_design]
set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w]
# Gold netlist
puts $outfile "\[gold]"
if { [env_var_exists_and_non_empty EQUIVALENCE_CHECK_USE_LIBS] } {
puts $outfile "read_liberty -ignore_miss_func $::env(EQUIVALENCE_CHECK_USE_LIBS)"
} else {
puts $outfile "read_verilog -sv $cell_files"
}
puts $outfile "read_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v \n"
puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
# Modified netlist
puts $outfile "\[gate]"
if { [env_var_exists_and_non_empty EQUIVALENCE_CHECK_USE_LIBS] } {
puts $outfile "read_liberty -ignore_miss_func $::env(EQUIVALENCE_CHECK_USE_LIBS)"
} else {
puts $outfile "read_verilog -sv $cell_files"
}
puts $outfile "read_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v \n"
puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
...
Additional Context
No response
Description
The equivalence checker built into Yosys, eqy, supports the use of .lib models. However, the ORFS flow currently only supports the use of verilog simulation models. This is problematic since it's not uncommon for simulation models for cells to be represented as UDPs, which are not supported by eqy. This makes the equivalence checking feature in ORFS unusable for many vendor libraries -- unless the user hacks the simulation models and replaces the UDP descriptions with synthesizable representations, but that's not really an acceptable solution.
Suggested Solution
To solve this, ORFS could provide a variable which controls what type of model is used for equivalence checking: verilog simulation models or eqy. This variable would be used to control branching logic in the write_eqy_script procedure in the load.tcl file. For example, the variable named EQUIVALENCE_CHECK_USE_LIBS could contain a list of .lib files to use, and the code could look like this:
Additional Context
No response