ASAP7 fakeram_512x8 Verilog model does not compile with Icarus and uses non-overwrite write behavior

[Arcadia-1]

Describe the issue

The ASAP7 fakeram_512x8.v functional Verilog model under ORFS does not compile cleanly with Icarus Verilog, and its write behavior is not normal SRAM overwrite semantics.

This makes it difficult to use the ORFS-provided ASAP7 macro model for open-source gate-level simulation of designs that instantiate fakeram_512x8.

File:

flow/platforms/asap7/verilog/fakeram_512x8.v

Environment

OpenROAD-flow-scripts checkout: 46c636cb79d9b293cf919814be2d05207a7a1dff
Platform: ASAP7
Simulator: Icarus Verilog, invoked with iverilog -g2012

To Reproduce

Minimal testbench:

`timescale 1ns/1ps
module tb;
  reg clk = 0, ce = 1, we = 0;
  reg [8:0] addr = 0;
  reg [7:0] wd = 0;
  wire [7:0] rd;

  fakeram_512x8 dut(
    .rd_out(rd),
    .addr_in(addr),
    .we_in(we),
    .wd_in(wd),
    .clk(clk),
    .ce_in(ce)
  );

  always #5 clk = ~clk;
  initial begin
    #1; $finish;
  end
endmodule

Command:

iverilog -g2012 -Wall -o tb.vvp tb.v flow/platforms/asap7/verilog/fakeram_512x8.v

Observed Result

flow/platforms/asap7/verilog/fakeram_512x8.v:1: warning: timescale for fakeram_512x8 inherited from another file.
tb.v:1: ...: The inherited timescale is here.
flow/platforms/asap7/verilog/fakeram_512x8.v:58: syntax error
flow/platforms/asap7/verilog/fakeram_512x8.v:58: Invalid simple path

Line 58 is inside the specify block:

(posedge clk *> rd_out) = (0, 0);

Additional Concern: write behavior

The same model writes with OR semantics instead of ordinary SRAM overwrite semantics:

mem[addr_in] <= (wd_in) | (mem[addr_in]);

For many functional simulations, users expect a single-port SRAM model to overwrite the addressed location on write:

mem[addr_in] <= wd_in;

If the OR-write behavior is intentional for this fake macro, it would be helpful to document that clearly. If not intentional, the model should probably be changed or a separate Icarus-friendly functional simulation model should be provided.

Expected Behavior

One of the following would make the model more usable:

1. Make fakeram_512x8.v compile under Icarus Verilog, or provide an Icarus-compatible variant without unsupported specify constructs.
2. Clarify whether the OR-write behavior is intentional.
3. Optionally provide a simple functional SRAM model for open-source gate-level simulation use cases where normal overwrite semantics are desired.

Context

This came up while validating an ASAP7 gate-level netlist generated by OpenROAD for a small RAM-backed AXI wrapper. STA used the official ASAP7 Liberty/LEF, but gate-level functional simulation needed a Verilog model for the fakeram_512x8 macro.