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remove manual configs for macro placer from public designs #3167

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Merged
maliberty merged 6 commits into from
May 17, 2025
Merged

remove manual configs for macro placer from public designs #3167

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6fb3ea7
remove mpl manual configurations from public designs
eder-matheus May 15, 2025
15a76b1
use latest openroad
eder-matheus May 15, 2025
3af970a
Merge branch 'master' into mpl_remove_manual_configs
eder-matheus May 16, 2025
ae2ae87
update nangate45/bp_fe
eder-matheus May 16, 2025
4b5c5cd
update nangate45/ariane136 metrics
eder-matheus May 16, 2025
907b5c5
Merge branch 'master' of https://github.com/The-OpenROAD-Project/Open…
eder-matheus May 16, 2025
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5 changes: 0 additions & 5 deletions flow/designs/asap7/riscv32i/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,6 @@ export PLATFORM = asap7

export SYNTH_HIERARCHICAL ?= 1

export RTLMP_MIN_INST = 1000
export RTLMP_MAX_INST = 3500
export RTLMP_MIN_MACRO = 1
export RTLMP_MAX_MACRO = 5

export SYNTH_MINIMUM_KEEP_SIZE ?= 10000

export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/riscv32i/*.v))
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4 changes: 0 additions & 4 deletions flow/designs/asap7/swerv_wrapper/BUILD.bazel
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Original file line number Diff line number Diff line change
Expand Up @@ -100,10 +100,6 @@ orfs_flow(
arguments = {
"LIB_MODEL": "CCS",
"SYNTH_HIERARCHICAL": "1",
"RTLMP_MAX_INST": "30000",
"RTLMP_MIN_INST": "5000",
"RTLMP_MAX_MACRO": "30",
"RTLMP_MIN_MACRO": "4",
"DIE_AREA": "0 0 550 600",
"CORE_AREA": "5 5 545 595",
"PLACE_PINS_ARGS": "-exclude left:* -exclude right:*",
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6 changes: 0 additions & 6 deletions flow/designs/asap7/swerv_wrapper/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -42,12 +42,6 @@ export SYNTH_KEEP_MODULES ?= \
ram_256x34


# RTL_MP Settings
export RTLMP_MAX_INST = 30000
export RTLMP_MIN_INST = 5000
export RTLMP_MAX_MACRO = 30
export RTLMP_MIN_MACRO = 4

export LIB_MODEL = CCS

export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \
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6 changes: 0 additions & 6 deletions flow/designs/nangate45/ariane133/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,6 @@ export PLATFORM = nangate45

export SYNTH_HIERARCHICAL = 1

# RTL_MP Settings
export RTLMP_MAX_INST = 30000
export RTLMP_MIN_INST = 5000
export RTLMP_MAX_MACRO = 16
export RTLMP_MIN_MACRO = 4

export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v

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4 changes: 0 additions & 4 deletions flow/designs/nangate45/ariane136/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,6 @@ export PLATFORM = nangate45
export SYNTH_HIERARCHICAL = 1

# RTL_MP Settings
export RTLMP_MAX_INST = 30000
export RTLMP_MIN_INST = 5000
export RTLMP_MAX_MACRO = 16
export RTLMP_MIN_MACRO = 4
export RTLMP_SIGNATURE_NET_THRESHOLD = 30

export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \
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2 changes: 1 addition & 1 deletion flow/designs/nangate45/ariane136/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
"value": 299,
"value": 509,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
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5 changes: 0 additions & 5 deletions flow/designs/nangate45/black_parrot/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,6 @@ export PLATFORM = nangate45

export SYNTH_HIERARCHICAL = 1
#
# RTL_MP Settings
export RTLMP_MAX_INST = 30000
export RTLMP_MIN_INST = 5000
export RTLMP_MAX_MACRO = 12
export RTLMP_MIN_MACRO = 4

export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v
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9 changes: 2 additions & 7 deletions flow/designs/nangate45/bp_fe_top/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,6 @@ export PLATFORM = nangate45

export SYNTH_HIERARCHICAL = 1
#
# RTL_MP Settings
export RTLMP_MAX_INST = 30000
export RTLMP_MIN_INST = 5000
export RTLMP_MAX_MACRO = 12
export RTLMP_MIN_MACRO = 4

export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v
Expand All @@ -29,8 +24,8 @@ export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl

export MACRO_PLACE_HALO = 10 10

export PLACE_DENSITY_LB_ADDON = 0.10
export PLACE_DENSITY_MAX_POST_HOLD = 0.12
export PLACE_DENSITY_LB_ADDON = 0.11
export PLACE_DENSITY_MAX_POST_HOLD = 0.13
export TNS_END_PERCENT = 100

export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl
4 changes: 2 additions & 2 deletions flow/designs/nangate45/bp_fe_top/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
"value": 2111490,
"value": 2503735,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand Down Expand Up @@ -60,7 +60,7 @@
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
"value": 2500,
"value": 100,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
Expand Down
5 changes: 0 additions & 5 deletions flow/designs/nangate45/bp_multi_top/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,6 @@ export PLATFORM = nangate45

export SYNTH_HIERARCHICAL = 1
#
# RTL_MP Settings
export RTLMP_MAX_INST = 30000
export RTLMP_MIN_INST = 5000
export RTLMP_MAX_MACRO = 12
export RTLMP_MIN_MACRO = 4

export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v
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2 changes: 1 addition & 1 deletion tools/OpenROAD
Open in desktop
Submodule OpenROAD updated 36 files
+20 −0 .github/workflows/github-actions-are-differences-found.yml
+1 −1 etc/DependencyInstaller.sh
+6 −0 src/dbSta/src/dbReadVerilog.cc
+6 −6 src/dbSta/test/report_cell_usage_modinsts_metrics.jsonok
+1 −3 src/dbSta/test/report_cell_usage_modinsts_metrics.ok
+46 −12 src/dpl/src/Optdp.cpp
+3 −3 src/dpl/test/aes-opt.ok
+3 −3 src/dpl/test/blockage1-opt.ok
+3 −3 src/dpl/test/edge_spacing-opt.ok
+3 −3 src/dpl/test/gcd-opt.ok
+3 −3 src/dpl/test/gcd_no_one_site_gaps-opt.ok
+3 −3 src/dpl/test/ibex-opt.ok
+3 −3 src/dpl/test/multi_height1-opt.ok
+3 −3 src/dpl/test/regions1-opt.ok
+3 −3 src/dpl/test/regions2-opt.ok
+113 −73 src/gpl/src/nesterovBase.cpp
+25 −24 src/gpl/src/nesterovBase.h
+3 −5 src/gpl/src/nesterovPlace.cpp
+1 −3 src/gpl/src/nesterovPlace.h
+4 −25 src/gpl/src/routeBase.cpp
+0 −7 src/gpl/src/routeBase.h
+292 −292 src/gpl/test/simple01-td-tune.defok
+1 −3 src/gpl/test/simple01-td-tune.ok
+289 −289 src/gpl/test/simple01-td.defok
+1 −3 src/gpl/test/simple01-td.ok
+5 −0 src/gui/src/clockWidget.cpp
+1 −0 src/gui/src/clockWidget.h
+35 −1 src/gui/src/displayControls.cpp
+1 −0 src/gui/src/displayControls.h
+56 −0 src/gui/src/stub_heatMap.cpp
+2 −1 src/odb/include/odb/util.h
+25 −5 src/odb/src/zutil/util.cpp
+12 −0 src/rcx/src/extRCmodel.cpp
+1 −1 src/sta
+3 −3 test/upf_aes.ok
+3 −3 test/upf_test.ok