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Updated SRAM sizes for asap7 cva6 #3196

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Merged
maliberty merged 2 commits into from
May 29, 2025
Merged

Updated SRAM sizes for asap7 cva6 #3196

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5917742
Updated SRAM sizes for asap7 cva6
jeffng-or May 28, 2025
bfdd26f
updated rules based on die size increase
jeffng-or May 28, 2025
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11 changes: 5 additions & 6 deletions flow/designs/asap7/cva6/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -65,23 +65,22 @@ export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/
$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
$(PLATFORM_DIR)/verilog/fakeram7_256x32.sv
$(PLATFORM_DIR)/verilog/fakeram7_256x256.sv

export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include

export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF

export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x32.lef
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x256.lef

export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x32.lib
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x256.lib

export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

export DIE_AREA = 0 0 250 250
export CORE_AREA = 1.08 1.08 240 240

export DIE_AREA = 0 0 350 350
export CORE_AREA = 1.08 1.08 340 340
export PLACE_DENSITY = 0.50

# a smoketest for this option, there are a
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9 changes: 4 additions & 5 deletions flow/designs/asap7/cva6/rules-base.json
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Original file line number Diff line number Diff line change
@@ -1,19 +1,18 @@
{
"synth__design__instance__area__stdcell": {
"value": 16477.72,
"value": 40692.1,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"compare": "=="
},
"placeopt__design__instance__area": {

"value": 19790,
"value": 45043,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 130789,
"value": 164118,
"compare": "<="
},
"detailedplace__design__violations": {
Expand Down Expand Up @@ -53,7 +52,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 20112,
"value": 45315,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
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4 changes: 2 additions & 2 deletions flow/designs/src/cva6/common/local/util/sram_cache.sv
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Expand Up @@ -52,7 +52,7 @@ module sram_cache #(
rdata_o = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH];
ruser_o = rdata_user[USER_WIDTH-1:0];
end
fakeram7_256x32 i_tc_sram_wrapper(
fakeram7_256x256 i_tc_sram_wrapper(
.clk ( clk_i ),
.ce_in ( req_i ),
.we_in ( we_i ),
Expand Down Expand Up @@ -91,7 +91,7 @@ module sram_cache #(
rdata_o = rdata_user;
ruser_o = '0;
end
fakeram7_256x32 i_tc_sram_wrapper(
fakeram7_256x256 i_tc_sram_wrapper(
.clk ( clk_i ),
.ce_in ( req_i ),
.we_in ( we_i ),
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2 changes: 1 addition & 1 deletion flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv
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Expand Up @@ -39,7 +39,7 @@ module hpdcache_sram
output logic [DATA_SIZE-1:0] rdata
);

fakeram7_256x32 ram_i (
fakeram7_256x256 ram_i (
.clk(clk),
.ce_in(cs),
.we_in(we),
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2 changes: 1 addition & 1 deletion ...esigns/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv
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Expand Up @@ -39,7 +39,7 @@ module hpdcache_sram_wbyteenable
input logic [DATA_SIZE/8-1:0] wbyteenable,
output logic [DATA_SIZE-1:0] rdata
);
fakeram7_256x32 ram_i (
fakeram7_256x256 ram_i (
.clk (clk),
.ce_in(cs),
.we_in(we),
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