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2 changes: 1 addition & 1 deletion flow/designs/asap7/riscv32i-mock-sram/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 2269,
"value": 2616,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
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4 changes: 2 additions & 2 deletions flow/designs/ihp-sg13g2/aes/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 210460,
"value": 253595,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
Expand All @@ -28,7 +28,7 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
"value": 0,
"value": 3,
"compare": "<="
},
"detailedroute__route__wirelength": {
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4 changes: 2 additions & 2 deletions flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -28,11 +28,11 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
"value": 0,
"value": 2,
"compare": "<="
},
"detailedroute__route__wirelength": {
"value": 49751,
"value": 60953,
"compare": "<="
},
"detailedroute__route__drc_errors": {
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2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/ibex/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 305593,
"value": 371258,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
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2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/spi/rules-base.json
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
"value": 4391,
"value": 5088,
"compare": "<="
},
"detailedroute__route__drc_errors": {
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23 changes: 11 additions & 12 deletions flow/platforms/asap7/setRC.tcl
Original file line number Diff line number Diff line change
@@ -1,13 +1,14 @@
# Liberty units are fF,kOhm
set_layer_rc -layer M1 -capacitance 1.1368e-01 -resistance 1.3889e-01
set_layer_rc -layer M2 -capacitance 1.3426e-01 -resistance 2.4222e-02
set_layer_rc -layer M3 -capacitance 1.2918e-01 -resistance 2.4222e-02
set_layer_rc -layer M4 -capacitance 1.1396e-01 -resistance 1.6778e-02
set_layer_rc -layer M5 -capacitance 1.3323e-01 -resistance 1.4677e-02
set_layer_rc -layer M6 -capacitance 1.1575e-01 -resistance 1.0371e-02
set_layer_rc -layer M7 -capacitance 1.3293e-01 -resistance 9.6720e-03
set_layer_rc -layer M8 -capacitance 1.1822e-01 -resistance 7.4310e-03
set_layer_rc -layer M9 -capacitance 1.3497e-01 -resistance 6.8740e-03
# correlation result (aes, cva6, ibex, riscv32i)
# M1 capacitance fixed up from -4.8e-02 to 1e-10 as a minuscule positive value
set_layer_rc -layer M1 -resistance 7.04175E-02 -capacitance 1e-10
set_layer_rc -layer M2 -resistance 4.62311E-02 -capacitance 1.84542E-01
set_layer_rc -layer M3 -resistance 3.63251E-02 -capacitance 1.53955E-01
set_layer_rc -layer M4 -resistance 2.03083E-02 -capacitance 1.89434E-01
set_layer_rc -layer M5 -resistance 1.93005E-02 -capacitance 1.71593E-01
set_layer_rc -layer M6 -resistance 1.18619E-02 -capacitance 1.76146E-01
set_layer_rc -layer M7 -resistance 1.25311E-02 -capacitance 1.47030E-01
set_wire_rc -signal -resistance 3.23151E-02 -capacitance 1.73323E-01
set_wire_rc -clock -resistance 5.13971E-02 -capacitance 1.44549E-01
Comment on lines +10 to +11

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This seems odd as the clock is routed on M4-M7 which signals are on M2-M7. I would expect clocks to see less resistance.

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Clocks might be seeing more via resistance. I double-checked clocks and signals aren't swapped.


set_layer_rc -via V1 -resistance 1.72E-02
set_layer_rc -via V2 -resistance 1.72E-02
Expand All @@ -17,5 +18,3 @@ set_layer_rc -via V5 -resistance 1.18E-02
set_layer_rc -via V6 -resistance 8.20E-03
set_layer_rc -via V7 -resistance 8.20E-03
set_layer_rc -via V8 -resistance 6.30E-03

set_wire_rc -layer M3
22 changes: 9 additions & 13 deletions flow/platforms/ihp-sg13g2/setRC.tcl
Original file line number Diff line number Diff line change
@@ -1,20 +1,16 @@
# correlateRC.py gcd,ibex,aes,jpeg,chameleon,riscv32i,chameleon_hier
# cap units pf/um
set_layer_rc -layer Metal1 -capacitance 3.49E-05 -resistance 0.135e-03
set_layer_rc -layer Metal2 -capacitance 1.81E-05 -resistance 0.103e-03
set_layer_rc -layer Metal3 -capacitance 2.14962E-04 -resistance 0.103e-03
set_layer_rc -layer Metal4 -capacitance 1.48128E-04 -resistance 0.103e-03
set_layer_rc -layer Metal5 -capacitance 1.54087E-04 -resistance 0.103e-03
set_layer_rc -layer TopMetal1 -capacitance 1.54087E-04 -resistance 0.021e-03
set_layer_rc -layer TopMetal2 -capacitance 1.54087E-04 -resistance 0.0145e-03
# end correlate
# correlation result (aes, gcd, ibex, riscv32i, spi)
# Metal1 capacitance fixed up from -1.1e-05 to 1e-10 as a minuscule positive value
set_layer_rc -layer Metal1 -resistance 8.54576E-03 -capacitance 1e-10
set_layer_rc -layer Metal2 -resistance 2.53519E-03 -capacitance 1.69121E-04
set_layer_rc -layer Metal3 -resistance 1.54329E-03 -capacitance 1.82832E-04
set_layer_rc -layer Metal4 -resistance 6.31424E-04 -capacitance 1.66454E-04
set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05
set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04
set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04

set_layer_rc -via Via1 -resistance 2.0E-3
set_layer_rc -via Via2 -resistance 2.0E-3
set_layer_rc -via Via3 -resistance 2.0E-3
set_layer_rc -via Via4 -resistance 2.0E-3
set_layer_rc -via TopVia1 -resistance 0.4E-3
set_layer_rc -via TopVia2 -resistance 0.22E-3

set_wire_rc -signal -layer Metal2
set_wire_rc -clock -layer Metal5
1 change: 1 addition & 0 deletions flow/util/correlateRC.py
Original file line number Diff line number Diff line change
Expand Up @@ -116,6 +116,7 @@ def makeDict():
else:
via_resist = float(match.group(2))
stack.append((name, is_routing, via_resist))
stack_line = line
continue

tokens = line.strip().split(",")
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