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updated asap7 platform config.mk to support multi vt #3223

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updated asap7 platform config.mk to support multi vt #3223

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12 changes: 3 additions & 9 deletions flow/designs/asap7/jpeg_lvt/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,6 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
export ABC_AREA = 1

export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_LVT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib

export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_L_220121a.gds
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_L_1x_220121a.lef

export CORE_UTILIZATION = 30
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 2
Expand All @@ -25,3 +16,6 @@ export PLACE_DENSITY = 0.60
export TNS_END_PERCENT = 100
export RECOVER_POWER = 100

export ASAP7_USE_VT = LVT


143 changes: 82 additions & 61 deletions flow/platforms/asap7/config.mk
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Expand Up @@ -80,94 +80,114 @@ export KLAYOUT_DRC_FILE = $(PLATFORM_DIR)/drc/asap7.lydrc
# OpenRCX extRules
export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules

# XS - defining function for using LVT
ifeq ($(ASAP7_USE_VT), LVT)
export VT_TAG = L
else ifeq ($(ASAP7_USE_VT), SLVT)
export VT_TAG = SL
else
# Default to RVT
export VT_TAG = R
endif

# PLACEHOLDER gets replaced with the appropriate VT tag in the following templates
export BC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib
export BC_CCS_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib
export WC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib
export TC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib
export BC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_nldm_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib
export BC_CCS_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_ccs_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib
export WC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_SS_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_SS_nldm_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_SS_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_SS_nldm_211120.lib.gz
export TC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_TT_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_TT_nldm_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_TT_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_TT_nldm_211120.lib.gz
export FILL_CELLS_T = FILLERxp5_ASAP7_75t_ \
FILLER_ASAP7_75t_ \
DECAPx1_ASAP7_75t_ \
DECAPx2_ASAP7_75t_ \
DECAPx4_ASAP7_75t_ \
DECAPx6_ASAP7_75t_ \
DECAPx10_ASAP7_75t_

# Default to RVT if unset
export VT_LIST = $(if $(strip $(ASAP7_USE_VT)), $(ASAP7_USE_VT), RVT)

# # The first VT in the ASAP7_USE_VT list is the primary VT. The others get added to OTHER_VT
export PRIMARY_VT = $(word 1, $(VT_LIST))
export PRIMARY_VT_TAG = $(strip $(patsubst %VT, %, $(PRIMARY_VT)))
export OTHER_VT = $(wordlist 2, $(words $(VT_LIST)), $(VT_LIST))

## Set cells based on the primary VT first
# Set the TIEHI/TIELO cells
# These are used in yosys synthesis to avoid logical 1/0's in the netlist
export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(VT_TAG) H
export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(VT_TAG) L
export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(PRIMARY_VT_TAG) H
export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(PRIMARY_VT_TAG) L

# Used in synthesis
export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(VT_TAG) A Y
export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) A Y

export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG)
export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG)

export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG)
export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG)

# Fill cells used in fill cell insertion
export FILL_CELLS ?= FILLERxp5_ASAP7_75t_$(VT_TAG) \
FILLER_ASAP7_75t_$(VT_TAG) \
DECAPx1_ASAP7_75t_$(VT_TAG) \
DECAPx2_ASAP7_75t_$(VT_TAG) \
DECAPx4_ASAP7_75t_$(VT_TAG) \
DECAPx6_ASAP7_75t_$(VT_TAG) \
DECAPx10_ASAP7_75t_$(VT_TAG)
export FILL_CELLS ?= $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))

export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(VT_TAG)
export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(PRIMARY_VT_TAG)

# GDS_FILES has to be = vs. ?= because GDS_FILES gets set in the ORFS Makefile
export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(VT_TAG)_220121a.gds \
$(ADDITIONAL_GDS)
export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_220121a.gds

export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(VT_TAG)_1x_220121a.lef
export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_1x_220121a.lef

# Yosys mapping files
export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(VT_TAG).v
export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(VT_TAG).v
export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(VT_TAG).v

export BC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib

export BC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_nldm_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib

export BC_CCS_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_ccs_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib \
$(BC_ADDITIONAL_LIBS)
export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(PRIMARY_VT_TAG).v
export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(PRIMARY_VT_TAG).v
export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(PRIMARY_VT_TAG).v

export BC_CCS_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib

export WC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib

export WC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_SS_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_SS_nldm_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_SS_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_SS_nldm_211120.lib.gz
export BC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))
export BC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_LIB_FILES_T))
export BC_CCS_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_LIB_FILES_T)) \
$(BC_ADDITIONAL_LIBS)
export BC_CCS_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))

export TC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib
export WC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))
export WC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_LIB_FILES_T))

export TC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_TT_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_TT_nldm_220122.lib.gz \
$(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_TT_nldm_211120.lib.gz \
$(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib \
$(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_TT_nldm_211120.lib.gz
export TC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))
export TC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_LIB_FILES_T))

ifeq ($(CLUSTER_FLOPS),1)
# Add the multi-bit FF for clustering. These are single corner libraries.
export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(VT_TAG)VT_TT_nldm_FAKE.lib \
$(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(VT_TAG)VT_TT_nldm_FAKE.lib
export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib \
$(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib

export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNH2V2X.lef \
$(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV2X.lef
export ADDITIONAL_SITES += asap7sc7p5t_pg
export GDS_ALLOW_EMPTY ?= DFFHQN[VH][24].*
endif

### Add additional files to the variables based on the OTHER_VT list
$(foreach vt_type,$(OTHER_VT),\
$(eval OTHER_VT_TAG = $(strip $(patsubst %VT, %, $(vt_type)))) \
$(eval ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(OTHER_VT_TAG)_1x_220121a.lef) \
$(eval BC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))) \
$(eval BC_CCS_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))) \
$(eval WC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))) \
$(eval TC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))) \
$(eval BC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_LIB_FILES_T))) \
$(eval BC_CCS_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_LIB_FILES_T))) \
$(eval WC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_LIB_FILES_T))) \
$(eval TC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_LIB_FILES_T))) \
$(eval GDS_FILES += $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(OTHER_VT_TAG)_220121a.gds) \
$(eval FILL_CELLS += $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))) \
)

# Dont use SC library based on CORNER selection
#
# BC - Best case, fastest
Expand All @@ -176,6 +196,7 @@ endif
export CORNER ?= BC
export LIB_FILES += $($(CORNER)_$(LIB_MODEL)_LIB_FILES)
export LIB_FILES += $(ADDITIONAL_LIBS)
export GDS_FILES += $(ADDITIONAL_GDS)
export DB_FILES += $(realpath $($(CORNER)_DB_FILES))
export TEMPERATURE = $($(CORNER)_TEMPERATURE)
export VOLTAGE = $($(CORNER)_VOLTAGE)
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