hercules_is_int gate level netlist support

flow/designs/rapidus2hp/hercules_is_int/config.mk

@@ -3,6 +3,11 @@ export PLATFORM               = rapidus2hp
 export DESIGN_NAME            = hercules_is_int
 
 export SRC_HOME = /platforms/Rapidus/designs/hercules_is_int
+
+ifeq ($(FLOW_VARIANT), gatelevel)
+  export SYNTH_NETLIST_FILES = $(SRC_HOME)/ca78_8t_postroute_0707.v
+endif
+
 export VERILOG_FILES          =	$(sort $(wildcard $(SRC_HOME)/hercules_issue/verilog/*.sv)) \
 	$(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \
 	$(sort $(wildcard $(SRC_HOME)/models/cells/generic/*.sv))
@@ -11,10 +16,7 @@ export VERILOG_INCLUDE_DIRS =  $(SRC_HOME)/hercules_issue/verilog \
 	$(SRC_HOME)/shared/verilog \
 	$(SRC_HOME)/models/cells/generic
 
-export VERILOG_DEFINES += 
-
-export ADDITIONAL_LEFS = 
-export ADDITIONAL_LIBS += 
+export VERILOG_DEFINES +=
 
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc
 

flow/designs/rapidus2hp/hercules_is_int/prects_prop.sdc

@@ -0,0 +1,14 @@
+#set sdc_version 2.1
+set sdc_version 1.4
+current_design hercules_is_int
+
+set clk_period 250
+
+set_max_fanout 32 [current_design]
+set_load 10 [all_outputs]
+set_max_capacitance 10 [all_inputs]
+
+create_clock -name "clk" -add -period $clk_period \
+  -waveform [list 0.0 [expr { 0.5 * $clk_period }]] [get_ports clk]
+
+set_propagated_clock [all_clocks]