Initial commit of hercules_idecode on Rapidus

flow/designs/rapidus2hp/hercules_idecode/config.mk

@@ -0,0 +1,23 @@
+export PLATFORM             = rapidus2hp
+
+export DESIGN_NAME          = hercules_idecode
+
+export SRC_HOME             = /platforms/Rapidus/designs/hercules_idecode
+export VERILOG_FILES        = $(sort $(wildcard $(SRC_HOME)/hercules_idecode/verilog/*.sv)) \
+	$(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \
+	$(sort $(wildcard $(SRC_HOME)/models/cells/generic/*.sv))
+
+export VERILOG_INCLUDE_DIRS =  $(SRC_HOME)/hercules_idecode/verilog \
+	$(SRC_HOME)/shared/verilog \
+	$(SRC_HOME)/models/cells/generic
+
+export SDC_FILE             = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc
+
+export SYNTH_HDL_FRONTEND  ?= slang
+export CORE_UTILIZATION     = 25
+export CORE_MARGIN          = 1
+export PLACE_DENSITY        = 0.50
+
+# a smoketest for this option, there are a
+# few last gasp iterations
+export SKIP_LAST_GASP      ?= 1

flow/designs/rapidus2hp/hercules_idecode/prects.sdc

@@ -0,0 +1,12 @@
+#set sdc_version 2.1
+set sdc_version 1.4
+current_design hercules_idecode
+
+set clk_period 250
+
+set_max_fanout 32 [current_design]
+set_load 10 [all_outputs]
+set_max_capacitance 10 [all_inputs]
+
+create_clock -name "clk" -add -period $clk_period \
+  -waveform [list 0.0 [expr 0.5*$clk_period]] [get_ports clk]

flow/designs/rapidus2hp/hercules_idecode/rules-base.json

@@ -0,0 +1,54 @@
+{
+    "synth__design__instance__area__stdcell": {
+        "value": 8741.01,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 1,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 17454,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 315828,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 27463,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 27463,
+        "compare": "<="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 0,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -79.25,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 17734,
+        "compare": "<="
+    },
+    "finish__timing__drv__setup_violation_count": {
+        "value": 13732,
+        "compare": "<="
+    },
+    "finish__timing__drv__hold_violation_count": {
+        "value": 149,
+        "compare": "<="
+    },
+    "finish__timing__wns_percent_delay": {
+        "value": -31.7,
+        "compare": ">="
+    }
+}

flow/scripts/synth_preamble.tcl

@@ -47,7 +47,7 @@ proc read_design_sources { } {
     # slang requires all files at once
     plugin -i slang
     yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \
-      --ignore-assertions --top $::env(DESIGN_NAME) \
+      --ignore-assertions --no-implicit-memories --top $::env(DESIGN_NAME) \
       {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}[env_var_or_empty VERILOG_DEFINES]
     # Workaround for yosys-slang#119
     setattr -unset init