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Merged
maliberty merged 5 commits into from
Aug 19, 2025
Merged

Tighten constraints for asap7, sky130hs designs #3401

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92e4ba7
Tighten constraints for asap7, sky130hs designs
povik Aug 14, 2025
e151e25
Iterate on tightening
povik Aug 18, 2025
5452922
Merge remote-tracking branch 'origin/master' into tighten-2508
povik Aug 18, 2025
33438a5
flow: update rules
github-actions[bot] Aug 18, 2025
92ad5bb
Update asap7/swerv_wrapper metrics after tightening
povik Aug 19, 2025
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2 changes: 1 addition & 1 deletion flow/designs/asap7/aes-block/constraint.sdc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 475
set clk_period 450
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/asap7/aes-mbff/constraint.sdc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 400
set clk_period 380
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/asap7/aes/constraint.sdc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 400
set clk_period 380
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/asap7/aes_lvt/constraint.sdc
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@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 400
set clk_period 360
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/asap7/cva6/constraint.sdc
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Expand Up @@ -3,7 +3,7 @@
set clk_name main_clk
set clk_port clk_i
set clk_ports_list [list $clk_port]
set clk_period 1200
set clk_period 1000
set input_delay 0.46
set output_delay 0.11
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
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4 changes: 2 additions & 2 deletions flow/designs/asap7/ethmac/config.mk
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Expand Up @@ -6,7 +6,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NIC
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export ABC_AREA = 1

export CORE_UTILIZATION = 40
export CORE_UTILIZATION = 60
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 2
export PLACE_DENSITY = 0.60
export PLACE_DENSITY = 0.75

@povik povik Aug 14, 2025

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I've checked ethmac does complete with an even higher density of 0.85 so there's margin.

2 changes: 1 addition & 1 deletion flow/designs/asap7/ibex/constraint.sdc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name core_clock
set clk_port_name clk_i
set clk_period 1260
set clk_period 1000
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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4 changes: 2 additions & 2 deletions flow/designs/asap7/ibex/rules-base.json
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Expand Up @@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -75.22,
"value": -212.68,
"compare": ">="
},
"finish__design__instance__area": {
Expand All @@ -64,7 +64,7 @@
"compare": "<="
},
"finish__timing__wns_percent_delay": {
"value": -11.43,
"value": -30.27,
"compare": ">="
}
}
4 changes: 2 additions & 2 deletions flow/designs/asap7/jpeg/config.mk
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Expand Up @@ -8,10 +8,10 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
export ABC_AREA = 1

export CORE_UTILIZATION = 30
export CORE_UTILIZATION = 70
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 2
export PLACE_DENSITY = 0.60
export PLACE_DENSITY = 0.75

export TNS_END_PERCENT = 100
export EQUIVALENCE_CHECK ?= 1
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2 changes: 1 addition & 1 deletion flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
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Expand Up @@ -2,7 +2,7 @@ current_design jpeg_encoder

set clk_name clk
set clk_port_name clk
set clk_period 900
set clk_period 680
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ current_design jpeg_encoder

set clk_name clk
set clk_port_name clk
set clk_period 1100
set clk_period 600
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/asap7/mock-alu/constraints.sdc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name clock
set clk_port_name clock
set clk_period 100
set clk_period 300
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/asap7/riscv32i/constraint.sdc
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Expand Up @@ -2,7 +2,7 @@ current_design riscv_top

set clk_name clk
set clk_port_name clk
set clk_period 1260
set clk_period 1000
set clk_io_pct 0.125

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/asap7/swerv_wrapper/constraint.sdc
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ current_design swerv_wrapper

set clk_name core_clock
set clk_port_name clk
set clk_period 2500
set clk_period 1600
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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10 changes: 5 additions & 5 deletions flow/designs/asap7/swerv_wrapper/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
"compare": "<="
},
"detailedroute__route__wirelength": {
"value": 1867701,
"value": 1692500,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -48,23 +48,23 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": 0.0,
"value": -359.45,
"compare": ">="
},
"finish__design__instance__area": {
"value": 56945,
"value": 56888,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
"value": 7294,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
"value": 286,
"value": 1245,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
"value": -10.0,
"value": -24.59,
"compare": ">="
}
}
2 changes: 1 addition & 1 deletion flow/designs/asap7/uart/constraint.sdc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 300
set clk_period 270
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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4 changes: 2 additions & 2 deletions flow/designs/asap7/uart/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -48,15 +48,15 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -20.24,
"value": -42.58,
"compare": ">="
},
"finish__design__instance__area": {
"value": 103,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
"value": 36,
"value": 79,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
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2 changes: 1 addition & 1 deletion flow/designs/sky130hs/aes/constraint.sdc
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ current_design aes_cipher_top

set clk_name clk
set clk_port_name clk
set clk_period 3.1
set clk_period 2.8
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/sky130hs/gcd/constraint.sdc
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Expand Up @@ -2,7 +2,7 @@ current_design gcd

set clk_name core_clock
set clk_port_name clk
set clk_period 2.2
set clk_period 1.9
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/sky130hs/ibex/constraint.sdc
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Expand Up @@ -2,7 +2,7 @@ current_design ibex_core

set clk_name core_clock
set clk_port_name clk_i
set clk_period 9.0
set clk_period 7.0
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/sky130hs/ibex/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -0.19,
"value": -0.56,
"compare": ">="
},
"finish__design__instance__area": {
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2 changes: 1 addition & 1 deletion flow/designs/sky130hs/jpeg/constraint.sdc
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ current_design jpeg_encoder

set clk_name clk
set clk_port_name clk
set clk_period 6.0
set clk_period 4.0
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/sky130hs/jpeg/rules-base.json
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Expand Up @@ -28,7 +28,7 @@
"compare": "<="
},
"globalroute__antenna_diodes_count": {
"value": 87,
"value": 336,
"compare": "<="
},
"detailedroute__route__wirelength": {
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2 changes: 1 addition & 1 deletion flow/designs/sky130hs/riscv32i/constraint.sdc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 5.2
set clk_period 4.8
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/sky130hs/riscv32i/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -0.21,
"value": -0.48,
"compare": ">="
},
"finish__design__instance__area": {
Expand Down