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2 changes: 1 addition & 1 deletion .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
url = ../../The-OpenROAD-Project/yosys.git
[submodule "tools/OpenROAD"]
path = tools/OpenROAD
url = ../OpenROAD.git
url = https://github.com/The-OpenROAD-Project/OpenROAD.git

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Seems unrelated

[submodule "tools/yosys-slang"]
path = tools/yosys-slang
url = https://github.com/povik/yosys-slang.git
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5 changes: 3 additions & 2 deletions flow/designs/src/chameleon/IPs/WDT32.v
Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,9 @@ module WDT32 (
end

reg wden_p;
always @(posedge clk)
wden_p <= WDEN;
always @(posedge clk or posedge rst)
if (rst) wden_p <= 1'b0;
else wden_p <= WDEN;
Comment on lines +43 to +45

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high

The addition of the asynchronous reset to wden_p correctly addresses the X-propagation issue during simulation. However, the same IP module is duplicated at flow/designs/src/chameleon_hier/rtl/IPs/WDT32.v and remains unpatched in this pull request. To ensure consistency across the repository and prevent simulation/synthesis mismatches in designs using the hierarchical path, this fix should be applied to that file as well.


always @(posedge clk or posedge rst)
begin
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5 changes: 3 additions & 2 deletions flow/designs/src/chameleon_hier/rtl/IPs/WDT32.v
Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,9 @@ module WDT32 (
end

reg wden_p;
always @(posedge clk)
wden_p <= WDEN;
always @(posedge clk or posedge rst)
if (rst) wden_p <= 1'b0;
else wden_p <= WDEN;

always @(posedge clk or posedge rst)
begin
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2 changes: 1 addition & 1 deletion tools/OpenROAD
Submodule OpenROAD updated 366 files