gt2n: add 2nm BSPDN platform with gcd and aes designs

.gitignore

@@ -63,6 +63,7 @@ flow/platforms/*
 !flow/platforms/sky130io
 !flow/platforms/sky130ram
 !flow/platforms/gf180
+!flow/platforms/gt2n
 flow/private
 
 # network

flow/designs/gt2n/aes/config.mk

@@ -0,0 +1,24 @@
+export DESIGN_NICKNAME = aes
+export DESIGN_NAME     = aes_cipher_top
+export PLATFORM        = gt2n
+
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
+export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+# AES is bigger than gcd; give the floorplan more room.
+export CORE_UTILIZATION       = 30
+export CORE_ASPECT_RATIO      = 1
+export CORE_MARGIN            = 2
+export PLACE_DENSITY_LB_ADDON = 0.20
+
+export TNS_END_PERCENT = 100
+# workaround for high congestion in post-grt repair (matches nangate45/aes)
+export SKIP_INCREMENTAL_REPAIR = 1
+
+export SWAP_ARITH_OPERATORS = 1
+export OPENROAD_HIERARCHICAL = 1
+
+# Highest layer aes actually routes on (M11-M13 carry no wire). Capping here
+# instead of the platform M13 top shrinks the detailed-route grid, vias, and
+# DRC. See platforms/gt2n/config.mk.
+export MAX_ROUTING_LAYER = M10

flow/designs/gt2n/aes/constraint.sdc

@@ -0,0 +1,17 @@
+current_design aes_cipher_top
+
+set clk_name clk
+set clk_port_name clk
+# GT2N lib uses time_unit = 1 ps. 500 ps -> 2 GHz target; first-pass
+# loose, can tighten once routing is clean.
+set clk_period 500
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/designs/gt2n/aes/rules-base.json

@@ -0,0 +1,112 @@
+{
+    "synth__canonical_netlist__hash": {
+        "value": "e9426c391e35d86c9f9023e814fd4826714b89b5",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "93f9e9316090c4b4b44bf35599036a9c5cdfe109",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__design__instance__area__stdcell": {
+        "value": 492.0,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 1,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 564,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 20700,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 1800,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 1800,
+        "compare": "<="
+    },
+    "cts__timing__setup__ws": {
+        "value": -25.0,
+        "compare": ">="
+    },
+    "cts__timing__setup__tns": {
+        "value": -100.0,
+        "compare": ">="
+    },
+    "cts__timing__hold__ws": {
+        "value": -25.0,
+        "compare": ">="
+    },
+    "cts__timing__hold__tns": {
+        "value": -100.0,
+        "compare": ">="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "globalroute__timing__setup__ws": {
+        "value": -75.2,
+        "compare": ">="
+    },
+    "globalroute__timing__setup__tns": {
+        "value": -585.0,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__ws": {
+        "value": -41.2,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__tns": {
+        "value": -1220.0,
+        "compare": ">="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 42394,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -75.2,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -585.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
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+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -1220.0,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 1636,
+        "compare": "<="
+    }
+}

flow/designs/gt2n/gcd/config.mk

@@ -0,0 +1,16 @@
+export DESIGN_NICKNAME = gcd
+export DESIGN_NAME     = gcd
+export PLATFORM        = gt2n
+
+export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
+export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
+
+export CORE_UTILIZATION   = 25
+export CORE_MARGIN        = 0.5
+export PLACE_DENSITY      = 0.35
+export TNS_END_PERCENT    = 100
+
+# Highest layer gcd actually routes on (M6-M13 carry no wire). Capping here
+# instead of the platform M13 top shrinks the detailed-route grid, vias, and
+# DRC. See platforms/gt2n/config.mk.
+export MAX_ROUTING_LAYER  = M5

flow/designs/gt2n/gcd/constraint.sdc

@@ -0,0 +1,17 @@
+current_design gcd
+
+set clk_name core_clock
+set clk_port_name clk
+# 500 ps clock (2 GHz) — modest target; lib path delays grow once realistic
+# wire RC kicks in. Tighten once a clean run lands.
+set clk_period 500
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/designs/gt2n/gcd/rules-base.json

@@ -0,0 +1,112 @@
+{
+    "synth__canonical_netlist__hash": {
+        "value": "94435b2c79066c9133b4aed43b6f5abf1ec21003",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "102bf37d6da7bc1aa234e916ebbf91984197836d",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__design__instance__area__stdcell": {
+        "value": 18.8,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 1,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 22,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 877,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 76,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 76,
+        "compare": "<="
+    },
+    "cts__timing__setup__ws": {
+        "value": -25.0,
+        "compare": ">="
+    },
+    "cts__timing__setup__tns": {
+        "value": -100.0,
+        "compare": ">="
+    },
+    "cts__timing__hold__ws": {
+        "value": -25.0,
+        "compare": ">="
+    },
+    "cts__timing__hold__tns": {
+        "value": -100.0,
+        "compare": ">="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "globalroute__timing__setup__ws": {
+        "value": -25.0,
+        "compare": ">="
+    },
+    "globalroute__timing__setup__tns": {
+        "value": -100.0,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__ws": {
+        "value": -25.0,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__tns": {
+        "value": -100.0,
+        "compare": ">="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 848,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -25.0,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -100.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
+        "value": -25.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -100.0,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 73,
+        "compare": "<="
+    }
+}

flow/designs/gt2n/jpeg/config.mk

@@ -0,0 +1,21 @@
+export DESIGN_NICKNAME = jpeg
+export DESIGN_NAME     = jpeg_encoder
+export PLATFORM        = gt2n
+
+export VERILOG_FILES        = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
+export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
+export SDC_FILE             = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export ABC_AREA = 1
+
+# Floorplan: jpeg_encoder is larger than aes; start conservative.
+export CORE_UTILIZATION       = 40
+export CORE_ASPECT_RATIO      = 1
+export CORE_MARGIN            = 2
+export PLACE_DENSITY_LB_ADDON = 0.20
+export TNS_END_PERCENT        = 100
+
+# Highest layer jpeg actually routes on (M10-M13 carry no wire). Capping here
+# instead of the platform M13 top shrinks the detailed-route grid, vias, and
+# DRC. See platforms/gt2n/config.mk.
+export MAX_ROUTING_LAYER      = M9

flow/designs/gt2n/jpeg/constraint.sdc

@@ -0,0 +1,16 @@
+current_design jpeg_encoder
+
+set clk_name clk
+set clk_port_name clk
+# GT2N lib uses time_unit = 1 ps. 1500 ps -> 667 MHz. Loose first-pass
+# target with the analytical-RC stand-in -- tighten once the optimize-ppa
+# loop has the baseline period_min.
+set clk_period 1000
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]