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flow: log_cmd the unlogged synth and load steps for timing #4292

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flow: log_cmd the unlogged synth and load steps for timing #4292

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flow: log_cmd the unlogged synth and load steps for timing
oharboe Jun 14, 2026
e9ee6f9
flow: log_cmd read_lef inside load_design, not the whole proc
oharboe Jun 14, 2026
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8 changes: 4 additions & 4 deletions flow/scripts/load.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -16,14 +16,14 @@ proc load_design { design_file sdc_file } {
# Read design files
set ext [file extension $design_file]
if { $ext == ".v" } {
read_lef $::env(TECH_LEF)
read_lef $::env(SC_LEF)
log_cmd read_lef $::env(TECH_LEF)
log_cmd read_lef $::env(SC_LEF)
if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } {
foreach lef $::env(ADDITIONAL_LEFS) {
read_lef $lef
log_cmd read_lef $lef
}
}
read_verilog $::env(RESULTS_DIR)/$design_file
log_cmd read_verilog $::env(RESULTS_DIR)/$design_file

@gemini-code-assist gemini-code-assist Bot Jun 14, 2026

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medium

While wrapping read_verilog in log_cmd is a great improvement, the read_lef commands in load_design (lines 19, 20, and 23) are still not logged. Sourcing LEF files can take a significant amount of time, so wrapping them in log_cmd inside load_design would provide complete visibility without needing to wrap the entire load_design procedure in synth_odb.tcl (which causes nested logging).

log_cmd link_design {*}[hier_options] $::env(DESIGN_NAME)
} elseif { $ext == ".odb" } {
log_cmd read_db {*}[hier_options] $::env(RESULTS_DIR)/$design_file
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