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Merged
maliberty merged 10 commits into from
Jun 17, 2026
Merged

flow: Use Virtual Clocks for IO Delays #4294

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732bf73
flow: Use virtual clocks for IO delays
jhkim-pii Jun 15, 2026
a6e23b0
flow: Update CI metric thresholds
jhkim-pii Jun 15, 2026
5511fcc
flow: Tune IO clock latency estimates
jhkim-pii Jun 15, 2026
297ca57
flow: Update CI metric thresholds
jhkim-pii Jun 15, 2026
cb16bc6
flow: Bump OpenROAD for CTS virtual clock latency fix
jhkim-pii Jun 17, 2026
3cce3ab
Merge remote-tracking branch 'origin/master' into secure-fix-cts-prop…
jhkim-pii Jun 17, 2026
57543e8
test: Rebase public flow metrics
jhkim-pii Jun 17, 2026
49a4304
test: Rebase public flow rules
jhkim-pii Jun 17, 2026
3178331
test: Rebase gf12 ariane metrics
jhkim-pii Jun 17, 2026
a7d79fb
test: Trigger public CI
jhkim-pii Jun 17, 2026
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28 changes: 14 additions & 14 deletions flow/designs/asap7/aes-block/rules-base.json
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"synth__canonical_netlist__hash": {
"value": "83fdb355d67936eac58202298e680864403e2e7c",
"value": "3fc8a6d24fdb16116484d2eed15ff2dbe4531126",
"compare": "==",
"level": "warning"
},
Expand All @@ -10,39 +10,39 @@
"level": "warning"
},
"synth__design__instance__area__stdcell": {
"value": 1930.0,
"value": 631.0,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 6699,
"value": 6705,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 9621,
"value": 10214,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 837,
"value": 888,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 837,
"value": 888,
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -89.2,
"value": -84.1,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -3220.0,
"value": -4320.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -58,11 +58,11 @@
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -22.5,
"value": -31.1,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -90.0,
"value": -174.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand All @@ -74,7 +74,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 49870,
"value": 50261,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -90,11 +90,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -31.5,
"value": -56.6,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -123.0,
"value": -1520.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand All @@ -106,7 +106,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 6742,
"value": 6750,
"compare": "<="
}
}
26 changes: 13 additions & 13 deletions flow/designs/asap7/aes-mbff/rules-base.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,35 +14,35 @@
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"value": 2,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 1898,
"value": 1897,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 18142,
"value": 18134,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 1578,
"value": 1577,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 1578,
"value": 1577,
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -21.6,
"value": -20.8,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -78.6,
"value": -77.8,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -58,11 +58,11 @@
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -19.5,
"value": -19.0,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -76.5,
"value": -76.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand All @@ -74,7 +74,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 68982,
"value": 69120,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -90,11 +90,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -19.0,
"value": -20.8,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -76.0,
"value": -77.8,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand All @@ -106,7 +106,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 1947,
"value": 1942,
"compare": "<="
}
}
8 changes: 6 additions & 2 deletions flow/designs/asap7/aes/constraint.sdc
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,12 @@ set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]

create_clock -name $clk_name -period $clk_period $clk_port
set clk_io_name vclk_$clk_name
create_clock -name $clk_io_name -period $clk_period
set_clock_latency 77.930 [get_clocks $clk_name]
set_clock_latency 77.930 [get_clocks $clk_io_name]

set non_clock_inputs [all_inputs -no_clocks]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]
28 changes: 14 additions & 14 deletions flow/designs/asap7/aes/rules-base.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,39 +10,39 @@
"level": "warning"
},
"synth__design__instance__area__stdcell": {
"value": 1780.0,
"value": 1610.0,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"value": 2,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 1849,
"value": 1614,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 17477,
"value": 14476,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 1520,
"value": 1259,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 1520,
"value": 1259,
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -19.0,
"value": -28.9,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -76.0,
"value": -119.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -58,11 +58,11 @@
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -19.5,
"value": -28.0,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -169.0,
"value": -164.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand All @@ -74,7 +74,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 60637,
"value": 57961,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -90,11 +90,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -20.8,
"value": -24.2,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -77.8,
"value": -87.7,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand All @@ -106,7 +106,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 1884,
"value": 1664,
"compare": "<="
}
}
30 changes: 21 additions & 9 deletions flow/designs/asap7/ethmac/constraint.sdc
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,29 +3,41 @@ set clk_period 1000
set clk_io_pct 0.2
set clk_port [get_ports $top_clk_name]
create_clock -name $top_clk_name -period $clk_period $clk_port
set top_io_clk_name vclk_$top_clk_name
create_clock -name $top_io_clk_name -period $clk_period
set_clock_latency 229.195 [get_clocks $top_clk_name]
set_clock_latency 229.195 [get_clocks $top_io_clk_name]
set non_clock_inputs [all_inputs -no_clocks]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name [all_outputs]

set tx_clk_name mtx_clk_pad_i
set tx_clk_port [get_ports $tx_clk_name]
set tx_clk_period 300
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
set tx_io_clk_name vclk_$tx_clk_name
create_clock -name $tx_io_clk_name -period $tx_clk_period
set_clock_latency 55.660 [get_clocks $tx_clk_name]
set_clock_latency 55.660 [get_clocks $tx_io_clk_name]
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name $mtx_non_clock_inputs
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name [all_outputs]

set rx_clk_name mrx_clk_pad_i
set rx_clk_port [get_ports $rx_clk_name]
set rx_clk_period 300
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
set rx_io_clk_name vclk_$rx_clk_name
create_clock -name $rx_io_clk_name -period $rx_clk_period
set_clock_latency 76.515 [get_clocks $rx_clk_name]
set_clock_latency 76.515 [get_clocks $rx_io_clk_name]
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name $mrx_non_clock_inputs
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name [all_outputs]

set_clock_groups -name core_clock -logically_exclusive \
-group [get_clocks $top_clk_name] \
-group [get_clocks $tx_clk_name] \
-group [get_clocks $rx_clk_name]
-group [concat [get_clocks $top_clk_name] [get_clocks $top_io_clk_name]] \
-group [concat [get_clocks $tx_clk_name] [get_clocks $tx_io_clk_name]] \
-group [concat [get_clocks $rx_clk_name] [get_clocks $rx_io_clk_name]]

set_max_fanout 10 [current_design]
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