diff --git a/flow/designs/asap7/rcx-fanout-1/config.mk b/flow/designs/asap7/rcx-fanout-1/config.mk new file mode 100644 index 0000000000..730f016392 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-1/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = asap7 +export DESIGN_NAME = fanout_1 +export DESIGN_NICKNAME = rcx-fanout-1 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_1.v +export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-1/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-1/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 1.0 1.0 149.0 11.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/asap7/rcx-fanout-1/constraint.sdc b/flow/designs/asap7/rcx-fanout-1/constraint.sdc new file mode 100644 index 0000000000..6545a820fd --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-1/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_1 + +set clk_period 250 +create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs] +set_max_delay 200 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/asap7/rcx-fanout-1/io.tcl b/flow/designs/asap7/rcx-fanout-1/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-1/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/asap7/rcx-fanout-128/config.mk b/flow/designs/asap7/rcx-fanout-128/config.mk new file mode 100644 index 0000000000..72c66caf7c --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-128/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = asap7 +export DESIGN_NAME = fanout_128 +export DESIGN_NICKNAME = rcx-fanout-128 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_128.v +export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-128/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-128/io.tcl + +export DIE_AREA = 0 0 264.0 19.8 +export CORE_AREA = 1.0 1.0 263.0 18.8 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/asap7/rcx-fanout-128/constraint.sdc b/flow/designs/asap7/rcx-fanout-128/constraint.sdc new file mode 100644 index 0000000000..0d9ada450d --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-128/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_128 + +set clk_period 250 +create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs] +set_max_delay 200 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/asap7/rcx-fanout-128/io.tcl b/flow/designs/asap7/rcx-fanout-128/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-128/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/asap7/rcx-fanout-16/config.mk b/flow/designs/asap7/rcx-fanout-16/config.mk new file mode 100644 index 0000000000..88b63acc5c --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-16/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = asap7 +export DESIGN_NAME = fanout_16 +export DESIGN_NICKNAME = rcx-fanout-16 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_16.v +export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-16/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-16/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 1.0 1.0 149.0 11.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/asap7/rcx-fanout-16/constraint.sdc b/flow/designs/asap7/rcx-fanout-16/constraint.sdc new file mode 100644 index 0000000000..67defe1e49 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-16/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_16 + +set clk_period 250 +create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs] +set_max_delay 200 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/asap7/rcx-fanout-16/io.tcl b/flow/designs/asap7/rcx-fanout-16/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-16/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/asap7/rcx-fanout-2/config.mk b/flow/designs/asap7/rcx-fanout-2/config.mk new file mode 100644 index 0000000000..9fff487f58 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-2/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = asap7 +export DESIGN_NAME = fanout_2 +export DESIGN_NICKNAME = rcx-fanout-2 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_2.v +export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-2/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-2/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 1.0 1.0 149.0 11.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/asap7/rcx-fanout-2/constraint.sdc b/flow/designs/asap7/rcx-fanout-2/constraint.sdc new file mode 100644 index 0000000000..d6ad7bfc48 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-2/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_2 + +set clk_period 250 +create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs] +set_max_delay 200 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/asap7/rcx-fanout-2/io.tcl b/flow/designs/asap7/rcx-fanout-2/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-2/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/asap7/rcx-fanout-32/config.mk b/flow/designs/asap7/rcx-fanout-32/config.mk new file mode 100644 index 0000000000..631b81db77 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-32/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = asap7 +export DESIGN_NAME = fanout_32 +export DESIGN_NICKNAME = rcx-fanout-32 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_32.v +export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-32/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-32/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 1.0 1.0 149.0 11.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/asap7/rcx-fanout-32/constraint.sdc b/flow/designs/asap7/rcx-fanout-32/constraint.sdc new file mode 100644 index 0000000000..f8562df041 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-32/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_32 + +set clk_period 250 +create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs] +set_max_delay 200 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/asap7/rcx-fanout-32/io.tcl b/flow/designs/asap7/rcx-fanout-32/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-32/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/asap7/rcx-fanout-4/config.mk b/flow/designs/asap7/rcx-fanout-4/config.mk new file mode 100644 index 0000000000..398533de02 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-4/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = asap7 +export DESIGN_NAME = fanout_4 +export DESIGN_NICKNAME = rcx-fanout-4 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_4.v +export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-4/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-4/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 1.0 1.0 149.0 11.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/asap7/rcx-fanout-4/constraint.sdc b/flow/designs/asap7/rcx-fanout-4/constraint.sdc new file mode 100644 index 0000000000..d3f3d94eb7 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-4/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_4 + +set clk_period 250 +create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs] +set_max_delay 200 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/asap7/rcx-fanout-4/io.tcl b/flow/designs/asap7/rcx-fanout-4/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-4/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/asap7/rcx-fanout-64/config.mk b/flow/designs/asap7/rcx-fanout-64/config.mk new file mode 100644 index 0000000000..0f8d202b60 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-64/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = asap7 +export DESIGN_NAME = fanout_64 +export DESIGN_NICKNAME = rcx-fanout-64 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_64.v +export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-64/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-64/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 1.0 1.0 149.0 11.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/asap7/rcx-fanout-64/constraint.sdc b/flow/designs/asap7/rcx-fanout-64/constraint.sdc new file mode 100644 index 0000000000..badc7da084 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-64/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_64 + +set clk_period 250 +create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs] +set_max_delay 200 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/asap7/rcx-fanout-64/io.tcl b/flow/designs/asap7/rcx-fanout-64/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-64/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/asap7/rcx-fanout-8/config.mk b/flow/designs/asap7/rcx-fanout-8/config.mk new file mode 100644 index 0000000000..a9e330c16f --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-8/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = asap7 +export DESIGN_NAME = fanout_8 +export DESIGN_NICKNAME = rcx-fanout-8 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_8.v +export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-8/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-8/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 1.0 1.0 149.0 11.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/asap7/rcx-fanout-8/constraint.sdc b/flow/designs/asap7/rcx-fanout-8/constraint.sdc new file mode 100644 index 0000000000..41e4510dfb --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-8/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_8 + +set clk_period 250 +create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs] +set_max_delay 200 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/asap7/rcx-fanout-8/io.tcl b/flow/designs/asap7/rcx-fanout-8/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/asap7/rcx-fanout-8/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/gt2n/rcx-fanout-1/config.mk b/flow/designs/gt2n/rcx-fanout-1/config.mk new file mode 100644 index 0000000000..38f8693295 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-1/config.mk @@ -0,0 +1,16 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = gt2n +export DESIGN_NAME = fanout_1 +export DESIGN_NICKNAME = rcx-fanout-1 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_1.v +export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-1/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-1/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 2.0 2.0 148.0 10.0 +export PLACE_DENSITY = 0.10 +export MAX_ROUTING_LAYER = M5 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/gt2n/rcx-fanout-1/constraint.sdc b/flow/designs/gt2n/rcx-fanout-1/constraint.sdc new file mode 100644 index 0000000000..98cd0008b8 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-1/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_1 + +set clk_period 600 +create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs] +set_max_delay 480 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/gt2n/rcx-fanout-1/io.tcl b/flow/designs/gt2n/rcx-fanout-1/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-1/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/gt2n/rcx-fanout-128/config.mk b/flow/designs/gt2n/rcx-fanout-128/config.mk new file mode 100644 index 0000000000..0584ac7010 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-128/config.mk @@ -0,0 +1,16 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = gt2n +export DESIGN_NAME = fanout_128 +export DESIGN_NICKNAME = rcx-fanout-128 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_128.v +export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-128/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-128/io.tcl + +export DIE_AREA = 0 0 264.0 19.8 +export CORE_AREA = 2.0 2.0 262.0 17.8 +export PLACE_DENSITY = 0.10 +export MAX_ROUTING_LAYER = M5 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/gt2n/rcx-fanout-128/constraint.sdc b/flow/designs/gt2n/rcx-fanout-128/constraint.sdc new file mode 100644 index 0000000000..29a731d22c --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-128/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_128 + +set clk_period 600 +create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs] +set_max_delay 480 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/gt2n/rcx-fanout-128/io.tcl b/flow/designs/gt2n/rcx-fanout-128/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-128/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/gt2n/rcx-fanout-16/config.mk b/flow/designs/gt2n/rcx-fanout-16/config.mk new file mode 100644 index 0000000000..669f7dc3e5 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-16/config.mk @@ -0,0 +1,16 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = gt2n +export DESIGN_NAME = fanout_16 +export DESIGN_NICKNAME = rcx-fanout-16 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_16.v +export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-16/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-16/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 2.0 2.0 148.0 10.0 +export PLACE_DENSITY = 0.10 +export MAX_ROUTING_LAYER = M5 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/gt2n/rcx-fanout-16/constraint.sdc b/flow/designs/gt2n/rcx-fanout-16/constraint.sdc new file mode 100644 index 0000000000..6f47018769 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-16/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_16 + +set clk_period 600 +create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs] +set_max_delay 480 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/gt2n/rcx-fanout-16/io.tcl b/flow/designs/gt2n/rcx-fanout-16/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-16/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/gt2n/rcx-fanout-2/config.mk b/flow/designs/gt2n/rcx-fanout-2/config.mk new file mode 100644 index 0000000000..1a8f4f63bf --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-2/config.mk @@ -0,0 +1,16 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = gt2n +export DESIGN_NAME = fanout_2 +export DESIGN_NICKNAME = rcx-fanout-2 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_2.v +export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-2/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-2/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 2.0 2.0 148.0 10.0 +export PLACE_DENSITY = 0.10 +export MAX_ROUTING_LAYER = M5 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/gt2n/rcx-fanout-2/constraint.sdc b/flow/designs/gt2n/rcx-fanout-2/constraint.sdc new file mode 100644 index 0000000000..ea9f24866e --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-2/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_2 + +set clk_period 600 +create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs] +set_max_delay 480 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/gt2n/rcx-fanout-2/io.tcl b/flow/designs/gt2n/rcx-fanout-2/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-2/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/gt2n/rcx-fanout-32/config.mk b/flow/designs/gt2n/rcx-fanout-32/config.mk new file mode 100644 index 0000000000..49f9102f68 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-32/config.mk @@ -0,0 +1,16 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = gt2n +export DESIGN_NAME = fanout_32 +export DESIGN_NICKNAME = rcx-fanout-32 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_32.v +export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-32/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-32/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 2.0 2.0 148.0 10.0 +export PLACE_DENSITY = 0.10 +export MAX_ROUTING_LAYER = M5 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/gt2n/rcx-fanout-32/constraint.sdc b/flow/designs/gt2n/rcx-fanout-32/constraint.sdc new file mode 100644 index 0000000000..1a180be966 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-32/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_32 + +set clk_period 600 +create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs] +set_max_delay 480 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/gt2n/rcx-fanout-32/io.tcl b/flow/designs/gt2n/rcx-fanout-32/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-32/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/gt2n/rcx-fanout-4/config.mk b/flow/designs/gt2n/rcx-fanout-4/config.mk new file mode 100644 index 0000000000..7398721c13 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-4/config.mk @@ -0,0 +1,16 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = gt2n +export DESIGN_NAME = fanout_4 +export DESIGN_NICKNAME = rcx-fanout-4 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_4.v +export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-4/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-4/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 2.0 2.0 148.0 10.0 +export PLACE_DENSITY = 0.10 +export MAX_ROUTING_LAYER = M5 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/gt2n/rcx-fanout-4/constraint.sdc b/flow/designs/gt2n/rcx-fanout-4/constraint.sdc new file mode 100644 index 0000000000..409473e8d8 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-4/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_4 + +set clk_period 600 +create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs] +set_max_delay 480 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/gt2n/rcx-fanout-4/io.tcl b/flow/designs/gt2n/rcx-fanout-4/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-4/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/gt2n/rcx-fanout-64/config.mk b/flow/designs/gt2n/rcx-fanout-64/config.mk new file mode 100644 index 0000000000..6e2784bf9e --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-64/config.mk @@ -0,0 +1,16 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = gt2n +export DESIGN_NAME = fanout_64 +export DESIGN_NICKNAME = rcx-fanout-64 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_64.v +export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-64/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-64/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 2.0 2.0 148.0 10.0 +export PLACE_DENSITY = 0.10 +export MAX_ROUTING_LAYER = M5 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/gt2n/rcx-fanout-64/constraint.sdc b/flow/designs/gt2n/rcx-fanout-64/constraint.sdc new file mode 100644 index 0000000000..468b00e574 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-64/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_64 + +set clk_period 600 +create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs] +set_max_delay 480 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/gt2n/rcx-fanout-64/io.tcl b/flow/designs/gt2n/rcx-fanout-64/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-64/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/gt2n/rcx-fanout-8/config.mk b/flow/designs/gt2n/rcx-fanout-8/config.mk new file mode 100644 index 0000000000..11eb114e63 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-8/config.mk @@ -0,0 +1,16 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = gt2n +export DESIGN_NAME = fanout_8 +export DESIGN_NICKNAME = rcx-fanout-8 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_8.v +export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-8/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-8/io.tcl + +export DIE_AREA = 0 0 150.0 12.0 +export CORE_AREA = 2.0 2.0 148.0 10.0 +export PLACE_DENSITY = 0.10 +export MAX_ROUTING_LAYER = M5 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/gt2n/rcx-fanout-8/constraint.sdc b/flow/designs/gt2n/rcx-fanout-8/constraint.sdc new file mode 100644 index 0000000000..07aadc95eb --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-8/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_8 + +set clk_period 600 +create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs] +set_max_delay 480 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/gt2n/rcx-fanout-8/io.tcl b/flow/designs/gt2n/rcx-fanout-8/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/gt2n/rcx-fanout-8/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-1/config.mk b/flow/designs/ihp-sg13g2/rcx-fanout-1/config.mk new file mode 100644 index 0000000000..d719b57832 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-1/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = ihp-sg13g2 +export DESIGN_NAME = fanout_1 +export DESIGN_NICKNAME = rcx-fanout-1 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_1.v +export SDC_FILE = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-1/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-1/io.tcl + +export DIE_AREA = 0 0 500.0 160.0 +export CORE_AREA = 26.0 26.0 474.0 134.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-1/constraint.sdc b/flow/designs/ihp-sg13g2/rcx-fanout-1/constraint.sdc new file mode 100644 index 0000000000..1f3480abb3 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-1/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_1 + +set clk_period 6000 +create_clock -name clock -period 6000 -waveform [list 0 [expr 6000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 4800 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 4800 -from [all_registers] -to [all_outputs] +set_max_delay 4800 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-1/io.tcl b/flow/designs/ihp-sg13g2/rcx-fanout-1/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-1/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-128/config.mk b/flow/designs/ihp-sg13g2/rcx-fanout-128/config.mk new file mode 100644 index 0000000000..283a526f98 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-128/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = ihp-sg13g2 +export DESIGN_NAME = fanout_128 +export DESIGN_NICKNAME = rcx-fanout-128 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_128.v +export SDC_FILE = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-128/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-128/io.tcl + +export DIE_AREA = 0 0 776.0 198.0 +export CORE_AREA = 26.0 26.0 750.0 172.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-128/constraint.sdc b/flow/designs/ihp-sg13g2/rcx-fanout-128/constraint.sdc new file mode 100644 index 0000000000..6027d0985b --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-128/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_128 + +set clk_period 6000 +create_clock -name clock -period 6000 -waveform [list 0 [expr 6000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 4800 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 4800 -from [all_registers] -to [all_outputs] +set_max_delay 4800 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-128/io.tcl b/flow/designs/ihp-sg13g2/rcx-fanout-128/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-128/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-16/config.mk b/flow/designs/ihp-sg13g2/rcx-fanout-16/config.mk new file mode 100644 index 0000000000..005a4fc04f --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-16/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = ihp-sg13g2 +export DESIGN_NAME = fanout_16 +export DESIGN_NICKNAME = rcx-fanout-16 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_16.v +export SDC_FILE = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-16/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-16/io.tcl + +export DIE_AREA = 0 0 500.0 160.0 +export CORE_AREA = 26.0 26.0 474.0 134.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-16/constraint.sdc b/flow/designs/ihp-sg13g2/rcx-fanout-16/constraint.sdc new file mode 100644 index 0000000000..b12ad74ad7 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-16/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_16 + +set clk_period 6000 +create_clock -name clock -period 6000 -waveform [list 0 [expr 6000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 4800 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 4800 -from [all_registers] -to [all_outputs] +set_max_delay 4800 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-16/io.tcl b/flow/designs/ihp-sg13g2/rcx-fanout-16/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-16/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-2/config.mk b/flow/designs/ihp-sg13g2/rcx-fanout-2/config.mk new file mode 100644 index 0000000000..a032aa11a5 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-2/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = ihp-sg13g2 +export DESIGN_NAME = fanout_2 +export DESIGN_NICKNAME = rcx-fanout-2 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_2.v +export SDC_FILE = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-2/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-2/io.tcl + +export DIE_AREA = 0 0 500.0 160.0 +export CORE_AREA = 26.0 26.0 474.0 134.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-2/constraint.sdc b/flow/designs/ihp-sg13g2/rcx-fanout-2/constraint.sdc new file mode 100644 index 0000000000..bbd2ceea18 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-2/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_2 + +set clk_period 6000 +create_clock -name clock -period 6000 -waveform [list 0 [expr 6000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 4800 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 4800 -from [all_registers] -to [all_outputs] +set_max_delay 4800 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-2/io.tcl b/flow/designs/ihp-sg13g2/rcx-fanout-2/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-2/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-32/config.mk b/flow/designs/ihp-sg13g2/rcx-fanout-32/config.mk new file mode 100644 index 0000000000..a85c025569 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-32/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = ihp-sg13g2 +export DESIGN_NAME = fanout_32 +export DESIGN_NICKNAME = rcx-fanout-32 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_32.v +export SDC_FILE = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-32/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-32/io.tcl + +export DIE_AREA = 0 0 500.0 160.0 +export CORE_AREA = 26.0 26.0 474.0 134.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-32/constraint.sdc b/flow/designs/ihp-sg13g2/rcx-fanout-32/constraint.sdc new file mode 100644 index 0000000000..88b1f65c28 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-32/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_32 + +set clk_period 6000 +create_clock -name clock -period 6000 -waveform [list 0 [expr 6000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 4800 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 4800 -from [all_registers] -to [all_outputs] +set_max_delay 4800 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-32/io.tcl b/flow/designs/ihp-sg13g2/rcx-fanout-32/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-32/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-4/config.mk b/flow/designs/ihp-sg13g2/rcx-fanout-4/config.mk new file mode 100644 index 0000000000..9bbe6d34d8 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-4/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = ihp-sg13g2 +export DESIGN_NAME = fanout_4 +export DESIGN_NICKNAME = rcx-fanout-4 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_4.v +export SDC_FILE = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-4/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-4/io.tcl + +export DIE_AREA = 0 0 500.0 160.0 +export CORE_AREA = 26.0 26.0 474.0 134.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-4/constraint.sdc b/flow/designs/ihp-sg13g2/rcx-fanout-4/constraint.sdc new file mode 100644 index 0000000000..494c061748 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-4/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_4 + +set clk_period 6000 +create_clock -name clock -period 6000 -waveform [list 0 [expr 6000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 4800 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 4800 -from [all_registers] -to [all_outputs] +set_max_delay 4800 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-4/io.tcl b/flow/designs/ihp-sg13g2/rcx-fanout-4/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-4/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-64/config.mk b/flow/designs/ihp-sg13g2/rcx-fanout-64/config.mk new file mode 100644 index 0000000000..84ee0f2c7c --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-64/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = ihp-sg13g2 +export DESIGN_NAME = fanout_64 +export DESIGN_NICKNAME = rcx-fanout-64 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_64.v +export SDC_FILE = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-64/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-64/io.tcl + +export DIE_AREA = 0 0 500.0 160.0 +export CORE_AREA = 26.0 26.0 474.0 134.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-64/constraint.sdc b/flow/designs/ihp-sg13g2/rcx-fanout-64/constraint.sdc new file mode 100644 index 0000000000..2c868a5258 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-64/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_64 + +set clk_period 6000 +create_clock -name clock -period 6000 -waveform [list 0 [expr 6000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 4800 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 4800 -from [all_registers] -to [all_outputs] +set_max_delay 4800 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-64/io.tcl b/flow/designs/ihp-sg13g2/rcx-fanout-64/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-64/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-8/config.mk b/flow/designs/ihp-sg13g2/rcx-fanout-8/config.mk new file mode 100644 index 0000000000..eca80b061b --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-8/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = ihp-sg13g2 +export DESIGN_NAME = fanout_8 +export DESIGN_NICKNAME = rcx-fanout-8 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_8.v +export SDC_FILE = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-8/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/ihp-sg13g2/rcx-fanout-8/io.tcl + +export DIE_AREA = 0 0 500.0 160.0 +export CORE_AREA = 26.0 26.0 474.0 134.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-8/constraint.sdc b/flow/designs/ihp-sg13g2/rcx-fanout-8/constraint.sdc new file mode 100644 index 0000000000..1221f31c07 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-8/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_8 + +set clk_period 6000 +create_clock -name clock -period 6000 -waveform [list 0 [expr 6000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 4800 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 4800 -from [all_registers] -to [all_outputs] +set_max_delay 4800 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/ihp-sg13g2/rcx-fanout-8/io.tcl b/flow/designs/ihp-sg13g2/rcx-fanout-8/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/rcx-fanout-8/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/sky130hd/rcx-fanout-1/config.mk b/flow/designs/sky130hd/rcx-fanout-1/config.mk new file mode 100644 index 0000000000..3dc7afc43e --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-1/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = sky130hd +export DESIGN_NAME = fanout_1 +export DESIGN_NICKNAME = rcx-fanout-1 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_1.v +export SDC_FILE = $(DESIGN_HOME)/sky130hd/rcx-fanout-1/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/sky130hd/rcx-fanout-1/io.tcl + +export DIE_AREA = 0 0 500.0 140.0 +export CORE_AREA = 12.0 12.0 488.0 128.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/sky130hd/rcx-fanout-1/constraint.sdc b/flow/designs/sky130hd/rcx-fanout-1/constraint.sdc new file mode 100644 index 0000000000..5f2ac75bc8 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-1/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_1 + +set clk_period 8000 +create_clock -name clock -period 8000 -waveform [list 0 [expr 8000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 6400 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 6400 -from [all_registers] -to [all_outputs] +set_max_delay 6400 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/sky130hd/rcx-fanout-1/io.tcl b/flow/designs/sky130hd/rcx-fanout-1/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-1/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/sky130hd/rcx-fanout-128/config.mk b/flow/designs/sky130hd/rcx-fanout-128/config.mk new file mode 100644 index 0000000000..e65c7d03eb --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-128/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = sky130hd +export DESIGN_NAME = fanout_128 +export DESIGN_NICKNAME = rcx-fanout-128 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_128.v +export SDC_FILE = $(DESIGN_HOME)/sky130hd/rcx-fanout-128/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/sky130hd/rcx-fanout-128/io.tcl + +export DIE_AREA = 0 0 776.0 198.0 +export CORE_AREA = 12.0 12.0 764.0 186.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/sky130hd/rcx-fanout-128/constraint.sdc b/flow/designs/sky130hd/rcx-fanout-128/constraint.sdc new file mode 100644 index 0000000000..fef289be42 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-128/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_128 + +set clk_period 8000 +create_clock -name clock -period 8000 -waveform [list 0 [expr 8000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 6400 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 6400 -from [all_registers] -to [all_outputs] +set_max_delay 6400 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/sky130hd/rcx-fanout-128/io.tcl b/flow/designs/sky130hd/rcx-fanout-128/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-128/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/sky130hd/rcx-fanout-16/config.mk b/flow/designs/sky130hd/rcx-fanout-16/config.mk new file mode 100644 index 0000000000..334b096f24 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-16/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = sky130hd +export DESIGN_NAME = fanout_16 +export DESIGN_NICKNAME = rcx-fanout-16 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_16.v +export SDC_FILE = $(DESIGN_HOME)/sky130hd/rcx-fanout-16/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/sky130hd/rcx-fanout-16/io.tcl + +export DIE_AREA = 0 0 500.0 140.0 +export CORE_AREA = 12.0 12.0 488.0 128.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/sky130hd/rcx-fanout-16/constraint.sdc b/flow/designs/sky130hd/rcx-fanout-16/constraint.sdc new file mode 100644 index 0000000000..a94e64b9a8 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-16/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_16 + +set clk_period 8000 +create_clock -name clock -period 8000 -waveform [list 0 [expr 8000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 6400 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 6400 -from [all_registers] -to [all_outputs] +set_max_delay 6400 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/sky130hd/rcx-fanout-16/io.tcl b/flow/designs/sky130hd/rcx-fanout-16/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-16/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/sky130hd/rcx-fanout-2/config.mk b/flow/designs/sky130hd/rcx-fanout-2/config.mk new file mode 100644 index 0000000000..d022a39557 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-2/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = sky130hd +export DESIGN_NAME = fanout_2 +export DESIGN_NICKNAME = rcx-fanout-2 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_2.v +export SDC_FILE = $(DESIGN_HOME)/sky130hd/rcx-fanout-2/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/sky130hd/rcx-fanout-2/io.tcl + +export DIE_AREA = 0 0 500.0 140.0 +export CORE_AREA = 12.0 12.0 488.0 128.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/sky130hd/rcx-fanout-2/constraint.sdc b/flow/designs/sky130hd/rcx-fanout-2/constraint.sdc new file mode 100644 index 0000000000..7b6f462262 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-2/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_2 + +set clk_period 8000 +create_clock -name clock -period 8000 -waveform [list 0 [expr 8000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 6400 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 6400 -from [all_registers] -to [all_outputs] +set_max_delay 6400 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/sky130hd/rcx-fanout-2/io.tcl b/flow/designs/sky130hd/rcx-fanout-2/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-2/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/sky130hd/rcx-fanout-32/config.mk b/flow/designs/sky130hd/rcx-fanout-32/config.mk new file mode 100644 index 0000000000..5c06c94c2a --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-32/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = sky130hd +export DESIGN_NAME = fanout_32 +export DESIGN_NICKNAME = rcx-fanout-32 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_32.v +export SDC_FILE = $(DESIGN_HOME)/sky130hd/rcx-fanout-32/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/sky130hd/rcx-fanout-32/io.tcl + +export DIE_AREA = 0 0 500.0 140.0 +export CORE_AREA = 12.0 12.0 488.0 128.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/sky130hd/rcx-fanout-32/constraint.sdc b/flow/designs/sky130hd/rcx-fanout-32/constraint.sdc new file mode 100644 index 0000000000..977a629e03 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-32/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_32 + +set clk_period 8000 +create_clock -name clock -period 8000 -waveform [list 0 [expr 8000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 6400 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 6400 -from [all_registers] -to [all_outputs] +set_max_delay 6400 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/sky130hd/rcx-fanout-32/io.tcl b/flow/designs/sky130hd/rcx-fanout-32/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-32/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/sky130hd/rcx-fanout-4/config.mk b/flow/designs/sky130hd/rcx-fanout-4/config.mk new file mode 100644 index 0000000000..785f1c3936 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-4/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = sky130hd +export DESIGN_NAME = fanout_4 +export DESIGN_NICKNAME = rcx-fanout-4 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_4.v +export SDC_FILE = $(DESIGN_HOME)/sky130hd/rcx-fanout-4/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/sky130hd/rcx-fanout-4/io.tcl + +export DIE_AREA = 0 0 500.0 140.0 +export CORE_AREA = 12.0 12.0 488.0 128.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/sky130hd/rcx-fanout-4/constraint.sdc b/flow/designs/sky130hd/rcx-fanout-4/constraint.sdc new file mode 100644 index 0000000000..b4d6e39813 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-4/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_4 + +set clk_period 8000 +create_clock -name clock -period 8000 -waveform [list 0 [expr 8000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 6400 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 6400 -from [all_registers] -to [all_outputs] +set_max_delay 6400 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/sky130hd/rcx-fanout-4/io.tcl b/flow/designs/sky130hd/rcx-fanout-4/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-4/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/sky130hd/rcx-fanout-64/config.mk b/flow/designs/sky130hd/rcx-fanout-64/config.mk new file mode 100644 index 0000000000..956c23f133 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-64/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = sky130hd +export DESIGN_NAME = fanout_64 +export DESIGN_NICKNAME = rcx-fanout-64 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_64.v +export SDC_FILE = $(DESIGN_HOME)/sky130hd/rcx-fanout-64/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/sky130hd/rcx-fanout-64/io.tcl + +export DIE_AREA = 0 0 500.0 140.0 +export CORE_AREA = 12.0 12.0 488.0 128.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/sky130hd/rcx-fanout-64/constraint.sdc b/flow/designs/sky130hd/rcx-fanout-64/constraint.sdc new file mode 100644 index 0000000000..34de8f6b3d --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-64/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_64 + +set clk_period 8000 +create_clock -name clock -period 8000 -waveform [list 0 [expr 8000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 6400 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 6400 -from [all_registers] -to [all_outputs] +set_max_delay 6400 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/sky130hd/rcx-fanout-64/io.tcl b/flow/designs/sky130hd/rcx-fanout-64/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-64/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/sky130hd/rcx-fanout-8/config.mk b/flow/designs/sky130hd/rcx-fanout-8/config.mk new file mode 100644 index 0000000000..fb04ce3e22 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-8/config.mk @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = sky130hd +export DESIGN_NAME = fanout_8 +export DESIGN_NICKNAME = rcx-fanout-8 + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_8.v +export SDC_FILE = $(DESIGN_HOME)/sky130hd/rcx-fanout-8/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/sky130hd/rcx-fanout-8/io.tcl + +export DIE_AREA = 0 0 500.0 140.0 +export CORE_AREA = 12.0 12.0 488.0 128.0 +export PLACE_DENSITY = 0.10 + +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/sky130hd/rcx-fanout-8/constraint.sdc b/flow/designs/sky130hd/rcx-fanout-8/constraint.sdc new file mode 100644 index 0000000000..21ca09441a --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-8/constraint.sdc @@ -0,0 +1,15 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_8 + +set clk_period 8000 +create_clock -name clock -period 8000 -waveform [list 0 [expr 8000 / 2]] [get_ports clock] + +if {[llength [get_ports -quiet reset]] == 1} { + set_false_path -from [get_ports reset] +} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency 6400 -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency 6400 -from [all_registers] -to [all_outputs] +set_max_delay 6400 -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] diff --git a/flow/designs/sky130hd/rcx-fanout-8/io.tcl b/flow/designs/sky130hd/rcx-fanout-8/io.tcl new file mode 100644 index 0000000000..6af09264d0 --- /dev/null +++ b/flow/designs/sky130hd/rcx-fanout-8/io.tcl @@ -0,0 +1,5 @@ +# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* diff --git a/flow/designs/src/rcx-fanout/fanout_1.v b/flow/designs/src/rcx-fanout/fanout_1.v new file mode 100644 index 0000000000..a813cc07cc --- /dev/null +++ b/flow/designs/src/rcx-fanout/fanout_1.v @@ -0,0 +1,30 @@ +// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to 1 capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_1 ( + input wire clock, + input wire reset, + input wire din, + input wire [0:0] perturb, + output reg [0:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {1{1'b0}}; + else begin + for (i = 0; i < 1; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule diff --git a/flow/designs/src/rcx-fanout/fanout_128.v b/flow/designs/src/rcx-fanout/fanout_128.v new file mode 100644 index 0000000000..6587ef4bb9 --- /dev/null +++ b/flow/designs/src/rcx-fanout/fanout_128.v @@ -0,0 +1,30 @@ +// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to 128 capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_128 ( + input wire clock, + input wire reset, + input wire din, + input wire [127:0] perturb, + output reg [127:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {128{1'b0}}; + else begin + for (i = 0; i < 128; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule diff --git a/flow/designs/src/rcx-fanout/fanout_16.v b/flow/designs/src/rcx-fanout/fanout_16.v new file mode 100644 index 0000000000..6676d7234d --- /dev/null +++ b/flow/designs/src/rcx-fanout/fanout_16.v @@ -0,0 +1,30 @@ +// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to 16 capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_16 ( + input wire clock, + input wire reset, + input wire din, + input wire [15:0] perturb, + output reg [15:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {16{1'b0}}; + else begin + for (i = 0; i < 16; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule diff --git a/flow/designs/src/rcx-fanout/fanout_2.v b/flow/designs/src/rcx-fanout/fanout_2.v new file mode 100644 index 0000000000..3aaa77f159 --- /dev/null +++ b/flow/designs/src/rcx-fanout/fanout_2.v @@ -0,0 +1,30 @@ +// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to 2 capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_2 ( + input wire clock, + input wire reset, + input wire din, + input wire [1:0] perturb, + output reg [1:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {2{1'b0}}; + else begin + for (i = 0; i < 2; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule diff --git a/flow/designs/src/rcx-fanout/fanout_32.v b/flow/designs/src/rcx-fanout/fanout_32.v new file mode 100644 index 0000000000..f6cdbfa119 --- /dev/null +++ b/flow/designs/src/rcx-fanout/fanout_32.v @@ -0,0 +1,30 @@ +// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to 32 capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_32 ( + input wire clock, + input wire reset, + input wire din, + input wire [31:0] perturb, + output reg [31:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {32{1'b0}}; + else begin + for (i = 0; i < 32; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule diff --git a/flow/designs/src/rcx-fanout/fanout_4.v b/flow/designs/src/rcx-fanout/fanout_4.v new file mode 100644 index 0000000000..b4c9629ae8 --- /dev/null +++ b/flow/designs/src/rcx-fanout/fanout_4.v @@ -0,0 +1,30 @@ +// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to 4 capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_4 ( + input wire clock, + input wire reset, + input wire din, + input wire [3:0] perturb, + output reg [3:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {4{1'b0}}; + else begin + for (i = 0; i < 4; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule diff --git a/flow/designs/src/rcx-fanout/fanout_64.v b/flow/designs/src/rcx-fanout/fanout_64.v new file mode 100644 index 0000000000..be88011e71 --- /dev/null +++ b/flow/designs/src/rcx-fanout/fanout_64.v @@ -0,0 +1,30 @@ +// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to 64 capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_64 ( + input wire clock, + input wire reset, + input wire din, + input wire [63:0] perturb, + output reg [63:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {64{1'b0}}; + else begin + for (i = 0; i < 64; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule diff --git a/flow/designs/src/rcx-fanout/fanout_8.v b/flow/designs/src/rcx-fanout/fanout_8.v new file mode 100644 index 0000000000..0f4c5c2190 --- /dev/null +++ b/flow/designs/src/rcx-fanout/fanout_8.v @@ -0,0 +1,30 @@ +// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to 8 capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_8 ( + input wire clock, + input wire reset, + input wire din, + input wire [7:0] perturb, + output reg [7:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {8{1'b0}}; + else begin + for (i = 0; i < 8; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule diff --git a/flow/docs/rcx/BUILD.bazel b/flow/docs/rcx/BUILD.bazel new file mode 100644 index 0000000000..8ea52de3ca --- /dev/null +++ b/flow/docs/rcx/BUILD.bazel @@ -0,0 +1,24 @@ +load("@orfs-pip//:requirements.bzl", "requirement") +load("@rules_python//python:defs.bzl", "py_binary") + +# Synthetic-design generator (stdlib only). +py_binary( + name = "gen_study", + srcs = ["gen_study.py"], + visibility = ["//visibility:public"], +) + +# Aggregate the swept results and (re)generate the study plots + data table. +# Run from the repo with: bazelisk run //flow/docs/rcx:update +# It resolves the flow/ results directory from BUILD_WORKING_DIRECTORY and +# writes the PNGs back into docs/rcx/plots/. +py_binary( + name = "update", + srcs = ["plot_rcx_study.py"], + main = "plot_rcx_study.py", + visibility = ["//visibility:public"], + deps = [ + requirement("matplotlib"), + requirement("numpy"), + ], +) diff --git a/flow/docs/rcx/README.md b/flow/docs/rcx/README.md new file mode 100644 index 0000000000..cf91b4a1ef --- /dev/null +++ b/flow/docs/rcx/README.md @@ -0,0 +1,191 @@ +# Disappointment is just mismanaged expectations + +### What to expect when global-route WNS meets RCX sign-off + +This is a small, self-contained study (synthetic designs + a few scripts) that +measures **how far the global-route (GRT) timing estimate is from the +post-route OpenRCX sign-off**, as a function of net fan-out and wire length, +across PDKs. It exists so that nobody is *surprised* when the WNS they read at +global route is not the WNS they get at `finish`. The gap is real, it is +predictable, and — as the plots below show — it can be large enough to flip a +design from "closes" to "fails" and back. + +> TL;DR: ORFS computes timing three times with three different parasitic models +> — `set_wire_rc` at placement, per-layer `set_layer_rc` after global route, and +> OpenRCX extraction at `finish`. The first two are *estimates*; only the last +> is *extracted* from the routed geometry. For long / high-fan-out nets the +> estimate and the extraction diverge. Today nothing in the flow warns you which +> nets are responsible. This study quantifies the divergence and proposes that +> global route flag the offending nets. + +## The three parasitic models (why there is a gap at all) + +OpenROAD does not have one parasitic model, it has three, applied at three +points in the flow ([OpenROAD discussion #3943][3943]): + +| Stage | Parasitics | Command | Accuracy | +|-------|-----------|---------|----------| +| placement | one default layer's R/C × estimated wire length | `set_wire_rc` | roughest | +| global route | per-layer R/C × global-route wire length | `set_layer_rc` (`estimate_parasitics -global_routing`) | better topology, still lumped, **coupling-blind** | +| finish | extracted from detailed-routed geometry | OpenRCX `extract_parasitics -ext_model_file $RCX_RULES` | sign-off | + +The resizer README states the limitation plainly: + +> *"Placement-based parasitics cannot accurately predict routed parasitics, so a +> margin can be used to 'over-repair' the design to compensate."* — [rsz README][rsz] + +The per-layer `set_layer_rc` values that drive the global-route estimate are a +**single linear model per layer**: capacitance ≈ (per-layer C) × (wire length). +That model: + +- ignores **coupling capacitance** to neighbours (which dominates at advanced + nodes and depends on routing that does not exist yet at global route); +- is only as good as the per-layer constants in the platform's `setRC.tcl`, + which are hand-derived and **not systematically validated against the RCX + deck** by the platform bring-up procedure ([PlatformBringUp][bringup]); +- "gives us an average over different contexts, but also 'hides' differences in + topology and layer assignment which may lead to inconsistencies" + ([ORFS issue #3969][3969]). + +ORFS ships a tool, `flow/util/correlateRC.py` (`make correlate_rc`), that fits +those per-layer constants to RCX and plots the residual GRT-vs-RCX gap. It is an +**offline, whole-PDK calibration step**. There is **no in-flow, per-design check +that the specific nets you just built fall inside the envelope where that linear +model is trustworthy.** That missing check is the feature this study argues for. + +## The experiment + +Synthetic, deliberately minimal designs (`docs/rcx/gen_study.py`): a single +launch flop (the *hub*) drives one net that fans out to **N** capture flops. +Inputs are pinned to the **west** edge, outputs to the **east** edge, so the +fan-out net spans the die. The hub is `dont_touch`, so the resizer cannot clone +the driver and chop the net into short, well-estimated segments — the long net +stays long, which is the whole point. We sweep **N = 1, 2, 4, 8, 16, 32, 64, +128**, well past the "sane RTL" fan-out region, and read WNS at every flow stage +plus the per-net GRT and RCX parasitics (`make write_net_rc`). + +WNS is **normalized by the clock period** so the *shape* of the curves is +comparable across PDKs (we do not care about absolute MHz here, only how far the +estimate strays from sign-off). + +### The "sane RTL" region + +The shaded bands on every plot mark where the estimate is expected to hold: + +- **green, fan-out ≤ 16** — at/under the logical-effort FO4 sweet spot and the + usual `set_max_fanout` floor; the Steiner topology (FLUTE) is accurate to + ~0.07% wire-length error, so the estimate should track RCX; +- **amber, 16–64** — the resizer starts inserting buffer trees; coupling and + detour error grow; +- **red, > 64** — multi-level buffering is mandatory and many-sink nets' + half-perimeter wire length under-estimates badly. + +Fan-out is a *proxy* for the real driver (long, coupling-heavy nets); the study +also varies wire length directly (see below). + +## Results + +Plots and `plots/study_data.csv` are generated by `bazelisk run +//flow/docs/rcx:update` (or `python3 docs/rcx/plot_rcx_study.py`) and committed, +so they render in GitHub's static Markdown. + +**The headline.** On asap7, the fan-out-128 design **closes at global route and +fails at sign-off**: GRT reports WNS ≈ **+21 ps** (looks fine), RCX reports WNS +≈ **−2 ps** (does not meet timing). The estimate is also *pessimistic* at low +fan-out (e.g. fan-out 16: GRT under-reports slack by ~50 ps). So the GRT WNS is +not a conservative bound — it is wrong in *both* directions depending on the net. + +![WNS surprise (RCX - GRT) across PDKs](plots/wns_surprise.png) + +The "surprise" — how far RCX moves WNS from the GRT estimate, as a fraction of +the clock period — is **substantial on asap7 (7 nm)** and swings sign with +fan-out, but is **flat at ~0 on sky130hd and ihp-sg13g2 (130 nm)**: at the older +node the lumped per-layer estimate tracks extraction to a fraction of a +picosecond. **gt2n (2 nm) ships no OpenRCX deck at all**, so `finish` *is* the +GRT estimate — there is nothing to diverge from, and no extraction-based +sign-off exists. The divergence is an **advanced-node phenomenon**, exactly +where it hurts most. + +![normalized WNS per stage vs fan-out, asap7](plots/wns_vs_fanout_asap7.png) + +Per net, the GRT capacitance estimate is off by tens of percent even where WNS +looks healthy — the errors partially cancel along a path, which is precisely why +the WNS number *hides* them: + +![per-net GRT-estimate vs RCX wire capacitance, asap7](plots/cap_divergence_asap7.png) + +The actionable per-net report (`docs/rcx/rcx_divergence_report.py`) ranks the +nets whose GRT estimate is furthest from RCX (net name, fan-out, routed length, +GRT vs RCX cap, % error, verdict) — the report this study argues global route +should emit natively. + +## Can we tune the estimate to match? Is this a bug? + +Largely **no, and no** — it is a known *calibration limitation*, not a defect: + +- The per-layer `set_layer_rc` model is intentionally coarse; improving it is + tracked as an enhancement ([ORFS #3969][3969], the motivation for + `correlateRC.py`'s `--mode segment`). +- Idiomatic levers exist but are blunt: re-derive `setRC.tcl` per corner from + the RCX deck with `make correlate_rc`; toggle `ENABLE_RESISTANCE_AWARE`; + apply `repair_design -cap_margin/-slew_margin` to "over-repair". None of these + tell you *which net in your design* is mis-estimated. +- OpenRCX itself is calibrated against a golden field solver + ([calibration][rcxcal]); the GRT *estimate* is not calibrated per design. + +## Feature request (the point of filing this) + +Global route already owns a DRC-marker database (`dbMarkerCategory "Global +route"`) and already attaches the offending nets to its **congestion** markers. +We ask for that same, already-built machinery to also surface parasitic +estimation risk: + +1. **A per-net GRT-vs-RCX divergence report** (or an `estimate_parasitics` + mode that emits per-net estimated R/C next to the routed extraction), so the + gap is queryable instead of requiring two SPEF dumps + `diff_spef`. +2. **A new global-route DRC-marker subcategory, "parasitic estimation out of + range,"** that `addSource()`s the nets whose fan-out / Steiner length / layer + span put them outside the envelope where `set_layer_rc`'s linear model is + trustworthy — so they light up in the DRC viewer exactly like congestion + markers do, including for *non-failing* designs. +3. **A warning + RTL guidance** when such nets exist ("net X: fan-out N, length + L µm — estimate may diverge from extraction; consider splitting the net, + pipelining, or an explicit fan-out buffer stage"). + +This turns a silent, end-of-flow surprise into an early, actionable signal. + +## Reproduce + +```bash +# 1. generate the synthetic designs (all PDKs) +python3 flow/docs/rcx/gen_study.py +# 2. run the full flow + collect per-stage WNS and per-net RC for a PDK +flow/docs/rcx/run_study.sh asap7 # then sky130hd, ihp-sg13g2, gt2n +# 3. (re)generate the plots + data table +python3 flow/docs/rcx/plot_rcx_study.py # or: bazelisk run //flow/docs/rcx:update +# 4. actionable per-net report for one design +python3 flow/docs/rcx/rcx_divergence_report.py \ + results/asap7/rcx-fanout-128/base/6_net_rc.csv +``` + +Note: **gt2n ships no OpenRCX deck**, so its `finish` stage falls back to the +global-route estimate — there is no extraction sign-off to diverge from. It is +included as an estimate-only data point, and that absence is itself a finding: +at 2 nm in ORFS today there is no extraction-based timing sign-off at all. + +[3943]: https://github.com/The-OpenROAD-Project/OpenROAD/discussions/3943 +[3969]: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/issues/3969 +[rsz]: https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/rsz/README.md +[bringup]: https://openroad-flow-scripts.readthedocs.io/en/latest/contrib/PlatformBringUp.html +[rcxcal]: https://openroad.readthedocs.io/en/latest/main/src/rcx/doc/calibration.html + +### References + +- I. Sutherland, R. Sproull, D. Harris, *Logical Effort: Designing Fast CMOS + Circuits*, Morgan Kaufmann, 1999. (FO4 / `set_max_fanout`.) +- C. Chu, Y.-C. Wong, "FLUTE: Fast Lookup Table Based Rectilinear Steiner + Minimal Tree Algorithm," ICCAD 2004 / IEEE TCAD 2008. (Steiner WL accuracy.) +- Liu et al., "Bridging the Gap between Global Route and Detailed Route ... for + Wire Parasitics and Delay Prediction," arXiv:2305.06917, 2023. +- L. Clark et al., "ASAP7: A 7-nm finFET predictive PDK," Microelectronics + Journal, 2016. diff --git a/flow/docs/rcx/gen_study.py b/flow/docs/rcx/gen_study.py new file mode 100644 index 0000000000..8ebd2fd567 --- /dev/null +++ b/flow/docs/rcx/gen_study.py @@ -0,0 +1,173 @@ +#!/usr/bin/env python3 +"""Generate the synthetic designs for the RCX-vs-GRT parasitic-divergence study. + +Writes, for every (PDK, fanout) pair: + flow/designs/src/rcx-fanout/fanout_.v (PDK-independent RTL) + flow/designs//rcx-fanout-/config.mk + flow/designs//rcx-fanout-/constraint.sdc + flow/designs//rcx-fanout-/io.tcl + +The RTL is a left-to-right macro: one launch flop (the "hub") drives a single +net that fans out to N capture flops; inputs are pinned to the WEST edge and +outputs to the EAST edge, so the fan-out net physically spans the die. As N +grows the net leaves the region where the global-route parasitic *estimate* +tracks the post-route RCX *extraction* -- which is what the study measures. + +Run from the flow/ directory: python3 docs/rcx/gen_study.py +""" + +import os + +# fanout=1 is the "no fan-out" single-sink baseline; the sweep runs well past +# the "sane RTL" region (see docs/rcx/README.md) so the divergence is visible. +FANOUTS = [1, 2, 4, 8, 16, 32, 64, 128] + +# Per-PDK knobs. width0/wpf set the die width (and thus the west->east fan-out +# net length, the dominant lever on the GRT-vs-RCX gap); coarser/older nodes +# need physically longer wires for the wire RC to matter, so they get a larger +# width scale. inset is the die->core spacing (must clear the PDN ring). clk is +# a constant fast period per PDK (the study normalizes WNS by it). +PDKS = { + "asap7": {"clk_period": 250, "die_h": 12.0, "inset": 1.0, + "width0": 150.0, "wpf": 2.0, "has_rcx": True, "extra": {}}, + "sky130hd": {"clk_period": 8000, "die_h": 140.0, "inset": 12.0, "pin_pitch": 1.5, + "width0": 500.0, "wpf": 6.0, "has_rcx": True, "extra": {}}, + "ihp-sg13g2": {"clk_period": 6000, "die_h": 160.0, "inset": 26.0, "pin_pitch": 1.5, + "width0": 500.0, "wpf": 6.0, "has_rcx": True, "extra": {}}, + # gt2n ships no OpenRCX deck: its `final` stage falls back to the global + # route estimate, so there is no extraction sign-off to diverge from. We + # still run it (estimate-only) and annotate that in the plots. gt2n designs + # must set MAX_ROUTING_LAYER (the flow requires it). + "gt2n": {"clk_period": 600, "die_h": 12.0, "inset": 2.0, + "width0": 150.0, "wpf": 2.0, "has_rcx": False, + "extra": {"MAX_ROUTING_LAYER": "M5"}}, +} + +HERE = os.path.dirname(os.path.abspath(__file__)) +FLOW = os.path.abspath(os.path.join(HERE, "..", "..")) +SRC_DIR = os.path.join(FLOW, "designs", "src", "rcx-fanout") + + +def verilog(n): + return f"""// Generated by docs/rcx/gen_study.py -- do not edit by hand. +// +// Left-to-right fan-out macro: a single launch flop ("hub") drives a net that +// fans out to {n} capture flop(s). Inputs are on the WEST edge, outputs on the +// EAST edge (see io.tcl), so the fan-out net spans the die. Each sink is XOR'd +// with its own perturb bit and bonded to a distinct output, so synthesis can +// neither merge nor delete sinks. The hub is dont_touch so the resizer cannot +// clone the driver and shorten the net (which would erase the effect we study). +module fanout_{n} ( + input wire clock, + input wire reset, + input wire din, + input wire [{n - 1}:0] perturb, + output reg [{n - 1}:0] dout +); + (* dont_touch = "true" *) reg hub; + always @(posedge clock) begin + if (reset) hub <= 1'b0; + else hub <= din; + end + + integer i; + always @(posedge clock) begin + if (reset) dout <= {{{n}{{1'b0}}}}; + else begin + for (i = 0; i < {n}; i = i + 1) + dout[i] <= hub ^ perturb[i]; + end + end +endmodule +""" + + +def config_mk(pdk, n, info): + # The GRT-vs-RCX WNS gap is driven by absolute wire length (RC ~ L^2), so + # the die must be wide enough that the west->east fan-out net is genuinely + # long; otherwise the gap is only a few ps and invisible. ~150um exposes a + # ~50ps gap on asap7; it grows with fan-out as the net carries more sinks. + # Loose placement density lets the capture flops spread toward the east edge + # (their pinned outputs) instead of clumping next to the hub. + width = max(info["width0"], 8.0 + info["wpf"] * n) + # Height must give the west/east edges enough IO-pin slots: the input edge + # carries n perturb pins + clock/din/reset, the output edge carries n dout + # pins. ~0.15 um/pin keeps a comfortable margin over the placer's slot count. + die_h = max(info["die_h"], round((n + 4) * info.get("pin_pitch", 0.15), 1)) + ins = info["inset"] + extra = "".join( + f"export {k:<24} = {v}\n" for k, v in info.get("extra", {}).items() + ) + return f"""# Generated by docs/rcx/gen_study.py -- do not edit by hand. +export PLATFORM = {pdk} +export DESIGN_NAME = fanout_{n} +export DESIGN_NICKNAME = rcx-fanout-{n} + +export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_{n}.v +export SDC_FILE = $(DESIGN_HOME)/{pdk}/rcx-fanout-{n}/constraint.sdc +export IO_CONSTRAINTS = $(DESIGN_HOME)/{pdk}/rcx-fanout-{n}/io.tcl + +export DIE_AREA = 0 0 {width:.1f} {die_h:.1f} +export CORE_AREA = {ins:.1f} {ins:.1f} {width - ins:.1f} {die_h - ins:.1f} +export PLACE_DENSITY = 0.10 +{extra} +# Tiny design: keep the run fast. +export SKIP_LAST_GASP ?= 1 +""" + + +def constraint_sdc(pdk, n, info): + # Self-contained (most platforms ship no generic constraints.sdc to source): + # a single clock plus set_max_delay optimization targets for the io legs. + # Only the reg->fan-out-net->reg arc is the timing-closure metric the study + # plots; set_max_delay (not set_input/output_delay) avoids hold-cell + # insertion and any clock-insertion-latency assumptions. + p = info["clk_period"] + opt = p - p // 5 + return f"""# Generated by docs/rcx/gen_study.py -- do not edit by hand. +current_design fanout_{n} + +set clk_period {p} +create_clock -name clock -period {p} -waveform [list 0 [expr {p} / 2]] [get_ports clock] + +if {{[llength [get_ports -quiet reset]] == 1}} {{ + set_false_path -from [get_ports reset] +}} + +set non_clk_inputs [all_inputs -no_clocks] +set_max_delay -ignore_clock_latency {opt} -from $non_clk_inputs -to [all_registers] +set_max_delay -ignore_clock_latency {opt} -from [all_registers] -to [all_outputs] +set_max_delay {opt} -from $non_clk_inputs -to [all_outputs] +group_path -name reg2reg -from [all_registers] -to [all_registers] +""" + + +def io_tcl(): + return """# Generated by docs/rcx/gen_study.py -- do not edit by hand. +# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the +# fan-out net spans the die from west to east. +set_io_pin_constraint -direction INPUT -region left:* +set_io_pin_constraint -direction OUTPUT -region right:* +""" + + +def write(path, content): + os.makedirs(os.path.dirname(path), exist_ok=True) + with open(path, "w") as f: + f.write(content) + print("wrote", os.path.relpath(path, FLOW)) + + +def main(): + for n in FANOUTS: + write(os.path.join(SRC_DIR, f"fanout_{n}.v"), verilog(n)) + for pdk, info in PDKS.items(): + for n in FANOUTS: + d = os.path.join(FLOW, "designs", pdk, f"rcx-fanout-{n}") + write(os.path.join(d, "config.mk"), config_mk(pdk, n, info)) + write(os.path.join(d, "constraint.sdc"), constraint_sdc(pdk, n, info)) + write(os.path.join(d, "io.tcl"), io_tcl()) + + +if __name__ == "__main__": + main() diff --git a/flow/docs/rcx/plot_rcx_study.py b/flow/docs/rcx/plot_rcx_study.py new file mode 100644 index 0000000000..3395262040 --- /dev/null +++ b/flow/docs/rcx/plot_rcx_study.py @@ -0,0 +1,294 @@ +#!/usr/bin/env python3 +"""Aggregate the RCX-vs-GRT fan-out sweep and render the study plots + data table. + +Reads, for every PDK/fanout that has been run (see docs/rcx/run_study.sh): + reports//rcx-fanout-/base/metadata.json per-stage WNS + results//rcx-fanout-/base/6_net_rc.csv per-net GRT & RCX R/C + designs//rcx-fanout-/constraint.sdc clk_period (normalizer) + +Writes into docs/rcx/plots/: + wns_vs_fanout_.png normalized WNS per stage vs fan-out (one panel/PDK) + wns_surprise.png cross-PDK (RCX - GRT) WNS surprise vs fan-out + cap_divergence_.png per-net (RCX-GRT)/GRT cap divergence vs fan-out + study_data.csv the aggregated table + +We do NOT care about absolute WNS, only the SHAPE of the curves across PDKs, so +every WNS is normalized by that design's SDC clock period (a unitless fraction +of the period). See docs/rcx/README.md. + +Run via: bazelisk run //flow/docs/rcx:update (or) python3 docs/rcx/plot_rcx_study.py +""" + +import csv +import json +import os +import re +import sys + +import matplotlib + +matplotlib.use("Agg") +import matplotlib.pyplot as plt # noqa: E402 +import numpy as np # noqa: E402 + +FANOUTS = [1, 2, 4, 8, 16, 32, 64, 128] + +# Literature-backed "sane RTL" fan-out regions (see README references). Fan-out +# is a proxy for the real driver (coupling-blind lumped RC + many-sink HPWL +# underestimate); the bands mark where the pre-route estimate is expected to +# stop tracking RCX. +SANE_MAX = 16 # <= ~FO4 / set_max_fanout floor: GRT should track RCX +TRANSITION_MAX = 64 # buffer trees inserted, divergence grows +# >64: outside the estimation envelope + +# Stages to plot as "estimate" curves leading up to the RCX sign-off, in flow +# order. Keys are metadata.json prefixes; finish = post-RCX extraction. +STAGES = [ + ("floorplan", "floorplan"), + ("cts", "cts"), + ("globalroute", "global route (GRT est.)"), + ("finish", "finish (RCX extract)"), +] + + +def flow_dir(): + """Locate the flow/ directory whether run directly or via `bazel run`.""" + wd = os.environ.get("BUILD_WORKING_DIRECTORY") + if wd: + # invoked from within the repo via bazel run + for cand in (wd, os.path.join(wd, "flow")): + if os.path.isdir(os.path.join(cand, "designs")): + return cand + here = os.path.dirname(os.path.abspath(__file__)) + return os.path.abspath(os.path.join(here, "..", "..")) + + +FLOW = flow_dir() +PLOTS = os.path.join(FLOW, "docs", "rcx", "plots") + + +def clk_period(pdk, n): + sdc = os.path.join(FLOW, "designs", pdk, f"rcx-fanout-{n}", "constraint.sdc") + with open(sdc) as f: + m = re.search(r"set\s+clk_period\s+(\d+(?:\.\d+)?)", f.read()) + return float(m.group(1)) if m else None + + +def discover_pdks(): + base = os.path.join(FLOW, "reports") + pdks = [] + if os.path.isdir(base): + for pdk in sorted(os.listdir(base)): + if any( + os.path.isfile( + os.path.join(base, pdk, f"rcx-fanout-{n}", "base", "metadata.json") + ) + for n in FANOUTS + ): + pdks.append(pdk) + return pdks + + +def load_wns(pdk): + """Return {stage: {fanout: normalized_ws}} for one PDK.""" + out = {s: {} for s, _ in STAGES} + for n in FANOUTS: + meta = os.path.join( + FLOW, "reports", pdk, f"rcx-fanout-{n}", "base", "metadata.json" + ) + if not os.path.isfile(meta): + continue + d = json.load(open(meta)) + period = clk_period(pdk, n) + if not period: + continue + for stage, _ in STAGES: + ws = d.get(f"{stage}__timing__setup__ws") + if ws is not None: + out[stage][n] = ws / period + return out + + +def load_net_rc(pdk): + """Return {design_fanout: {"all": [(fo, grt_cap, rcx_cap)], "hub": (fo, grt_cap, rcx_cap)}}. + + The "hub" of each design is its highest-fan-out net (the net under study); + its fan-out is ~N. Tracking the hub net per design gives a clean + estimate-error-vs-fan-out curve (the all-nets scatter is dominated by the + many incidental fan-out-1 nets present in every design).""" + out = {} + for n in FANOUTS: + csvf = os.path.join( + FLOW, "results", pdk, f"rcx-fanout-{n}", "base", "6_net_rc.csv" + ) + if not os.path.isfile(csvf): + continue + rows = [] + with open(csvf) as f: + for line in f: + if line.startswith("#") or not line.strip(): + continue + t = [x.strip() for x in line.split(",")] + # name,type,fanout,grt_res,grt_cap,rcx_res,rcx_cap, + try: + rows.append((int(t[2]), float(t[4]), float(t[6]))) + except (ValueError, IndexError): + continue + rows = [r for r in rows if r[2] > 0] # need extracted cap + if not rows: + continue + out[n] = {"all": rows, "hub": max(rows, key=lambda r: r[0])} + return out + + +def shade_regions(ax, xmax): + ax.axvspan(0.9, SANE_MAX, color="tab:green", alpha=0.08, zorder=0) + ax.axvspan(SANE_MAX, TRANSITION_MAX, color="tab:orange", alpha=0.08, zorder=0) + ax.axvspan(TRANSITION_MAX, xmax, color="tab:red", alpha=0.08, zorder=0) + ax.text(np.sqrt(0.9 * SANE_MAX), 0.02, "sane RTL", color="tab:green", + ha="center", va="bottom", transform=ax.get_xaxis_transform(), fontsize=8) + ax.text(np.sqrt(SANE_MAX * TRANSITION_MAX), 0.02, "transition", color="tab:orange", + ha="center", va="bottom", transform=ax.get_xaxis_transform(), fontsize=8) + ax.text(np.sqrt(TRANSITION_MAX * xmax), 0.02, "out of envelope", color="tab:red", + ha="center", va="bottom", transform=ax.get_xaxis_transform(), fontsize=8) + + +def plot_wns_per_pdk(pdk, wns): + fig, ax = plt.subplots(figsize=(8, 5)) + xmax = FANOUTS[-1] * 1.3 + shade_regions(ax, xmax) + for stage, label in STAGES: + pts = sorted(wns[stage].items()) + if not pts: + continue + xs, ys = zip(*pts) + ax.plot(xs, ys, marker="o", label=label) + ax.set_xscale("log", base=2) + ax.set_xticks(FANOUTS) + ax.get_xaxis().set_major_formatter(plt.ScalarFormatter()) + ax.set_xlabel("net fan-out (number of sinks)") + ax.set_ylabel("normalized WNS (worst slack / clock period)") + ax.axhline(0.0, color="k", lw=0.8, ls="--") + ax.set_title(f"{pdk}: normalized WNS per flow stage vs fan-out") + ax.legend() + ax.grid(True, which="both", alpha=0.3) + out = os.path.join(PLOTS, f"wns_vs_fanout_{pdk}.png") + fig.savefig(out, dpi=150, bbox_inches="tight") + plt.close(fig) + print("wrote", os.path.relpath(out, FLOW)) + + +def plot_surprise(all_wns): + """Cross-PDK: (RCX finish - GRT estimate) normalized WNS vs fan-out.""" + fig, ax = plt.subplots(figsize=(8, 5)) + xmax = FANOUTS[-1] * 1.3 + shade_regions(ax, xmax) + for pdk, wns in all_wns.items(): + xs, ys = [], [] + for n in FANOUTS: + if n in wns["finish"] and n in wns["globalroute"]: + xs.append(n) + ys.append(wns["finish"][n] - wns["globalroute"][n]) + if xs: + # PDKs without an OpenRCX deck (e.g. gt2n) fall back to the GRT + # estimate at finish, so finish == globalroute and there is nothing + # to diverge -- flag that rather than implying a perfect estimate. + label = pdk if max(abs(y) for y in ys) > 1e-6 else f"{pdk} (no RCX)" + ax.plot(xs, ys, marker="o", label=label) + ax.set_xscale("log", base=2) + ax.set_xticks(FANOUTS) + ax.get_xaxis().set_major_formatter(plt.ScalarFormatter()) + ax.set_xlabel("net fan-out (number of sinks)") + ax.set_ylabel("WNS surprise (RCX - GRT) / clock period") + ax.axhline(0.0, color="k", lw=0.8, ls="--") + ax.set_title("The surprise: how much RCX moves WNS vs the GRT estimate") + ax.legend() + ax.grid(True, which="both", alpha=0.3) + out = os.path.join(PLOTS, "wns_surprise.png") + fig.savefig(out, dpi=150, bbox_inches="tight") + plt.close(fig) + print("wrote", os.path.relpath(out, FLOW)) + + +def cap_err(grt, rcx): + """GRT estimate error vs the RCX truth, in percent (+ => GRT over-estimates).""" + return (grt - rcx) / rcx * 100.0 + + +def plot_cap_divergence(pdk, net_rc): + if not net_rc: + return + fig, ax = plt.subplots(figsize=(8, 5)) + xmax = FANOUTS[-1] * 1.3 + shade_regions(ax, xmax) + # background: every net of every design, at its own fan-out + sx, sy = [], [] + for d in net_rc.values(): + for fo, grt, rcx in d["all"]: + if fo >= 1 and grt > 0: + sx.append(fo) + sy.append(cap_err(grt, rcx)) + if sx: + jit = np.exp(np.random.uniform(-0.05, 0.05, size=len(sx))) + ax.scatter(np.array(sx) * jit, sy, s=10, alpha=0.25, + color="tab:blue", label="all nets") + # foreground: the hub net of each design (the net under study, fan-out ~= N) + hx, hy = [], [] + for n in sorted(net_rc): + fo, grt, rcx = net_rc[n]["hub"] + if grt > 0: + hx.append(fo) + hy.append(cap_err(grt, rcx)) + ax.plot(hx, hy, marker="s", color="tab:red", label="hub net (under study)") + ax.set_xscale("log", base=2) + ax.set_xticks(FANOUTS) + ax.get_xaxis().set_major_formatter(plt.ScalarFormatter()) + ax.set_xlabel("net fan-out (number of sinks)") + ax.set_ylabel("GRT wire-cap estimate error (GRT - RCX) / RCX [%]") + ax.axhline(0.0, color="k", lw=0.8, ls="--") + ax.set_title(f"{pdk}: GRT wire-capacitance estimate vs RCX extraction") + ax.legend() + ax.grid(True, which="both", alpha=0.3) + out = os.path.join(PLOTS, f"cap_divergence_{pdk}.png") + fig.savefig(out, dpi=150, bbox_inches="tight") + plt.close(fig) + print("wrote", os.path.relpath(out, FLOW)) + + +def write_table(all_wns): + out = os.path.join(PLOTS, "study_data.csv") + with open(out, "w", newline="") as f: + w = csv.writer(f) + w.writerow(["pdk", "fanout"] + [s for s, _ in STAGES] + ["surprise"]) + for pdk, wns in all_wns.items(): + for n in FANOUTS: + row = [pdk, n] + [wns[s].get(n, "") for s, _ in STAGES] + if n in wns["finish"] and n in wns["globalroute"]: + row.append(wns["finish"][n] - wns["globalroute"][n]) + else: + row.append("") + w.writerow(row) + print("wrote", os.path.relpath(out, FLOW)) + + +def main(): + os.makedirs(PLOTS, exist_ok=True) + np.random.seed(0) + pdks = discover_pdks() + if not pdks: + print("No results found. Run docs/rcx/run_study.sh first.", file=sys.stderr) + return 1 + print("PDKs:", ", ".join(pdks)) + all_wns = {} + for pdk in pdks: + wns = load_wns(pdk) + all_wns[pdk] = wns + plot_wns_per_pdk(pdk, wns) + plot_cap_divergence(pdk, load_net_rc(pdk)) + plot_surprise(all_wns) + write_table(all_wns) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/flow/docs/rcx/plots/cap_divergence_asap7.png b/flow/docs/rcx/plots/cap_divergence_asap7.png new file mode 100644 index 0000000000..e5d48a5d6c Binary files /dev/null and b/flow/docs/rcx/plots/cap_divergence_asap7.png differ diff --git a/flow/docs/rcx/plots/cap_divergence_ihp-sg13g2.png b/flow/docs/rcx/plots/cap_divergence_ihp-sg13g2.png new file mode 100644 index 0000000000..bb5fc90f13 Binary files /dev/null and b/flow/docs/rcx/plots/cap_divergence_ihp-sg13g2.png differ diff --git a/flow/docs/rcx/plots/cap_divergence_sky130hd.png b/flow/docs/rcx/plots/cap_divergence_sky130hd.png new file mode 100644 index 0000000000..ba3d750bd6 Binary files /dev/null and b/flow/docs/rcx/plots/cap_divergence_sky130hd.png differ diff --git a/flow/docs/rcx/plots/study_data.csv b/flow/docs/rcx/plots/study_data.csv new file mode 100644 index 0000000000..2cd3ea26a0 --- /dev/null +++ b/flow/docs/rcx/plots/study_data.csv @@ -0,0 +1,33 @@ +pdk,fanout,floorplan,cts,globalroute,finish,surprise +asap7,1,0.62438,0.28025760000000005,0.26517759999999996,0.3628284,0.09765080000000004 +asap7,2,0.622208,0.2811356,0.2669952,0.330376,0.06338080000000001 +asap7,4,0.572052,0.26942160000000004,0.2575276,0.339154,0.08162639999999999 +asap7,8,0.580076,0.212552,0.1951668,0.29139800000000005,0.09623120000000004 +asap7,16,0.532976,0.12345919999999999,0.106724,0.3135232,0.20679920000000002 +asap7,32,0.530124,0.40226799999999996,0.392002,0.38984399999999997,-0.0021580000000000488 +asap7,64,0.498484,0.2173672,0.208872,0.2308028,0.0219308 +asap7,128,0.465212,0.02680732,0.0848352,-0.00782564,-0.09266084 +gt2n,1,0.7409783333333333,0.42891333333333337,0.35570999999999997,0.35570999999999997,0.0 +gt2n,2,0.7408716666666667,0.31511833333333333,0.19074166666666664,0.19074166666666664,0.0 +gt2n,4,0.7391933333333334,0.12307083333333334,-0.1010605,-0.1010605,0.0 +gt2n,8,0.7392133333333334,0.37095500000000003,0.26882333333333336,0.26882333333333336,0.0 +gt2n,16,0.7377583333333333,0.39076500000000003,0.260795,0.260795,0.0 +gt2n,32,0.7418416666666667,0.41768833333333333,0.32850999999999997,0.32850999999999997,0.0 +gt2n,64,0.7408183333333334,0.23402666666666666,0.09391999999999999,0.09391999999999999,0.0 +gt2n,128,0.7410216666666667,0.183575,0.04911416666666667,0.04911416666666667,0.0 +ihp-sg13g2,1,0.79996,0.7999149999999999,0.7999133333333333,0.7999416666666666,2.8333333333296906e-05 +ihp-sg13g2,2,0.79996,0.7999166666666667,0.7999149999999999,0.7999400000000001,2.500000000016378e-05 +ihp-sg13g2,4,0.79996,0.7999166666666667,0.7999149999999999,0.799935,2.0000000000020002e-05 +ihp-sg13g2,8,0.79996,0.7999133333333333,0.7999133333333333,0.7999183333333334,5.000000000143778e-06 +ihp-sg13g2,16,0.79996,0.7998533333333333,0.7998449999999999,0.7998983333333334,5.3333333333460686e-05 +ihp-sg13g2,32,0.79996,0.7998766666666667,0.7998700000000001,0.7998916666666668,2.1666666666697587e-05 +ihp-sg13g2,64,0.79996,0.7998633333333334,0.7998566666666668,0.7998500000000001,-6.666666666710341e-06 +ihp-sg13g2,128,0.79996,0.7998133333333334,0.799805,0.7997816666666666,-2.3333333333375172e-05 +sky130hd,1,0.79996625,0.79983875,0.79983875,0.7998425,3.749999999969056e-06 +sky130hd,2,0.79996625,0.7998375,0.7998350000000001,0.79981625,-1.8750000000067324e-05 +sky130hd,4,0.79996625,0.7997825000000001,0.79977875,0.79981625,3.7500000000023626e-05 +sky130hd,8,0.79996625,0.79978375,0.79977125,0.79978625,1.4999999999987246e-05 +sky130hd,16,0.79996625,0.7998225,0.7998200000000001,0.79982625,6.2499999998744116e-06 +sky130hd,32,0.7999625,0.7998225,0.79981875,0.799815,-3.749999999969056e-06 +sky130hd,64,0.799965,0.79977625,0.799755,0.79975875,3.749999999969056e-06 +sky130hd,128,0.799965,0.79977625,0.79975,0.7997475,-2.500000000016378e-06 diff --git a/flow/docs/rcx/plots/wns_surprise.png b/flow/docs/rcx/plots/wns_surprise.png new file mode 100644 index 0000000000..5cfa629416 Binary files /dev/null and b/flow/docs/rcx/plots/wns_surprise.png differ diff --git a/flow/docs/rcx/plots/wns_vs_fanout_asap7.png b/flow/docs/rcx/plots/wns_vs_fanout_asap7.png new file mode 100644 index 0000000000..62bbf34312 Binary files /dev/null and b/flow/docs/rcx/plots/wns_vs_fanout_asap7.png differ diff --git a/flow/docs/rcx/plots/wns_vs_fanout_gt2n.png b/flow/docs/rcx/plots/wns_vs_fanout_gt2n.png new file mode 100644 index 0000000000..d42438b80a Binary files /dev/null and b/flow/docs/rcx/plots/wns_vs_fanout_gt2n.png differ diff --git a/flow/docs/rcx/plots/wns_vs_fanout_ihp-sg13g2.png b/flow/docs/rcx/plots/wns_vs_fanout_ihp-sg13g2.png new file mode 100644 index 0000000000..f45ee9622c Binary files /dev/null and b/flow/docs/rcx/plots/wns_vs_fanout_ihp-sg13g2.png differ diff --git a/flow/docs/rcx/plots/wns_vs_fanout_sky130hd.png b/flow/docs/rcx/plots/wns_vs_fanout_sky130hd.png new file mode 100644 index 0000000000..f4eb429b07 Binary files /dev/null and b/flow/docs/rcx/plots/wns_vs_fanout_sky130hd.png differ diff --git a/flow/docs/rcx/rcx_divergence_report.py b/flow/docs/rcx/rcx_divergence_report.py new file mode 100644 index 0000000000..33ac304dd5 --- /dev/null +++ b/flow/docs/rcx/rcx_divergence_report.py @@ -0,0 +1,111 @@ +#!/usr/bin/env python3 +"""Actionable per-net GRT-estimate vs RCX-extracted parasitics divergence report. + +Consumes the per-net CSV already produced by `make write_net_rc` +(results///base/6_net_rc.csv -- see flow/util/write_net_rc.tcl, +which this study extended with a `fanout` column) and emits a ranked, annotated +report of the nets where the global-route parasitic *estimate* diverges most +from the post-route OpenRCX *extraction*. + +This is the report the study argues global_route should emit natively (as DRC +markers on the offending nets); see docs/rcx/README.md. Until then this script +produces the same information from existing flow data. + +Usage: + python3 docs/rcx/rcx_divergence_report.py results/asap7/rcx-fanout-128/base/6_net_rc.csv + python3 docs/rcx/rcx_divergence_report.py [--top N] [--sane-fanout 16] +""" + +import argparse +import sys + +# fF per Farad, for human-readable output. +FF = 1e15 + + +def parse_csv(path): + """Yield dicts per net from a 6_net_rc.csv (with the fanout column).""" + stack = [] + with open(path) as f: + for line in f: + if line.startswith("# stack:"): + for layer in line.removeprefix("# stack:").strip().split(): + name = layer.split("(")[0] + routing = "(routing)" in layer + stack.append((name, routing)) + continue + if line.startswith("#") or not line.strip(): + continue + t = [x.strip() for x in line.split(",")] + try: + lengths = [float(x) for x in t[7:]] + except ValueError: + continue + wl = sum( + ln for i, ln in enumerate(lengths) + if i < len(stack) and stack[i][1] + ) + yield { + "net": t[0], + "type": t[1], + "fanout": int(t[2]), + "grt_res": float(t[3]), + "grt_cap": float(t[4]), + "rcx_res": float(t[5]), + "rcx_cap": float(t[6]), + "wire_length": wl, + } + + +def pct(new, ref): + return (new - ref) / ref * 100.0 if ref else 0.0 + + +def main(): + ap = argparse.ArgumentParser(description=__doc__) + ap.add_argument("csv", help="6_net_rc.csv from `make write_net_rc`") + ap.add_argument("--top", type=int, default=20, help="rows to print") + ap.add_argument("--sane-fanout", type=int, default=16, + help="fan-out at/below which GRT is expected to track RCX") + args = ap.parse_args() + + nets = [n for n in parse_csv(args.csv) if n["rcx_cap"] > 0] + if not nets: + print("no nets with extracted parasitics in", args.csv, file=sys.stderr) + return 1 + + for n in nets: + n["cap_div"] = pct(n["grt_cap"], n["rcx_cap"]) # GRT relative to RCX truth + n["res_div"] = pct(n["grt_res"], n["rcx_res"]) if n["rcx_res"] else 0.0 + # Rank by absolute capacitance divergence weighted by the RCX cap itself, so + # big, badly-estimated nets (the ones that actually move timing) float up. + nets.sort(key=lambda n: abs(n["grt_cap"] - n["rcx_cap"]), reverse=True) + + n_out = sum(1 for n in nets if n["fanout"] > args.sane_fanout) + print(f"# GRT-estimate vs RCX-extracted parasitic divergence") + print(f"# source: {args.csv}") + print(f"# nets: {len(nets)} fan-out > {args.sane_fanout}: {n_out}") + print(f"# cap divergence = (GRT_cap - RCX_cap) / RCX_cap " + f"(negative => GRT under-estimates)") + print() + hdr = (f"{'net':<22} {'fanout':>6} {'len_um':>8} " + f"{'GRT_cap_fF':>10} {'RCX_cap_fF':>10} {'cap_div%':>8} " + f"{'res_div%':>8} verdict") + print(hdr) + print("-" * len(hdr)) + for n in nets[: args.top]: + verdict = "" + if n["fanout"] > args.sane_fanout: + verdict = "OUT-OF-ENVELOPE (high fan-out: split / pipeline / buffer)" + elif abs(n["cap_div"]) > 25: + verdict = "estimate off > 25%" + # GRT only populates net resistance for 2-pin nets; show n/a otherwise. + res = f"{n['res_div']:>8.1f}" if n["grt_res"] > 0 else f"{'n/a':>8}" + print(f"{n['net']:<22} {n['fanout']:>6d} {n['wire_length']:>8.2f} " + f"{n['grt_cap'] * FF:>10.2f} {n['rcx_cap'] * FF:>10.2f} " + f"{n['cap_div']:>8.1f} {res} {verdict}") + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/flow/docs/rcx/run_study.sh b/flow/docs/rcx/run_study.sh new file mode 100755 index 0000000000..774efc488b --- /dev/null +++ b/flow/docs/rcx/run_study.sh @@ -0,0 +1,38 @@ +#!/usr/bin/env bash +# Run the RCX-vs-GRT fan-out sweep for one PDK through the full flow and collect, +# per variant, the per-stage WNS (reports/.../metadata.json) and the per-net +# GRT-vs-RCX parasitics (results/.../6_net_rc.csv). +# +# Usage: flow/docs/rcx/run_study.sh [PDK] (default: asap7) +# Tiny designs -> a full sweep is a few minutes. Designs are independent; this +# runs them sequentially (the native flow is one design per make invocation). +set -u +cd "$(dirname "$0")/../.." # -> flow/ +# shellcheck disable=SC1091 +source ../env.sh >/dev/null 2>&1 + +PDK="${1:-asap7}" +FANOUTS=(1 2 4 8 16 32 64 128) + +for n in "${FANOUTS[@]}"; do + cfg="./designs/${PDK}/rcx-fanout-${n}/config.mk" + if [[ ! -f "$cfg" ]]; then + echo "SKIP ${PDK} fanout ${n}: no $cfg (run docs/rcx/gen_study.py)"; continue + fi + echo "=== ${PDK} fanout ${n}: flow ===" + if ! make DESIGN_CONFIG="$cfg" >/dev/null 2>&1; then + echo " FLOW FAILED for ${PDK} fanout ${n}"; continue + fi + make DESIGN_CONFIG="$cfg" metadata-generate >/dev/null 2>&1 + make DESIGN_CONFIG="$cfg" write_net_rc >/dev/null 2>&1 + m="reports/${PDK}/rcx-fanout-${n}/base/metadata.json" + if [[ -f "$m" ]]; then + python3 - "$m" "$n" <<'PY' +import json, sys +d = json.load(open(sys.argv[1])); n = sys.argv[2] +g = d.get("globalroute__timing__setup__ws"); f = d.get("finish__timing__setup__ws") +print(f" fanout {n:>3}: grt_ws={g} finish_ws={f}") +PY + fi +done +echo "Done. Aggregate + plot with: python3 docs/rcx/plot_rcx_study.py" diff --git a/flow/util/correlateRC.py b/flow/util/correlateRC.py index b8d75922ac..275020f6ba 100755 --- a/flow/util/correlateRC.py +++ b/flow/util/correlateRC.py @@ -162,6 +162,9 @@ def makeDict(): stack_line = line continue + if line.startswith("#"): + continue + tokens = line.strip().split(",") if args.mode == "segment": @@ -172,15 +175,17 @@ def makeDict(): else: netName = tokens[0] + # net CSV: name,type,fanout,grt_res,grt_cap,rcx_res,rcx_cap, data[design][netName] = { "type": tokens[1], - "grt_res": float(tokens[2]), - "grt_cap": float(tokens[3]), - "rcx_res": float(tokens[4]), - "rcx_cap": float(tokens[5]), + "fanout": int(tokens[2]), + "grt_res": float(tokens[3]), + "grt_cap": float(tokens[4]), + "rcx_res": float(tokens[5]), + "rcx_cap": float(tokens[6]), } - layer_lengths = [float(tok) for tok in tokens[6:]] + layer_lengths = [float(tok) for tok in tokens[7:]] for i, length in enumerate(layer_lengths): if length > 0: active_layers.add(i) diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index fbe7c956fd..6e90ab6420 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -56,6 +56,7 @@ proc write_rc_csv { filename } { } } puts $stream "" + puts $stream "# columns: net,type,fanout,grt_res,grt_cap,rcx_res,rcx_cap," set use_drt_data [env_var_exists_and_non_empty CORRELATE_DRT_WIRELENGTH] @@ -70,7 +71,8 @@ proc write_rc_csv { filename } { lassign $grt_net_name_to_rc($net_name) grt_net_res grt_net_cap lassign $rcx_net_name_to_rc($net_name) rcx_net_res rcx_net_cap set net_type [expr { [string equal $type "CLOCK"] ? "clock" : "signal" }] - puts -nonewline $stream "[get_full_name $net],$net_type," + set fanout [llength [get_pins -of $net -filter "direction == input"]] + puts -nonewline $stream "[get_full_name $net],$net_type,$fanout," puts -nonewline $stream [concat \ [format "%.3e" $grt_net_res] "," [format "%.3e" $grt_net_cap] "," \ [format "%.3e" $rcx_net_res] "," [format "%.3e" $rcx_net_cap]]