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flow/docs/rcx: add GRT-vs-RCX parasitic divergence study #4302

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15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-1/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = asap7
export DESIGN_NAME = fanout_1
export DESIGN_NICKNAME = rcx-fanout-1

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_1.v
export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-1/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-1/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 1.0 1.0 149.0 11.0
export PLACE_DENSITY = 0.10

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-1/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_1

set clk_period 250
create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/asap7/rcx-fanout-1/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-128/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = asap7
export DESIGN_NAME = fanout_128
export DESIGN_NICKNAME = rcx-fanout-128

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_128.v
export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-128/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-128/io.tcl

export DIE_AREA = 0 0 264.0 19.8
export CORE_AREA = 1.0 1.0 263.0 18.8
export PLACE_DENSITY = 0.10

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-128/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_128

set clk_period 250
create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/asap7/rcx-fanout-128/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-16/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = asap7
export DESIGN_NAME = fanout_16
export DESIGN_NICKNAME = rcx-fanout-16

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_16.v
export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-16/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-16/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 1.0 1.0 149.0 11.0
export PLACE_DENSITY = 0.10

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-16/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_16

set clk_period 250
create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/asap7/rcx-fanout-16/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-2/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = asap7
export DESIGN_NAME = fanout_2
export DESIGN_NICKNAME = rcx-fanout-2

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_2.v
export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-2/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-2/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 1.0 1.0 149.0 11.0
export PLACE_DENSITY = 0.10

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-2/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_2

set clk_period 250
create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/asap7/rcx-fanout-2/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-32/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = asap7
export DESIGN_NAME = fanout_32
export DESIGN_NICKNAME = rcx-fanout-32

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_32.v
export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-32/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-32/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 1.0 1.0 149.0 11.0
export PLACE_DENSITY = 0.10

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-32/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_32

set clk_period 250
create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/asap7/rcx-fanout-32/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-4/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = asap7
export DESIGN_NAME = fanout_4
export DESIGN_NICKNAME = rcx-fanout-4

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_4.v
export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-4/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-4/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 1.0 1.0 149.0 11.0
export PLACE_DENSITY = 0.10

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-4/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_4

set clk_period 250
create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/asap7/rcx-fanout-4/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-64/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = asap7
export DESIGN_NAME = fanout_64
export DESIGN_NICKNAME = rcx-fanout-64

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_64.v
export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-64/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-64/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 1.0 1.0 149.0 11.0
export PLACE_DENSITY = 0.10

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-64/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_64

set clk_period 250
create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/asap7/rcx-fanout-64/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-8/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = asap7
export DESIGN_NAME = fanout_8
export DESIGN_NICKNAME = rcx-fanout-8

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_8.v
export SDC_FILE = $(DESIGN_HOME)/asap7/rcx-fanout-8/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/rcx-fanout-8/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 1.0 1.0 149.0 11.0
export PLACE_DENSITY = 0.10

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/asap7/rcx-fanout-8/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_8

set clk_period 250
create_clock -name clock -period 250 -waveform [list 0 [expr 250 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 200 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 200 -from [all_registers] -to [all_outputs]
set_max_delay 200 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/asap7/rcx-fanout-8/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
16 changes: 16 additions & 0 deletions flow/designs/gt2n/rcx-fanout-1/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = gt2n
export DESIGN_NAME = fanout_1
export DESIGN_NICKNAME = rcx-fanout-1

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_1.v
export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-1/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-1/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 2.0 2.0 148.0 10.0
export PLACE_DENSITY = 0.10
export MAX_ROUTING_LAYER = M5

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/gt2n/rcx-fanout-1/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_1

set clk_period 600
create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs]
set_max_delay 480 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/gt2n/rcx-fanout-1/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
16 changes: 16 additions & 0 deletions flow/designs/gt2n/rcx-fanout-128/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = gt2n
export DESIGN_NAME = fanout_128
export DESIGN_NICKNAME = rcx-fanout-128

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_128.v
export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-128/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-128/io.tcl

export DIE_AREA = 0 0 264.0 19.8
export CORE_AREA = 2.0 2.0 262.0 17.8
export PLACE_DENSITY = 0.10
export MAX_ROUTING_LAYER = M5

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
15 changes: 15 additions & 0 deletions flow/designs/gt2n/rcx-fanout-128/constraint.sdc
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
current_design fanout_128

set clk_period 600
create_clock -name clock -period 600 -waveform [list 0 [expr 600 / 2]] [get_ports clock]

if {[llength [get_ports -quiet reset]] == 1} {
set_false_path -from [get_ports reset]
}

set non_clk_inputs [all_inputs -no_clocks]
set_max_delay -ignore_clock_latency 480 -from $non_clk_inputs -to [all_registers]
set_max_delay -ignore_clock_latency 480 -from [all_registers] -to [all_outputs]
set_max_delay 480 -from $non_clk_inputs -to [all_outputs]
group_path -name reg2reg -from [all_registers] -to [all_registers]
5 changes: 5 additions & 0 deletions flow/designs/gt2n/rcx-fanout-128/io.tcl
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
# Inputs on the WEST (left) edge, outputs on the EAST (right) edge, so the
# fan-out net spans the die from west to east.
set_io_pin_constraint -direction INPUT -region left:*
set_io_pin_constraint -direction OUTPUT -region right:*
16 changes: 16 additions & 0 deletions flow/designs/gt2n/rcx-fanout-16/config.mk
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# Generated by docs/rcx/gen_study.py -- do not edit by hand.
export PLATFORM = gt2n
export DESIGN_NAME = fanout_16
export DESIGN_NICKNAME = rcx-fanout-16

export VERILOG_FILES = $(DESIGN_HOME)/src/rcx-fanout/fanout_16.v
export SDC_FILE = $(DESIGN_HOME)/gt2n/rcx-fanout-16/constraint.sdc
export IO_CONSTRAINTS = $(DESIGN_HOME)/gt2n/rcx-fanout-16/io.tcl

export DIE_AREA = 0 0 150.0 12.0
export CORE_AREA = 2.0 2.0 148.0 10.0
export PLACE_DENSITY = 0.10
export MAX_ROUTING_LAYER = M5

# Tiny design: keep the run fast.
export SKIP_LAST_GASP ?= 1
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