-
Notifications
You must be signed in to change notification settings - Fork 943
Expand file tree
/
Copy patharray.ok
More file actions
321 lines (311 loc) · 13.7 KB
/
Copy patharray.ok
File metadata and controls
321 lines (311 loc) · 13.7 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
[INFO ODB-0227] LEF file: Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias
[INFO ODB-0227] LEF file: Nangate45/Nangate45_stdcell.lef, created 135 library cells
[INFO ODB-0227] LEF file: array_tile.lef, created 1 library cells
[INFO IFP-0001] Added 3528 rows of 26000 site FreePDK45_38x28_10R_NP_162NW_34O.
[INFO ODB-0303] The initial 3528 rows (91728000 sites) were cut with 225 shapes for a total of 52263 rows (14219856 sites).
[INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 4940.000 4940.000 ) um
[INFO IFP-0101] Core BBox: ( 0.000 0.000 ) ( 4940.000 4939.200 ) um
[INFO IFP-0102] Core area: 24399648.000 um^2
[INFO IFP-0103] Total instances area: 20260174.500 um^2
[INFO IFP-0104] Effective utilization: 0.830
[INFO IFP-0105] Number of instances: 2475
[INFO CTS-0050] Root buffer is BUF_X4.
[INFO CTS-0051] Sink buffer is BUF_X4.
[INFO CTS-0052] The following clock buffers will be used for CTS:
BUF_X4
[INFO CTS-0049] Characterization buffer is BUF_X4.
[INFO CTS-0007] Net "clk" found for clock "clk".
[INFO CTS-0011] Clock net "clk" for macros has 225 sinks.
[INFO CTS-0011] Clock net "clk_regs" for registers has 2250 sinks.
[INFO CTS-0008] TritonCTS found 2 clock nets.
[INFO CTS-0097] Characterization used 1 buffer(s) types.
[INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net clk.
[INFO CTS-0028] Total number of sinks: 225.
[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 600.0 um.
[INFO CTS-0030] Number of static layers: 0.
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
[INFO CTS-0204] A clustering solution was found from clustering size of 4 and clustering diameter of 600.
[INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering.
[INFO CTS-0019] Total number of sinks after clustering: 122.
[INFO CTS-0024] Normalized sink region: [(1.09571, 44.4286), (661.096, 680.704)].
[INFO CTS-0025] Width: 660.0000.
[INFO CTS-0026] Height: 636.2757.
Level 1
Direction: Horizontal
Sinks per sub-region: 61
Sub-region size: 330.0000 X 636.2757
[INFO CTS-0034] Segment length (rounded): 164.
Level 2
Direction: Vertical
Sinks per sub-region: 31
Sub-region size: 330.0000 X 318.1379
[INFO CTS-0034] Segment length (rounded): 160.
Level 3
Direction: Horizontal
Sinks per sub-region: 16
Sub-region size: 165.0000 X 318.1379
[INFO CTS-0034] Segment length (rounded): 82.
Level 4
Direction: Vertical
Sinks per sub-region: 8
Sub-region size: 165.0000 X 159.0689
[INFO CTS-0034] Segment length (rounded): 80.
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035] Number of sinks covered: 122.
[INFO CTS-0201] 225 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net clk_regs.
[INFO CTS-0028] Total number of sinks: 2250.
[INFO CTS-0029] Register sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um.
[INFO CTS-0030] Number of static layers: 0.
[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100.
[INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering.
[INFO CTS-0019] Total number of sinks after clustering: 227.
[INFO CTS-0024] Normalized sink region: [(189.626, 2.21643), (661.055, 670.416)].
[INFO CTS-0025] Width: 471.4286.
[INFO CTS-0026] Height: 668.2000.
Level 1
Direction: Vertical
Sinks per sub-region: 114
Sub-region size: 471.4286 X 334.1000
[INFO CTS-0034] Segment length (rounded): 168.
Level 2
Direction: Horizontal
Sinks per sub-region: 57
Sub-region size: 235.7143 X 334.1000
[INFO CTS-0034] Segment length (rounded): 118.
Level 3
Direction: Vertical
Sinks per sub-region: 29
Sub-region size: 235.7143 X 167.0500
[INFO CTS-0034] Segment length (rounded): 84.
Level 4
Direction: Horizontal
Sinks per sub-region: 15
Sub-region size: 117.8572 X 167.0500
[INFO CTS-0034] Segment length (rounded): 58.
Level 5
Direction: Vertical
Sinks per sub-region: 8
Sub-region size: 117.8572 X 83.5250
[INFO CTS-0034] Segment length (rounded): 42.
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035] Number of sinks covered: 227.
[INFO CTS-0018] Created 190 clock buffers.
[INFO CTS-0012] Minimum number of buffers in the clock path: 16.
[INFO CTS-0013] Maximum number of buffers in the clock path: 17.
[INFO CTS-0015] Created 190 clock nets.
[INFO CTS-0016] Fanout distribution for the current clock = 2:103, 6:1, 7:6, 8:7, 9:2..
[INFO CTS-0017] Max level of the clock tree: 4.
[INFO CTS-0018] Created 366 clock buffers.
[INFO CTS-0012] Minimum number of buffers in the clock path: 17.
[INFO CTS-0013] Maximum number of buffers in the clock path: 17.
[INFO CTS-0015] Created 366 clock nets.
[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 4:3, 5:9, 6:5, 7:4, 8:3, 9:4, 10:230..
[INFO CTS-0017] Max level of the clock tree: 5.
[INFO CTS-0098] Clock net "clk"
[INFO CTS-0099] Sinks 225
[INFO CTS-0100] Leaf buffers 103
[INFO CTS-0101] Average sink wire length 9285.18 um
[INFO CTS-0102] Path depth 16 - 17
[INFO CTS-0207] Dummy loads inserted 0
[INFO CTS-0098] Clock net "clk_regs"
[INFO CTS-0099] Sinks 2254
[INFO CTS-0100] Leaf buffers 227
[INFO CTS-0101] Average sink wire length 4121.94 um
[INFO CTS-0102] Path depth 17 - 17
[INFO CTS-0207] Dummy loads inserted 4
[INFO CTS-0033] Balancing latency for clock clk
[INFO CTS-0036] inserted 3 delay buffers
[INFO CTS-0037] Total number of delay buffers: 3
Total number of Clock Roots: 2.
Total number of Buffers Inserted: 556.
Total number of Clock Subnets: 556.
Total number of Sinks: 2475.
Cells used:
BUF_X4: 560
Dummys used:
BUF_X4: 2
INV_X1: 1
INV_X4: 1
[INFO RSZ-0058] Using max wire length 693um.
[INFO RSZ-0047] Found 40 long wires.
[INFO RSZ-0048] Inserted 88 buffers in 40 nets.
[INFO DPL-0006] Core area: 24399648.00 um^2, Instances area: 20261656.39 um^2, Utilization: 83.0%
[INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically.
[INFO DPL-1101] Legalizing using diamond search.
Movements Summary
---------------------------------------
Total cells: 2902
Diamond Move Success: 2902 (100.00%)
Diamond Move Failure: 0
Rip-up and replace Success: 0 ( 0.00% of diamond failures)
Rip-up and replace Failure: 0
Total Placement Failures: 0
---------------------------------------
Placement Analysis
---------------------------------
total displacement 3741.8 u
average displacement 1.2 u
max displacement 140.5 u
original HPWL 192183.7 u
legalized HPWL 193026.7 u
delta HPWL 0 %
Clock clk
1.03 source latency inst_12_11/clk ^
-1.17 target latency inst_13_11/clk ^
0.00 CRPR
--------------
-0.14 setup skew
Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clk (in)
0.05 0.05 ^ wire_slew7/Z (BUF_X16)
0.05 0.10 ^ wire_slew6/Z (BUF_X16)
0.06 0.15 ^ wire_length5/Z (BUF_X8)
0.03 0.18 ^ wire_slew4/Z (BUF_X16)
0.07 0.25 ^ wire_slew3/Z (BUF_X32)
0.07 0.32 ^ wire_slew2/Z (BUF_X32)
0.07 0.38 ^ wire_slew1/Z (BUF_X32)
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 0.48 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.04 0.52 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 0.59 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 0.63 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.03 0.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 0.70 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 0.73 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 0.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 0.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.84 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.03 0.91 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 1.04 ^ wire_length9/Z (BUF_X8)
0.04 1.09 ^ max_length8/Z (BUF_X8)
0.05 1.14 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
0.00 1.15 ^ inst_1_1/clk (array_tile)
0.21 1.36 ^ inst_1_1/e_out (array_tile)
0.00 1.36 ^ inst_2_1/w_in (array_tile)
1.36 data arrival time
5.00 5.00 clock clk (rise edge)
0.00 5.00 clock source latency
0.00 5.00 ^ clk (in)
0.05 5.05 ^ wire_slew7/Z (BUF_X16)
0.05 5.10 ^ wire_slew6/Z (BUF_X16)
0.06 5.15 ^ wire_length5/Z (BUF_X8)
0.03 5.18 ^ wire_slew4/Z (BUF_X16)
0.07 5.25 ^ wire_slew3/Z (BUF_X32)
0.07 5.32 ^ wire_slew2/Z (BUF_X32)
0.07 5.38 ^ wire_slew1/Z (BUF_X32)
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 5.48 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.04 5.52 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 5.59 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 5.63 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.03 5.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 5.70 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 5.73 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 5.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 5.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.84 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.03 5.91 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 6.04 ^ max_length11/Z (BUF_X8)
0.04 6.07 ^ max_length10/Z (BUF_X8)
0.02 6.10 ^ inst_2_1/clk (array_tile)
0.00 6.10 clock reconvergence pessimism
-0.05 6.05 library setup time
6.05 data required time
---------------------------------------------------------
6.05 data required time
-1.36 data arrival time
---------------------------------------------------------
4.69 slack (MET)
Startpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: inst_3_1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clk (in)
0.05 0.05 ^ wire_slew7/Z (BUF_X16)
0.05 0.10 ^ wire_slew6/Z (BUF_X16)
0.06 0.15 ^ wire_length5/Z (BUF_X8)
0.03 0.18 ^ wire_slew4/Z (BUF_X16)
0.07 0.25 ^ wire_slew3/Z (BUF_X32)
0.07 0.32 ^ wire_slew2/Z (BUF_X32)
0.07 0.38 ^ wire_slew1/Z (BUF_X32)
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 0.48 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.04 0.52 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 0.59 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 0.63 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.03 0.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 0.70 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 0.73 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 0.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 0.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.84 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.03 0.91 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 1.04 ^ max_length11/Z (BUF_X8)
0.04 1.07 ^ max_length10/Z (BUF_X8)
0.02 1.10 ^ inst_2_1/clk (array_tile)
0.21 1.31 ^ inst_2_1/e_out (array_tile)
0.00 1.31 ^ inst_3_1/w_in (array_tile)
1.31 data arrival time
5.00 5.00 clock clk (rise edge)
0.00 5.00 clock source latency
0.00 5.00 ^ clk (in)
0.05 5.05 ^ wire_slew7/Z (BUF_X16)
0.05 5.10 ^ wire_slew6/Z (BUF_X16)
0.06 5.15 ^ wire_length5/Z (BUF_X8)
0.03 5.18 ^ wire_slew4/Z (BUF_X16)
0.07 5.25 ^ wire_slew3/Z (BUF_X32)
0.07 5.32 ^ wire_slew2/Z (BUF_X32)
0.07 5.38 ^ wire_slew1/Z (BUF_X32)
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 5.48 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.04 5.52 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 5.59 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 5.63 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.03 5.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 5.70 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 5.73 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 5.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 5.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.84 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.03 5.91 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 6.04 ^ max_length11/Z (BUF_X8)
0.05 6.09 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
0.00 6.09 ^ inst_3_1/clk (array_tile)
0.00 6.09 clock reconvergence pessimism
-0.05 6.04 library setup time
6.04 data required time
---------------------------------------------------------
6.04 data required time
-1.31 data arrival time
---------------------------------------------------------
4.73 slack (MET)