test: Read flat escape slash Verilog

Restore the flat escape_slash regression coverage for read_verilog parsing of top-level escaped slash identifiers before DEF floorplan data is applied.

The test now links the minimal Verilog netlist and uses read_def -floorplan_initialize so the reduced fixture still exercises both Verilog parsing and Verilog/SPEF writing without invoking placement or CTS.

Tested: RESULTS_DIR=/workspace/exp/escape_slash_min/review_verify_flat openroad -no_init -no_splash -exit -metrics /workspace/exp/escape_slash_min/review_verify_escape_slash.metrics.json escape_slash.tcl

Tested: RESULTS_DIR=/workspace/exp/escape_slash_min/review_verify_hier openroad -no_init -no_splash -exit -metrics /workspace/exp/escape_slash_min/review_verify_escape_slash_hier.metrics.json escape_slash_hier.tcl

Tested: git diff --check

Tested: bazel test //src/dbSta/test:escape_slash-tcl_test //src/dbSta/test:escape_slash_hier-tcl_test

Co-authored-by: OmX <omx@oh-my-codex.dev>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Author: jhkim-pii

src/dbSta/test/escape_slash.ok

@@ -1,7 +1,7 @@
 [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
 [INFO ODB-0128] Design: multi_sink
-[INFO ODB-0130]     Created 1 pins.
-[INFO ODB-0131]     Created 3 components and 17 component-terminals.
-[INFO ODB-0133]     Created 2 nets and 4 connections.
+[INFO ODB-0252]     Updated 1 pins.
+[INFO ODB-0253]     Updated 3 components.
+[INFO ODB-0254]     Updated 2 nets and 4 connections.
 No differences found.
 No differences found.

src/dbSta/test/escape_slash.spefok

@@ -18,8 +18,8 @@ clk I
 
 *D_NET clk 0.213642
 *CONN
-*I hi_inst\/gclk2_inst:CK I *D CLKGATE_X1
 *P clk I
+*I hi_inst\/gclk2_inst:CK I *D CLKGATE_X1
 *CAP
 1 clk:0 0.106821
 2 clk:1 0.106821
@@ -33,9 +33,9 @@ clk I
 
 *D_NET hi_gclk2 0.430855
 *CONN
-*I hi_inst\/gclk2_inst:GCK O *D CLKGATE_X1
-*I h1\/ff1:CK I *D DFF_X1
 *I ff0\/name:CK I *D DFF_X1
+*I h1\/ff1:CK I *D DFF_X1
+*I hi_inst\/gclk2_inst:GCK O *D CLKGATE_X1
 *CAP
 1 hi_gclk2:0 0.0797636
 2 hi_gclk2:1 0.215427

src/dbSta/test/escape_slash.tcl

@@ -6,7 +6,9 @@ set test_name escape_slash
 source Nangate45/Nangate45.vars
 read_liberty Nangate45/Nangate45_typ.lib
 read_lef Nangate45/Nangate45.lef
-read_def $test_name.def
+read_verilog $test_name.v
+link_design multi_sink
+read_def -floorplan_initialize $test_name.def
 
 source Nangate45/Nangate45.rc
 source $layer_rc_file