Merge branch 'master' into mbff_hier_issue

Author: dsengupta0628

BUILD.bazel

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright (c) 2025-2025, The OpenROAD Authors
 
+load("@bazel_skylib//rules:build_test.bzl", "build_test")
 load("@bazel_skylib//rules:common_settings.bzl", "string_flag")
 load("@rules_cc//cc:cc_binary.bzl", "cc_binary")
 load("@rules_cc//cc:cc_library.bzl", "cc_library")
@@ -98,6 +99,7 @@ OPENROAD_LIBRARY_DEPS = [
     "//src/exa:ui",
     "//src/fin",
     "//src/gpl",
+    "//src/gpl:ui",
     "//src/grt",
     "//src/grt:ui",
     "//src/ifp",
@@ -138,12 +140,7 @@ OPENROAD_LIBRARY_DEPS = [
     "//src/web:ui",
     "@abc",
     ":ord",
-] + select(
-    {
-        ":platform_cli": ["//src/gui"],
-        ":platform_gui": ["//src/gui:gui_qt"],
-    },
-)
+]
 
 # Flags applied to top-level OpenROAD targets only. Flags that apply
 # globally to every cc_* target (-Wall, -Wextra, -Wno-sign-compare,
@@ -190,46 +187,113 @@ cc_library(
     ],
 )
 
+# Deps shared by :openroad and :openroad-qt. Kept as a Starlark list
+# rather than a cc_library wrapper because layering_check is enabled
+# package-wide: a deps-only cc_library does not re-export its deps'
+# headers to consumers, so direct binary deps are what each Main.cc
+# include needs to see.
+OPENROAD_MAIN_DEPS = [
+    ":openroad_version",
+    ":opt_notification",
+    ":ord",
+    ":tcl_readline_setup",
+    "//bazel:tcl_library_init",
+    "//src/cut",
+    "//src/sta:opensta_lib",
+    "//src/utl",
+    "//src/web",
+    "@abseil-cpp//absl/base:no_destructor",
+    "@boost.stacktrace",
+    "@rules_cc//cc/runfiles",  # sets BAZEL_CURRENT_REPOSITORY
+    "@tcl_lang//:tcl",
+]
+
 cc_binary(
     name = "openroad",
     srcs = [
         "src/Main.cc",
     ],
     copts = OPENROAD_COPTS,
+    defines = OPENROAD_DEFINES,
     features = ["-use_header_modules"],
     malloc = select({
         "@platforms//os:linux": "@tcmalloc//tcmalloc",
         "@platforms//os:macos": "@bazel_tools//tools/cpp:malloc",
     }),
     visibility = ["//visibility:public"],
+    deps = OPENROAD_MAIN_DEPS + select(
+        {
+            ":platform_cli": [
+                ":openroad_lib",
+                "//src/gui",
+                "//src/gui:gui_stub",
+            ],
+            ":platform_gui": [
+                ":openroad_lib_qt",
+                "//src/gui:gui_qt",
+            ],
+        },
+    ),
+)
+
+# Qt GUI variant. Build explicitly when the interactive GUI is wanted:
+#   bazelisk build //:openroad-qt
+# Additive to the existing `--//:platform=gui //:openroad` flag path —
+# this target is preferable for ad-hoc GUI builds because it does not
+# invalidate `:openroad`'s cache the way flipping the flag does.
+cc_binary(
+    name = "openroad-qt",
+    srcs = [
+        "src/Main.cc",
+    ],
+    copts = OPENROAD_COPTS,
+    defines = OPENROAD_DEFINES,
+    features = ["-use_header_modules"],
+    malloc = select({
+        "@platforms//os:linux": "@tcmalloc//tcmalloc",
+        "@platforms//os:macos": "@bazel_tools//tools/cpp:malloc",
+    }),
+    visibility = ["//visibility:public"],
+    deps = OPENROAD_MAIN_DEPS + [
+        ":openroad_lib_qt",
+        "//src/gui:gui_qt",
+    ],
+)
+
+# CLI variant: the default. What downstream rule libraries pull as a
+# build-time tool, and what `bazelisk build //:openroad` produces.
+cc_library(
+    name = "openroad_lib",
+    srcs = [
+        "src/Design.cc",
+        "src/OpenRoad.cc",
+        "src/Tech.cc",
+        "src/Timing.cc",
+        ":openroad_swig",
+        ":openroad_tcl",
+    ],
+    copts = OPENROAD_COPTS,
+    defines = OPENROAD_DEFINES + ["BUILD_GUI=false"],
+    features = ["-use_header_modules"],
+    includes = [
+        "include",
+    ],
+    visibility = ["//:__subpackages__"],
     deps = [
-        ":openroad_lib",
-        ":openroad_version",
-        ":opt_notification",
-        ":ord",
-        ":tcl_readline_setup",
-        "//bazel:tcl_library_init",
-        "//src/cut",
         "//src/gui",
         "//src/sta:opensta_lib",
-        "//src/utl",
-        "//src/web",
-        "@abseil-cpp//absl/base:no_destructor",
+        "@abseil-cpp//absl/base:core_headers",
+        "@abseil-cpp//absl/synchronization",
         "@boost.stacktrace",
-        "@rules_cc//cc/runfiles",  # sets BAZEL_CURRENT_REPOSITORY
         "@tcl_lang//:tcl",
-    ],
-)
-
-GUI_BUILD_FLAGS = select(
-    {
-        ":platform_cli": ["BUILD_GUI=false"],
-        ":platform_gui": ["BUILD_GUI=true"],
-    },
+    ] + OPENROAD_LIBRARY_DEPS,
 )
 
+# Qt variant: same sources, linked against the Qt GUI implementation.
+# Used by :openroad-qt, and by :openroad when --//:platform=gui is set.
+# Compiled separately (different `BUILD_GUI` define + different gui dep).
 cc_library(
-    name = "openroad_lib",
+    name = "openroad_lib_qt",
     srcs = [
         "src/Design.cc",
         "src/OpenRoad.cc",
@@ -239,13 +303,14 @@ cc_library(
         ":openroad_tcl",
     ],
     copts = OPENROAD_COPTS,
-    defines = OPENROAD_DEFINES + GUI_BUILD_FLAGS,
+    defines = OPENROAD_DEFINES + ["BUILD_GUI=true"],
     features = ["-use_header_modules"],
     includes = [
         "include",
     ],
     visibility = ["//:__subpackages__"],
     deps = [
+        "//src/gui:gui_qt",
         "//src/sta:opensta_lib",
         "@abseil-cpp//absl/base:core_headers",
         "@abseil-cpp//absl/synchronization",
@@ -347,6 +412,7 @@ cc_binary(
         "//src/gpl",
         "//src/grt",
         "//src/gui",
+        "//src/gui:gui_stub",
         "//src/ifp",
         "//src/odb/src/db",
         "//src/par",
@@ -478,6 +544,14 @@ sh_test(
     tags = ["local"],
 )
 
+# Make sure the Qt GUI variant keeps building. :openroad is exercised by
+# downstream rule libraries that pull it as a tool; :openroad-qt has no
+# such consumer in CI, so a build_test pins its compilability.
+build_test(
+    name = "openroad_qt_build_test",
+    targets = [":openroad-qt"],
+)
+
 # ---------------------------------------------------------------------------
 # Lint & tidy targets
 #

src/cts/src/TritonCTS.cpp

@@ -1456,11 +1456,16 @@ bool TritonCTS::separateMacroRegSinks(
     std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& registerSinks,
     std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& macroSinks)
 {
+  odb::dbInst* skippedTimingBuf = nullptr;
+
   for (odb::dbITerm* iterm : net->getITerms()) {
     odb::dbInst* inst = iterm->getInst();
 
-    if (buffer_masters.find(inst->getMaster()) != buffer_masters.end()
-        && inst->getSourceType() == odb::dbSourceType::TIMING) {
+    const bool isTimingBuffer
+        = buffer_masters.find(inst->getMaster()) != buffer_masters.end()
+          && inst->getSourceType() == odb::dbSourceType::TIMING;
+
+    if (iterm->isOutputSignal() && isTimingBuffer) {
       logger_->warn(CTS,
                     105,
                     "Net \"{}\" already has clock buffer {}. Skipping...",
@@ -1469,6 +1474,12 @@ bool TritonCTS::separateMacroRegSinks(
       return false;
     }
 
+    // TIMING buffer sinks are traversed via initOneClockTree, not as sinks.
+    if (iterm->isInputSignal() && isTimingBuffer) {
+      skippedTimingBuf = inst;
+      continue;
+    }
+
     if (iterm->isInputSignal() && inst->isPlaced()) {
       // Cells with insertion delay, macros, clock gaters and inverters that
       // drive macros are put in the macro sinks.
@@ -1490,6 +1501,14 @@ bool TritonCTS::separateMacroRegSinks(
       }
     }
   }
+  if (skippedTimingBuf && (registerSinks.size() + macroSinks.size()) < 2) {
+    logger_->warn(CTS,
+                  110,
+                  "Net \"{}\" already has clock buffer {}. Skipping...",
+                  clockNet.getName(),
+                  skippedTimingBuf->getName());
+    return false;
+  }
 
   return true;
 }

src/cts/test/BUILD

@@ -14,6 +14,7 @@ COMPULSORY_TESTS = [
     "array_max_wl",
     "array_no_blockages",
     "array_repair_clock_nets",
+    "buffer_ports",
     "check_buffers",
     "check_buffers_blockages",
     "check_buffers_blockages_merge",

src/cts/test/CMakeLists.txt

@@ -9,6 +9,7 @@ or_integration_tests(
     array_max_wl
     array_no_blockages
     array_repair_clock_nets
+    buffer_ports
     check_buffers
     check_buffers_blockages
     colocated_sinks

src/cts/test/buffer_ports.ok

@@ -0,0 +1,113 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO IFP-0001] Added 714 rows of 5263 site FreePDK45_38x28_10R_NP_162NW_34O.
+[INFO IFP-0100] Die BBox:  (  0.000  0.000 ) ( 1000.000 1000.000 ) um
+[INFO IFP-0101] Core BBox: (  0.000  0.000 ) ( 999.970 999.600 ) um
+[INFO IFP-0102] Core area:                       999570.012 um^2
+[INFO IFP-0103] Total instances area:               111.454 um^2
+[INFO IFP-0104] Effective utilization:                0.000
+[INFO IFP-0105] Number of instances:                     68
+[INFO RSZ-0026] Removed 5 buffers.
+[INFO RSZ-0027] Inserted 9 BUF_X1 input buffers.
+[INFO RSZ-0028] Inserted 9 BUF_X1 output buffers.
+Found 0 macro blocks.
+Using 2 tracks default min distance between IO pins.
+[INFO PPL-0001] Number of available slots 12380
+[INFO PPL-0002] Number of I/O             19
+[INFO PPL-0003] Number of I/O w/sink      19
+[INFO PPL-0004] Number of I/O w/o sink    0
+[INFO PPL-0005] Slots per section         200
+[INFO PPL-0008] Successfully assigned pins to sections.
+[INFO PPL-0012] I/O nets HPWL: 1057.01 um.
+[INFO GPL-0001] ---- Initialize GPL Main Data Structures
+[INFO GPL-0002] DBU: 2000
+[INFO GPL-0003] SiteSize: (  0.190  1.400 ) um
+[INFO GPL-0004] CoreBBox: (  0.000  0.000 ) ( 999.970 999.600 ) um
+[INFO GPL-0036] Movable instances area:        121.562 um^2
+[INFO GPL-0037] Total instances area:          121.562 um^2
+[INFO GPL-0035] Pin density area adjust:         7.987 um^2
+[INFO GPL-0032] ---- Initialize Region: Top-level
+[INFO GPL-0006] Number of instances:                81
+[INFO GPL-0007] Movable instances:                  81
+[INFO GPL-0008] Fixed instances:                     0
+[INFO GPL-0009] Dummy instances:                     0
+[INFO GPL-0010] Number of nets:                    107
+[INFO GPL-0011] Number of pins:                    281
+[INFO GPL-0012] Die BBox:  (  0.000  0.000 ) ( 1000.000 1000.000 ) um
+[INFO GPL-0013] Core BBox: (  0.000  0.000 ) ( 999.970 999.600 ) um
+[INFO GPL-0016] Core area:                  999570.012 um^2
+[INFO GPL-0014] Region name: top-level.
+[INFO GPL-0015] Region area:                999570.012 um^2
+[INFO GPL-0017] Fixed instances area:            0.000 um^2
+[INFO GPL-0018] Movable instances area:        129.549 um^2
+[INFO GPL-0019] Utilization:                     0.013 %
+[INFO GPL-0020] Standard cells area:           129.549 um^2
+[INFO GPL-0021] Large instances area:            0.000 um^2
+[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
+[INFO GPL-0051] Source of initial instance position counters:
+	Odb location = 18	Core center = 63	Region center = 0
+[InitialPlace]  Iter: 1 conjugate gradient residual: 0.00000006 HPWL: 1722700
+[InitialPlace]  Iter: 2 conjugate gradient residual: 0.00000005 HPWL: 8121024
+[InitialPlace]  Iter: 3 conjugate gradient residual: 0.00000011 HPWL: 2164788
+[InitialPlace]  Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 1701248
+[InitialPlace]  Iter: 5 conjugate gradient residual: 0.00000007 HPWL: 1688200
+[INFO DPL-0006] Core area: 999570.01 um^2, Instances area: 121.56 um^2, Utilization: 0.0%
+[INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically.
+[INFO DPL-1101] Legalizing using diamond search.
+Movements Summary
+---------------------------------------
+Total cells:                      81
+Diamond Move Success:             81 (100.00%)
+Diamond Move Failure:              0
+Rip-up and replace Success:        0 (  0.00% of diamond failures)
+Rip-up and replace Failure:        0
+Total Placement Failures:          0
+---------------------------------------
+Placement Analysis
+---------------------------------
+total displacement        798.6 u
+average displacement        9.9 u
+max displacement           13.0 u
+original HPWL             573.2 u
+legalized HPWL           1628.1 u
+delta HPWL                  184 %
+
+[INFO CTS-0050] Root buffer is BUF_X1.
+[INFO CTS-0051] Sink buffer is BUF_X1.
+[INFO CTS-0052] The following clock buffers will be used for CTS:
+                    BUF_X1
+[INFO CTS-0049] Characterization buffer is BUF_X1.
+[INFO CTS-0007] Net "clk" found for clock "core".
+[INFO CTS-0010]  Clock net "clk" has 9 sinks.
+[WARNING CTS-0105] Net "clk_out" already has clock buffer output10. Skipping...
+[INFO CTS-0008] TritonCTS found 1 clock nets.
+[INFO CTS-0097] Characterization used 1 buffer(s) types.
+[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
+[INFO CTS-0027] Generating H-Tree topology for net clk.
+[INFO CTS-0028]  Total number of sinks: 9.
+[INFO CTS-0090]  Sinks will be clustered based on buffer max cap.
+[INFO CTS-0030]  Number of static layers: 1.
+[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
+[INFO CTS-0021]  Distance between buffers: 7 units (100 um).
+[INFO CTS-0023]  Original sink region: [(3230, 1230), (10890, 18025)].
+[INFO CTS-0024]  Normalized sink region: [(0.230714, 0.0878571), (0.777857, 1.2875)].
+[INFO CTS-0025]     Width:  0.5471.
+[INFO CTS-0026]     Height: 1.1996.
+ Level 1
+    Direction: Vertical
+    Sinks per sub-region: 5
+    Sub-region size: 0.5471 X 0.5998
+[INFO CTS-0034]     Segment length (rounded): 1.
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 9.
+[INFO CTS-0018]     Created 3 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 3 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 4:1, 5:1..
+[INFO CTS-0017]     Max level of the clock tree: 1.
+[INFO CTS-0098] Clock net "clk"
+[INFO CTS-0099]  Sinks 10
+[INFO CTS-0100]  Leaf buffers 0
+[INFO CTS-0101]  Average sink wire length 506.70 um
+[INFO CTS-0102]  Path depth 2 - 2
+[INFO CTS-0207]  Dummy loads inserted 1

src/cts/test/buffer_ports.sdc

@@ -0,0 +1,6 @@
+current_design clk_passthrough_top
+set clk_period 500
+create_clock -name clk -period $clk_period [get_ports clk]
+set_input_delay [expr $clk_period * 0.2] -clock clk [all_inputs -no_clocks]
+set_output_delay [expr $clk_period * 0.2] -clock clk [all_outputs]
+set_false_path -from [get_ports reset]